Contribution of PowerPC port (continuation of 422063005)

src/base/cpu.h

Index: src/base/cpu.h
diff --git a/src/base/cpu.h b/src/base/cpu.h
index fe8e1029757f0d37806247366b307eb3e3c13ad7..36b60acbc31d806d660681421ce960f265fdb3ab 100644
--- a/src/base/cpu.h
+++ b/src/base/cpu.h
@@ -48,6 +48,9 @@ class CPU FINAL {
   static const int QUALCOMM = 0x51;
   int architecture() const { return architecture_; }
   int part() const { return part_; }
+  int cache_line_size() const { return cache_line_size_; }

[Sven Panne, 2015/01/08 10:13:53]

We need to be more specific here *which* kind of cache we refer to (I or D), see
cpu-arm64.cc. You basically have 2 options:

  * Hide the cache line size handling in cpu-ppc.cc, just like cpu-arm64.cc. We
can then later handle this in a unified way in the CPU class and remember it in
CpuFeatures.

   * Do the unification already now.

As it is, it makes things more confusing, because we are half-way between those
options.

[michael_dawson, 2015/01/08 23:51:11]

This change is an optimization only needed for some ppc processors, as such I'd
like to leave it out of this set of changes for the port and we can contribute
in a later change were we can figure out which of the options is the way to go. 
I'll remove it from the next patch

+
+  // ARM-specific part codes
   static const int ARM_CORTEX_A5 = 0xc05;
   static const int ARM_CORTEX_A7 = 0xc07;
   static const int ARM_CORTEX_A8 = 0xc08;
@@ -55,6 +58,17 @@ class CPU FINAL {
   static const int ARM_CORTEX_A12 = 0xc0c;
   static const int ARM_CORTEX_A15 = 0xc0f;
 
+  // PPC-specific part codes
+  enum {
+    PPC_POWER5,
+    PPC_POWER6,
+    PPC_POWER7,
+    PPC_POWER8,
+    PPC_G4,
+    PPC_G5,
+    PPC_PA6T
+  };
+
   // General features
   bool has_fpu() const { return has_fpu_; }
 
@@ -93,6 +107,7 @@ class CPU FINAL {
   int implementer_;
   int architecture_;
   int part_;
+  int cache_line_size_;
   bool has_fpu_;
   bool has_cmov_;
   bool has_sahf_;