Speed up x86-64 validator by inlining heavily called routines. Speeds up

src/trusted/validator/x86/ncval_reg_sfi/nc_protect_base.c

 /*
  * Copyright (c) 2011 The Native Client Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 /* nc_protect_base.h - For 64-bit mode, verifies that no instruction
  * changes the value of the base register, that the invariant between
  * RSP and RBP is maintained, and that segment registers are not set.
  */
 #include <assert.h>
 
 #include "native_client/src/trusted/validator/x86/ncval_reg_sfi/nc_protect_base.h"
 
 #include "native_client/src/shared/platform/nacl_log.h"
-#include "native_client/src/trusted/validator/x86/decoder/ncop_exps.h"
-#include "native_client/src/trusted/validator/x86/decoder/nc_inst_iter.h"
 #include "native_client/src/trusted/validator/x86/decoder/nc_inst_state_internal.h"
 #include "native_client/src/trusted/validator/x86/decoder/nc_inst_trans.h"
 #include "native_client/src/trusted/validator/x86/ncval_reg_sfi/ncvalidate_iter.h"
 #include "native_client/src/trusted/validator/x86/ncval_reg_sfi/ncvalidate_iter_internal.h"
 #include "native_client/src/trusted/validator/x86/ncval_reg_sfi/ncvalidate_utils.h"
 #include "native_client/src/trusted/validator/x86/ncval_reg_sfi/nc_jumps.h"
 
 /* To turn on debugging of instruction decoding, change value of
  * DEBUGGING to 1.
  */
 #define DEBUGGING 0
 
 #include "native_client/src/shared/utils/debugging.h"
 
+#include "native_client/src/trusted/validator/x86/decoder/ncopcode_desc_inl.c"
+#include "native_client/src/trusted/validator/x86/decoder/ncop_exps_inl.c"
+#include "native_client/src/trusted/validator/x86/decoder/nc_inst_iter_inl.c"
+
 /* Defines locals used by the NaClBaseRegisterValidator to
  * record registers set in the current instruction, that are
  * a problem if not used correctly in the next instruction.
  */
 typedef struct NaClRegisterLocals {
   /* Points to an instruction that contains an assignment to register ESP,
    * or NULL if the instruction doesn't set ESP. This is done so that we
    * can check if the next instruction uses the value of ESP to update RSP
    * (if not, we need to report that ESP is incorrectly assigned).
    */
@@ skipping 92 matching lines @@
 }
 
 /* Returns true if the instruction is of the form
  *   OP %esp, C
  * where OP in { add , sub } and C is a 32 bit constant.
  */
 static Bool NaClIsAddOrSubBoundedConstFromEsp(NaClInstState* state) {
   const NaClInst* inst = NaClInstStateInst(state);
   NaClExpVector* vector = NaClInstStateExpVector(state);
   return (InstAdd == inst->name || InstSub == inst->name) &&
-      2 == NaClGetInstNumberOperands(inst) &&
+      2 == NaClGetInstNumberOperandsInline(inst) &&
       /* Note: Since the vector contains a list of operand expressions, the
        * first operand reference is always at index zero, and its first child
        * (where the register would be defined) is at index 1.
        */
       ExprRegister == vector->node[1].kind &&
-      RegESP == NaClGetExpRegister(&vector->node[1]) &&
+      RegESP == NaClGetExpRegisterInline(&vector->node[1]) &&
       /* Note: Since the first subtree is a register operand, it uses
        * nodes 0 and 1 in the vector (node 0 is the operand reference, and
        * node 1 is its child defining a register value). The second operand
        * reference therefore lies at node 2, and if the operand is defined by
        * a 32 bit constant, it is the first kid of node 2, which is node 3.
        */
       ExprConstant == vector->node[3].kind;
 }
 
 /* Returns true iff the instruction of form "lea _, [%reg+%rbase*1]" */
 static Bool NaClIsLeaAddressRegPlusRbase(NaClValidatorState* state,
                                          NaClInstState* inst_state,
                                          NaClOpKind reg) {
   const NaClInst* inst = NaClInstStateInst(inst_state);
   assert((RegRSP == reg) || (RegRBP == reg));
   if (InstLea == inst->name &&
-      2 == NaClGetInstNumberOperands(inst)) {
+      2 == NaClGetInstNumberOperandsInline(inst)) {
     NaClExpVector* vector = NaClInstStateExpVector(inst_state);
     int op2_index =
         NaClGetExpKidIndex(vector,
                            NaClGetNthExpKind(vector, OperandReference, 2),
                            0);
     NaClExp* op2 = &(vector->node[op2_index]);
     /* Only allow memory offset nodes with address size 64. */
     if (ExprMemOffset == op2->kind &&
         NACL_EMPTY_EFLAGS != (op2->flags & NACL_EFLAG(ExprSize64))) {
       int base_reg_index = op2_index + 1;
@@ skipping 30 matching lines @@
  * the corresponding 32-bit retister.
  */
 
 static Bool NaClAcceptRegMoveLea32To64(struct NaClValidatorState* state,
                                        struct NaClInstIter* iter,
                                        const NaClInst* inst,
                                        NaClOpKind reg) {
   NaClInstState* inst_state = state->cur_inst_state;
   assert((RegRSP == reg) || (RegRBP == reg));
   if (NaClOperandOneIsRegisterSet(inst_state, reg) &&
-      NaClInstIterHasLookbackState(iter, 1)) {
-    NaClInstState* prev_inst = NaClInstIterGetLookbackState(iter, 1);
+      NaClInstIterHasLookbackStateInline(iter, 1)) {
+    NaClInstState* prev_inst = NaClInstIterGetLookbackStateInline(iter, 1);
     if (NaClAssignsRegisterWithZeroExtends(
             prev_inst, NaClGet32For64BitReg(reg)) &&
         NaClIsLeaAddressRegPlusRbase(state, inst_state, reg)) {
       DEBUG(const char* reg_name = NaClOpKindName(reg);
             printf("nc protect base for 'lea %s. [%s, rbase]'\n",
                    reg_name, reg_name));
       NaClMarkInstructionJumpIllegal(state, inst_state);
       return TRUE;
     }
   }
@@ skipping 86 matching lines @@
       if (i == 3) return;
       break;
     case InstOr:
     case InstAdd:
       {
         /* case 2/4 (depending on instruction name). */
         if (NaClIsBinarySetUsingRegisters(
                 state->decoder_tables,
                 inst, inst_name, vector, RegRSP,
                 state->base_register) &&
-            NaClInstIterHasLookbackState(iter, 1)) {
+            NaClInstIterHasLookbackStateInline(iter, 1)) {
           NaClInstState* prev_inst =
-              NaClInstIterGetLookbackState(iter, 1);
+              NaClInstIterGetLookbackStateInline(iter, 1);
           if (NaClAssignsRegisterWithZeroExtends(prev_inst, RegESP)
               || (inst_name == InstAdd &&
                   NaClIsAddOrSubBoundedConstFromEsp(prev_inst))) {
             /* Found that the assignment to ESP in previous instruction
              * is legal, so long as the two instructions are atomic.
              */
             DEBUG(printf("nc protect esp for zero extend, or or/add "
                          "constant\n"));
             NaClMarkInstructionJumpIllegal(state, inst_state);
             locals->buffer[locals->previous_index].esp_set_inst = NULL;
@@ skipping 75 matching lines @@
    *
    *     Note: We require the scale to be 1, and rbase be in
    *     the index position.
    */
   NaClInstState* inst_state = state->cur_inst_state;
   const NaClInst* inst = state->cur_inst;
   NaClMnemonic inst_name = inst->name;
   NaClExpVector* vector = state->cur_inst_vector;
   switch (inst_name) {
     case InstAdd:
-      if (NaClInstIterHasLookbackState(iter, 1)) {
+      if (NaClInstIterHasLookbackStateInline(iter, 1)) {
         NaClInstState* prev_state =
-            NaClInstIterGetLookbackState(iter, 1);
+            NaClInstIterGetLookbackStateInline(iter, 1);
         if (NaClIsBinarySetUsingRegisters(
                 state->decoder_tables,
                 inst, InstAdd, vector,
                 RegRBP, state->base_register) &&
             NaClAssignsRegisterWithZeroExtends(
                 prev_state, RegEBP)) {
           /* case 2. */
           NaClMarkInstructionJumpIllegal(state, inst_state);
           locals->buffer[locals->previous_index].ebp_set_inst = NULL;
           return;
@@ skipping 56 matching lines @@
   NaClExpVector* vector = state->cur_inst_vector;
 
   DEBUG(NaClValidatorInstMessage(
       LOG_INFO, state, inst_state, "Checking base registers...\n"));
 
   /* Look for assignments to registers. */
   for (i = 0; i < vector->number_expr_nodes; ++i) {
     NaClExp* node = &vector->node[i];
     if (ExprRegister == node->kind) {
       if (node->flags & NACL_EFLAG(ExprSet)) {
-        NaClOpKind reg_name = NaClGetExpRegister(node);
+        NaClOpKind reg_name = NaClGetExpRegisterInline(node);
 
         /* If reached, found an assignment to a register.
          * Check if its one that we care about (i.e.
          * the base register (RBASE), RSP, RBP, or segment register).
          */
         if (reg_name == state->base_register) {
           NaClValidatorInstMessage(
               LOG_ERROR, state, inst_state,
               "Illegal to change the value of register %s\n",
               NaClOpKindName(state->base_register));
@@ skipping 41 matching lines @@
    */
   NaClMaybeReportPreviousBad(state, locals);
 }
 
 void NaClBaseRegisterSummarize(struct NaClValidatorState* state,
                              struct NaClInstIter* iter,
                              struct NaClBaseRegisterLocals* locals) {
   /* Check if problems in last instruction of segment. */
   NaClMaybeReportPreviousBad(state, locals);
 }