Fix MIPS assembler test.

runtime/vm/assembler_mips_test.cc

Index: runtime/vm/assembler_mips_test.cc
===================================================================
--- runtime/vm/assembler_mips_test.cc	(revision 42734)
+++ runtime/vm/assembler_mips_test.cc	(working copy)
@@ -1643,9 +1643,11 @@
   __ AddImmediate(SP, -8 * kWordSize);

[regis, 2015/01/09 17:16:02]

Why 8*kWordSize?
A double is 2*kWordSize, alignment requires an additional kWordSize, so
3*kWordSize should do.

   __ LoadImmediate(T1, ~(8 - 1));
   __ and_(T0, SP, T1);  // Need 8 byte alignment.
+  __ AddImmediate(T0, T0, 2 * kWordSize);

[regis, 2015/01/09 17:16:02]

This may work with 8*kWordSize above, but this is not necessary, and definitely
wrong with 3*kWordSize.

   __ LoadImmediate(D1, 1.0);
   __ sdc1(D1, Address(T0));
   __ ldc1(D0, Address(T0));
+  __ AddImmediate(SP, 8 * kWordSize);

[regis, 2015/01/09 17:16:02]

3*kWordSize?

It is only a test and efficiency is not important, but I find it hard to read. I
would have worked with SP directly:

mov T0, SP  // Save SP
addiu SP, -3*kWordSize
andi SP, 7
... use SP as base for sdc1 and ldc1 ...
mov SP, T0

[zra, 2015/01/09 17:49:28]

Changed to something like this.

   __ Ret();
 }