Fix MIPS assembler test.

runtime/vm/assembler_mips_test.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_MIPS)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/os.h"
@@ skipping 1622 matching lines @@
 
 ASSEMBLER_TEST_RUN(Movd, test) {
   typedef double (*SimpleCode)() DART_UNUSED;
   EXPECT(test != NULL);
   double res = EXECUTE_TEST_CODE_DOUBLE(SimpleCode, test->entry());
   EXPECT_FLOAT_EQ(1.0, res, 0.001);
 }
 
 
 ASSEMBLER_TEST_GENERATE(Sdc1Ldc1, assembler) {
   __ AddImmediate(SP, -8 * kWordSize);

[regis, 2015/01/09 17:16:02]

Why 8*kWordSize?
A double is 2*kWordSize, alignment requires an additional kWordSize, so
3*kWordSize should do.

   __ LoadImmediate(T1, ~(8 - 1));
   __ and_(T0, SP, T1);  // Need 8 byte alignment.
+  __ AddImmediate(T0, T0, 2 * kWordSize);

[regis, 2015/01/09 17:16:02]

This may work with 8*kWordSize above, but this is not necessary, and definitely
wrong with 3*kWordSize.

   __ LoadImmediate(D1, 1.0);
   __ sdc1(D1, Address(T0));
   __ ldc1(D0, Address(T0));
+  __ AddImmediate(SP, 8 * kWordSize);

[regis, 2015/01/09 17:16:02]

3*kWordSize?

It is only a test and efficiency is not important, but I find it hard to read. I
would have worked with SP directly:

mov T0, SP  // Save SP
addiu SP, -3*kWordSize
andi SP, 7
... use SP as base for sdc1 and ldc1 ...
mov SP, T0

[zra, 2015/01/09 17:49:28]

Changed to something like this.

   __ Ret();
 }
 
 
 ASSEMBLER_TEST_RUN(Sdc1Ldc1, test) {
   typedef double (*SimpleCode)() DART_UNUSED;
   EXPECT(test != NULL);
   double res = EXECUTE_TEST_CODE_DOUBLE(SimpleCode, test->entry());
   EXPECT_FLOAT_EQ(1.0, res, 0.001);
 }
@@ skipping 489 matching lines @@
 
   EXPECT_EQ(-1, RANGE_OF(Bool::True().raw()));
 
 #undef RANGE_OF
 }
 
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_MIPS