Process two 32-bit digits as one 64-bit digit in bigint absAdd intrinsic on x64.

runtime/vm/assembler_x64.cc

Index: runtime/vm/assembler_x64.cc
===================================================================
--- runtime/vm/assembler_x64.cc	(revision 41808)
+++ runtime/vm/assembler_x64.cc	(working copy)
@@ -1917,6 +1917,35 @@
 }
 
 
+void Assembler::adcq(Register dst, Register src) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  Operand operand(src);
+  EmitOperandREX(dst, operand, REX_W);
+  EmitUint8(0x13);
+  EmitOperand(dst & 7, operand);
+}
+
+
+void Assembler::adcq(Register dst, const Immediate& imm) {
+  if (imm.is_int32()) {
+    AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+    EmitRegisterREX(dst, REX_W);
+    EmitComplex(2, Operand(dst), imm);
+  } else {
+    movq(TMP, imm);
+    adcq(dst, TMP);
+  }
+}
+
+
+void Assembler::adcq(Register dst, const Address& address) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitOperandREX(dst, address, REX_W);
+  EmitUint8(0x13);
+  EmitOperand(dst & 7, address);
+}
+
+
 void Assembler::subl(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(src);
@@ -2118,6 +2147,35 @@
 }
 
 
+void Assembler::sbbq(Register dst, Register src) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  Operand operand(src);
+  EmitOperandREX(dst, operand, REX_W);
+  EmitUint8(0x1B);
+  EmitOperand(dst & 7, operand);
+}
+
+
+void Assembler::sbbq(Register dst, const Immediate& imm) {
+  if (imm.is_int32()) {
+    AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+    EmitRegisterREX(dst, REX_W);
+    EmitComplex(3, Operand(dst), imm);
+  } else {
+    movq(TMP, imm);
+    sbbq(dst, TMP);
+  }
+}
+
+
+void Assembler::sbbq(Register dst, const Address& address) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitOperandREX(dst, address, REX_W);
+  EmitUint8(0x1B);
+  EmitOperand(dst & 7, address);
+}
+
+
 void Assembler::shll(Register reg, const Immediate& imm) {
   EmitGenericShift(false, 4, reg, imm);
 }