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Side by Side Diff: runtime/vm/assembler_x64.cc

Issue 732663003: Process two 32-bit digits as one 64-bit digit in bigint absAdd intrinsic on x64. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 6 years, 1 month ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" 5 #include "vm/globals.h"
6 #if defined(TARGET_ARCH_X64) 6 #if defined(TARGET_ARCH_X64)
7 7
8 #include "vm/assembler.h" 8 #include "vm/assembler.h"
9 #include "vm/cpu.h" 9 #include "vm/cpu.h"
10 #include "vm/heap.h" 10 #include "vm/heap.h"
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1910 1910
1911 1911
1912 void Assembler::addq(const Address& address, Register src) { 1912 void Assembler::addq(const Address& address, Register src) {
1913 AssemblerBuffer::EnsureCapacity ensured(&buffer_); 1913 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1914 EmitOperandREX(src, address, REX_W); 1914 EmitOperandREX(src, address, REX_W);
1915 EmitUint8(0x01); 1915 EmitUint8(0x01);
1916 EmitOperand(src & 7, address); 1916 EmitOperand(src & 7, address);
1917 } 1917 }
1918 1918
1919 1919
1920 void Assembler::adcq(Register dst, Register src) {
1921 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1922 Operand operand(src);
1923 EmitOperandREX(dst, operand, REX_W);
1924 EmitUint8(0x13);
1925 EmitOperand(dst & 7, operand);
1926 }
1927
1928
1929 void Assembler::adcq(Register dst, const Immediate& imm) {
1930 if (imm.is_int32()) {
1931 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1932 EmitRegisterREX(dst, REX_W);
1933 EmitComplex(2, Operand(dst), imm);
1934 } else {
1935 movq(TMP, imm);
1936 adcq(dst, TMP);
1937 }
1938 }
1939
1940
1941 void Assembler::adcq(Register dst, const Address& address) {
1942 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1943 EmitOperandREX(dst, address, REX_W);
1944 EmitUint8(0x13);
1945 EmitOperand(dst & 7, address);
1946 }
1947
1948
1920 void Assembler::subl(Register dst, Register src) { 1949 void Assembler::subl(Register dst, Register src) {
1921 AssemblerBuffer::EnsureCapacity ensured(&buffer_); 1950 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
1922 Operand operand(src); 1951 Operand operand(src);
1923 EmitOperandREX(dst, operand, REX_NONE); 1952 EmitOperandREX(dst, operand, REX_NONE);
1924 EmitUint8(0x2B); 1953 EmitUint8(0x2B);
1925 EmitOperand(dst & 7, operand); 1954 EmitOperand(dst & 7, operand);
1926 } 1955 }
1927 1956
1928 1957
1929 void Assembler::subl(Register dst, const Address& address) { 1958 void Assembler::subl(Register dst, const Address& address) {
(...skipping 181 matching lines...) Expand 10 before | Expand all | Expand 10 after
2111 AssemblerBuffer::EnsureCapacity ensured(&buffer_); 2140 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2112 EmitOperandREX(0, address, REX_W); 2141 EmitOperandREX(0, address, REX_W);
2113 EmitComplex(5, Operand(address), imm); 2142 EmitComplex(5, Operand(address), imm);
2114 } else { 2143 } else {
2115 movq(TMP, imm); 2144 movq(TMP, imm);
2116 subq(address, TMP); 2145 subq(address, TMP);
2117 } 2146 }
2118 } 2147 }
2119 2148
2120 2149
2150 void Assembler::sbbq(Register dst, Register src) {
2151 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2152 Operand operand(src);
2153 EmitOperandREX(dst, operand, REX_W);
2154 EmitUint8(0x1B);
2155 EmitOperand(dst & 7, operand);
2156 }
2157
2158
2159 void Assembler::sbbq(Register dst, const Immediate& imm) {
2160 if (imm.is_int32()) {
2161 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2162 EmitRegisterREX(dst, REX_W);
2163 EmitComplex(3, Operand(dst), imm);
2164 } else {
2165 movq(TMP, imm);
2166 sbbq(dst, TMP);
2167 }
2168 }
2169
2170
2171 void Assembler::sbbq(Register dst, const Address& address) {
2172 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
2173 EmitOperandREX(dst, address, REX_W);
2174 EmitUint8(0x1B);
2175 EmitOperand(dst & 7, address);
2176 }
2177
2178
2121 void Assembler::shll(Register reg, const Immediate& imm) { 2179 void Assembler::shll(Register reg, const Immediate& imm) {
2122 EmitGenericShift(false, 4, reg, imm); 2180 EmitGenericShift(false, 4, reg, imm);
2123 } 2181 }
2124 2182
2125 2183
2126 void Assembler::shll(Register operand, Register shifter) { 2184 void Assembler::shll(Register operand, Register shifter) {
2127 EmitGenericShift(false, 4, operand, shifter); 2185 EmitGenericShift(false, 4, operand, shifter);
2128 } 2186 }
2129 2187
2130 2188
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3774 3832
3775 3833
3776 const char* Assembler::FpuRegisterName(FpuRegister reg) { 3834 const char* Assembler::FpuRegisterName(FpuRegister reg) {
3777 ASSERT((0 <= reg) && (reg < kNumberOfXmmRegisters)); 3835 ASSERT((0 <= reg) && (reg < kNumberOfXmmRegisters));
3778 return xmm_reg_names[reg]; 3836 return xmm_reg_names[reg];
3779 } 3837 }
3780 3838
3781 } // namespace dart 3839 } // namespace dart
3782 3840
3783 #endif // defined TARGET_ARCH_X64 3841 #endif // defined TARGET_ARCH_X64
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