[turbofan] small cleanups to aid register allocator debugging

src/compiler/pipeline.cc

Index: src/compiler/pipeline.cc
diff --git a/src/compiler/pipeline.cc b/src/compiler/pipeline.cc
index 3fdf826543557d2ed745635e0fe91740e6719f12..c5de2882fcf29d5d302f432a6bb7bfc5f4e4a8ec 100644
--- a/src/compiler/pipeline.cc
+++ b/src/compiler/pipeline.cc
@@ -110,6 +110,8 @@ class PipelineData {
   }
 
   Zone* instruction_zone() const { return instruction_zone_; }
+  // RawMachineAssembler generally produces graphs which cannot be verified.
+  bool MayHaveUnverifiableGraph() { return outer_zone_ == nullptr; }

[Benedikt Meurer, 2014/11/14 08:56:02]

Nit: const

 
   void DeleteGraphZone() {
     // Destroy objects with destructors first.
@@ -559,12 +561,7 @@ Handle<Code> Pipeline::GenerateCode(Linkage* linkage, PipelineData* data) {
     selector.SelectInstructions();
   }
 
-  if (FLAG_trace_turbo) {
-    OFStream os(stdout);
-    PrintableInstructionSequence printable = {
-        RegisterConfiguration::ArchDefault(), &sequence};
-    os << "----- Instruction sequence before register allocation -----\n"
-       << printable;
+  if (FLAG_trace_turbo && !data->MayHaveUnverifiableGraph()) {
     TurboCfgFile tcf(isolate());
     tcf << AsC1V("CodeGen", data->schedule(), data->source_positions(),
                  &sequence);
@@ -605,7 +602,7 @@ Handle<Code> Pipeline::GenerateCode(Linkage* linkage, PipelineData* data) {
       info()->AbortOptimization(kNotEnoughVirtualRegistersRegalloc);
       return Handle<Code>::null();
     }
-    if (FLAG_trace_turbo) {
+    if (FLAG_trace_turbo && !data->MayHaveUnverifiableGraph()) {
       TurboCfgFile tcf(isolate());
       tcf << AsC1VAllocator("CodeGen", &allocator);
     }