[turbofan] small cleanups to aid register allocator debugging

src/compiler/pipeline.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/pipeline.h"
 
 #include <fstream>  // NOLINT(readability/streams)
 #include <sstream>
 
 #include "src/base/platform/elapsed-timer.h"
@@ skipping 92 matching lines @@
   JSOperatorBuilder* javascript() const { return javascript_; }
   JSGraph* jsgraph() const { return jsgraph_; }
   Typer* typer() const { return typer_.get(); }
   Schedule* schedule() const { return schedule_; }
   void set_schedule(Schedule* schedule) {
     DCHECK_EQ(NULL, schedule_);
     schedule_ = schedule;
   }
 
   Zone* instruction_zone() const { return instruction_zone_; }
+  // RawMachineAssembler generally produces graphs which cannot be verified.
+  bool MayHaveUnverifiableGraph() { return outer_zone_ == nullptr; }

[Benedikt Meurer, 2014/11/14 08:56:02]

Nit: const

 
   void DeleteGraphZone() {
     // Destroy objects with destructors first.
     source_positions_.Reset(NULL);
     typer_.Reset(NULL);
     if (graph_zone_ == NULL) return;
     // Destroy zone and clear pointers.
     graph_zone_scope_.Destroy();
     graph_zone_ = NULL;
     graph_ = NULL;
@@ skipping 429 matching lines @@
   // Select and schedule instructions covering the scheduled graph.
   {
     PhaseScope phase_scope(data->pipeline_statistics(), "select instructions");
     ZonePool::Scope zone_scope(data->zone_pool());
     InstructionSelector selector(zone_scope.zone(), data->graph(), linkage,
                                  &sequence, data->schedule(),
                                  data->source_positions());
     selector.SelectInstructions();
   }
 
-  if (FLAG_trace_turbo) {
-    OFStream os(stdout);
-    PrintableInstructionSequence printable = {
-        RegisterConfiguration::ArchDefault(), &sequence};
-    os << "----- Instruction sequence before register allocation -----\n"
-       << printable;
+  if (FLAG_trace_turbo && !data->MayHaveUnverifiableGraph()) {
     TurboCfgFile tcf(isolate());
     tcf << AsC1V("CodeGen", data->schedule(), data->source_positions(),
                  &sequence);
   }
 
   data->DeleteGraphZone();
 
   if (data->pipeline_statistics() != NULL) {
     data->pipeline_statistics()->BeginPhaseKind("register allocation");
   }
@@ skipping 20 matching lines @@
     debug_name = GetDebugName(info());
 #endif
 
     RegisterAllocator allocator(RegisterConfiguration::ArchDefault(),
                                 zone_scope.zone(), &frame, &sequence,
                                 debug_name.get());
     if (!allocator.Allocate(data->pipeline_statistics())) {
       info()->AbortOptimization(kNotEnoughVirtualRegistersRegalloc);
       return Handle<Code>::null();
     }
-    if (FLAG_trace_turbo) {
+    if (FLAG_trace_turbo && !data->MayHaveUnverifiableGraph()) {
       TurboCfgFile tcf(isolate());
       tcf << AsC1VAllocator("CodeGen", &allocator);
     }
   }
 
   if (FLAG_trace_turbo) {
     OFStream os(stdout);
     PrintableInstructionSequence printable = {
         RegisterConfiguration::ArchDefault(), &sequence};
     os << "----- Instruction sequence after register allocation -----\n"
@@ skipping 32 matching lines @@
 }
 
 
 void Pipeline::TearDown() {
   InstructionOperand::TearDownCaches();
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8