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Unified Diff: src/arm/simulator-arm.cc

Issue 682643002: Add vrint{a,n,p,m,z} instructions to arm assembler. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Addressing more comments. Created 6 years, 2 months ago
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Index: src/arm/simulator-arm.cc
diff --git a/src/arm/simulator-arm.cc b/src/arm/simulator-arm.cc
index ceabe78cde711f8ba4b463b99db37bac6a8b1f87..aeb35c8a5f4f5bf52e27899eda297891006c8c94 100644
--- a/src/arm/simulator-arm.cc
+++ b/src/arm/simulator-arm.cc
@@ -2957,6 +2957,12 @@ void Simulator::DecodeTypeVFP(Instruction* instr) {
} else {
UNREACHABLE(); // Not used by v8.
}
+ } else if (((instr->Opc2Value() == 0x6)) && (instr->Opc3Value() == 0x3)) {
+ // vrintz - truncate
+ double dm_value = get_double_from_d_register(vm);
+ double dd_value = std::trunc(dm_value);
+ dd_value = canonicalizeNaN(dd_value);
+ set_d_register_from_double(vd, dd_value);
} else {
UNREACHABLE(); // Not used by V8.
}
@@ -3607,6 +3613,50 @@ void Simulator::DecodeSpecialCondition(Instruction* instr) {
UNIMPLEMENTED();
}
break;
+ case 0x1D:
+ if (instr->Opc1Value() == 0x7 && instr->Opc3Value() == 0x1 &&
+ instr->Bits(11, 9) == 0x5 && instr->Bits(19, 18) == 0x2 &&
+ instr->Bit(8) == 0x1) {
+ int vm = instr->VFPMRegValue(kDoublePrecision);
+ int vd = instr->VFPDRegValue(kDoublePrecision);
+ double dm_value = get_double_from_d_register(vm);
+ double dd_value = 0.0;
+ int rounding_mode = instr->Bits(17, 16);
+ switch (rounding_mode) {
+ case 0x0: // vrinta - round with ties to away from zero
+ dd_value = std::round(dm_value);
Torne 2014/11/04 16:28:55 The calls to std::round and std::trunc added here
Sven Panne 2014/11/05 08:05:00 Yes, we follow this policy, and normally this kind
+ break;
+ case 0x1: { // vrintn - round with ties to even
+ dd_value = std::floor(dm_value);
+ double error = dm_value - dd_value;
+ // Take care of correctly handling the range [-0.5, -0.0], which
+ // must yield -0.0.
+ if ((-0.5 <= dm_value) && (dm_value < 0.0)) {
+ dd_value = -0.0;
+ // If the error is greater than 0.5, or is equal to 0.5 and the
+ // integer result is odd, round up.
+ } else if ((error > 0.5) ||
+ ((error == 0.5) && (fmod(dd_value, 2) != 0))) {
+ dd_value++;
+ }
+ break;
+ }
+ case 0x2: // vrintp - ceil
+ dd_value = std::ceil(dm_value);
+ break;
+ case 0x3: // vrintm - floor
+ dd_value = std::floor(dm_value);
+ break;
+ default:
+ UNREACHABLE(); // Case analysis is exhaustive.
+ break;
+ }
+ dd_value = canonicalizeNaN(dd_value);
+ set_d_register_from_double(vd, dd_value);
+ } else {
+ UNIMPLEMENTED();
+ }
+ break;
default:
UNIMPLEMENTED();
break;
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