Subzero: Allow delaying Phi lowering until after register allocation.

tests_lit/llvm2ice_tests/simple-loop.ll

Index: tests_lit/llvm2ice_tests/simple-loop.ll
diff --git a/tests_lit/llvm2ice_tests/simple-loop.ll b/tests_lit/llvm2ice_tests/simple-loop.ll
index 02b78abd7b62521f42e93be881f38258416c0cf5..39337b576db93061a6b83084e5c735c8cb141fbc 100644
--- a/tests_lit/llvm2ice_tests/simple-loop.ll
+++ b/tests_lit/llvm2ice_tests/simple-loop.ll
@@ -35,14 +35,15 @@ for.end:
 ; CHECK-LABEL: simple_loop
 ; CHECK:      mov ecx, dword ptr [esp{{.*}}+{{.*}}{{[0-9]+}}]
 ; CHECK:      cmp ecx, 0
-; CHECK-NEXT: jle {{[0-9]}}
-
-; TODO: the mov from ebx to esi seems redundant here - so this may need to be
-; modified later
-
-; CHECK:      add [[IREG:[a-z]+]], 1
-; CHECK-NEXT: mov [[ICMPREG:[a-z]+]], [[IREG]]
-; CHECK:      cmp [[ICMPREG]], ecx
+; CHECK-NEXT: j{{le|g}} {{[0-9]}}
+
+; Check for the combination of address mode inference, register
+; allocation, and load/arithmetic fusing.
+; CHECK:      add e{{..}}, dword ptr [e{{..}} + 4*[[IREG:e..]]]
+; Check for incrementing of the register-allocated induction variable.
+; CHECK-NEXT: add [[IREG]], 1
+; Check for comparing the induction variable against the loop size.
+; CHECK-NEXT: cmp [[IREG]],
 ; CHECK-NEXT: jl -{{[0-9]}}
 ;
 ; There's nothing remarkable under Om1 to test for, since Om1 generates