Subzero: Allow delaying Phi lowering until after register allocation.

tests_lit/llvm2ice_tests/simple-loop.ll

 ; This tests a simple loop that sums the elements of an input array.
 ; The O2 check patterns represent the best code currently achieved.
 
 ; RUN: %p2i -i %s --args -O2 --verbose none \
 ; RUN:   | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
 ; RUN:   | llvm-objdump -d -symbolize -x86-asm-syntax=intel - | FileCheck %s
 ; RUN: %p2i -i %s --args -Om1 --verbose none \
 ; RUN:   | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
 ; RUN:   | llvm-objdump -d -symbolize -x86-asm-syntax=intel - \
 ; RUN:   | FileCheck --check-prefix=OPTM1 %s
@@ skipping 17 matching lines @@
   br i1 %cmp, label %for.body, label %for.end
 
 for.end:
   %sum.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.body ]
   ret i32 %sum.0.lcssa
 }
 
 ; CHECK-LABEL: simple_loop
 ; CHECK:      mov ecx, dword ptr [esp{{.*}}+{{.*}}{{[0-9]+}}]
 ; CHECK:      cmp ecx, 0
-; CHECK-NEXT: jle {{[0-9]}}
+; CHECK-NEXT: j{{le|g}} {{[0-9]}}
 
-; TODO: the mov from ebx to esi seems redundant here - so this may need to be
-; modified later
-
-; CHECK:      add [[IREG:[a-z]+]], 1
-; CHECK-NEXT: mov [[ICMPREG:[a-z]+]], [[IREG]]
-; CHECK:      cmp [[ICMPREG]], ecx
+; Check for the combination of address mode inference, register
+; allocation, and load/arithmetic fusing.
+; CHECK:      add e{{..}}, dword ptr [e{{..}} + 4*[[IREG:e..]]]
+; Check for incrementing of the register-allocated induction variable.
+; CHECK-NEXT: add [[IREG]], 1
+; Check for comparing the induction variable against the loop size.
+; CHECK-NEXT: cmp [[IREG]],
 ; CHECK-NEXT: jl -{{[0-9]}}
 ;
 ; There's nothing remarkable under Om1 to test for, since Om1 generates
 ; such atrocious code (by design).
 ; OPTM1-LABEL: simple_loop
 ; OPTM1:      cmp {{.*}}, 0
 ; OPTM1:      jg
 ; OPTM1:      ret
 
 ; ERRORS-NOT: ICE translation error