| Index: src/arm/simulator-arm.cc
|
| diff --git a/src/arm/simulator-arm.cc b/src/arm/simulator-arm.cc
|
| index 29be325275d05634e944d99af5edbfad048a755f..28954f63007e6aa35e4f67b5d6a903ab2ee9619e 100644
|
| --- a/src/arm/simulator-arm.cc
|
| +++ b/src/arm/simulator-arm.cc
|
| @@ -2473,6 +2473,8 @@ void Simulator::DecodeType7(Instruction* instr) {
|
| // vmov :Rt = Sn
|
| // vcvt: Dd = Sm
|
| // vcvt: Sd = Dm
|
| +// Dd = vabs(Dm)
|
| +// Dd = vneg(Dm)
|
| // Dd = vadd(Dn, Dm)
|
| // Dd = vsub(Dn, Dm)
|
| // Dd = vmul(Dn, Dm)
|
| @@ -2508,6 +2510,11 @@ void Simulator::DecodeTypeVFP(Instruction* instr) {
|
| double dm_value = get_double_from_d_register(vm);
|
| double dd_value = fabs(dm_value);
|
| set_d_register_from_double(vd, dd_value);
|
| + } else if ((instr->Opc2Value() == 0x1) && (instr->Opc3Value() == 0x1)) {
|
| + // vneg
|
| + double dm_value = get_double_from_d_register(vm);
|
| + double dd_value = -dm_value;
|
| + set_d_register_from_double(vd, dd_value);
|
| } else if ((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3)) {
|
| DecodeVCVTBetweenDoubleAndSingle(instr);
|
| } else if ((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) {
|
|
|