Index: src/arm/disasm-arm.cc |
diff --git a/src/arm/disasm-arm.cc b/src/arm/disasm-arm.cc |
index 85977b186e8a940558130f04c5f36d4ef32b005e..deaf552acc7e5c3388cd62c4b3f8d917ebca1699 100644 |
--- a/src/arm/disasm-arm.cc |
+++ b/src/arm/disasm-arm.cc |
@@ -1096,6 +1096,22 @@ void Decoder::DecodeType3(Instruction* instr) { |
break; |
} |
case db_x: { |
+ if (instr->Bits(22, 20) == 0x5) { |
+ if (instr->Bits(7, 4) == 0xd) { |
+ // SMMLS (in V8 notation matching ARM ISA format) |
+ Format(instr, "smmls'cond 'rn, 'rm, 'rs, 'rd"); |
+ break; |
+ } |
+ if (instr->Bits(7, 4) == 0x1) { |
+ if (instr->Bits(15, 12) == 0xF) { |
+ Format(instr, "smmul'cond 'rn, 'rm, 'rs"); |
+ } else { |
+ // SMMLA (in V8 notation matching ARM ISA format) |
+ Format(instr, "smmla'cond 'rn, 'rm, 'rs, 'rd"); |
+ } |
+ break; |
+ } |
+ } |
if (FLAG_enable_sudiv) { |
if (instr->Bits(5, 4) == 0x1) { |
if ((instr->Bit(22) == 0x0) && (instr->Bit(20) == 0x1)) { |