Index: src/arm/assembler-arm.cc |
diff --git a/src/arm/assembler-arm.cc b/src/arm/assembler-arm.cc |
index b3da1d65f3f70bde8b4e687e20c7de27c260a7f9..7e7456e78f90070cfe3fd52db5e9880f67fce342 100644 |
--- a/src/arm/assembler-arm.cc |
+++ b/src/arm/assembler-arm.cc |
@@ -1571,11 +1571,35 @@ void Assembler::udiv(Register dst, Register src1, Register src2, |
} |
-void Assembler::mul(Register dst, Register src1, Register src2, |
- SBit s, Condition cond) { |
+void Assembler::mul(Register dst, Register src1, Register src2, SBit s, |
+ Condition cond) { |
DCHECK(!dst.is(pc) && !src1.is(pc) && !src2.is(pc)); |
// dst goes in bits 16-19 for this instruction! |
- emit(cond | s | dst.code()*B16 | src2.code()*B8 | B7 | B4 | src1.code()); |
+ emit(cond | s | dst.code() * B16 | src2.code() * B8 | B7 | B4 | src1.code()); |
+} |
+ |
+ |
+void Assembler::smmla(Register dst, Register src1, Register src2, Register srcA, |
+ Condition cond) { |
+ DCHECK(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc)); |
+ emit(cond | B26 | B25 | B24 | B22 | B20 | dst.code() * B16 | |
+ srcA.code() * B12 | src2.code() * B8 | B4 | src1.code()); |
+} |
+ |
+ |
+void Assembler::smmls(Register dst, Register src1, Register src2, Register srcA, |
+ Condition cond) { |
+ DCHECK(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc)); |
+ emit(cond | B26 | B25 | B24 | B22 | B20 | dst.code() * B16 | |
+ srcA.code() * B12 | src2.code() * B8 | B7 | B6 | B4 | src1.code()); |
+} |
+ |
+ |
+void Assembler::smmul(Register dst, Register src1, Register src2, |
+ Condition cond) { |
+ DCHECK(!dst.is(pc) && !src1.is(pc) && !src2.is(pc)); |
+ emit(cond | B26 | B25 | B24 | B22 | B20 | dst.code() * B16 | 0xf * B12 | |
+ src2.code() * B8 | B4 | src1.code()); |
} |