Index: lib/Target/X86/X86NaClRewritePass.cpp |
diff --git a/lib/Target/X86/X86NaClRewritePass.cpp b/lib/Target/X86/X86NaClRewritePass.cpp |
index 4ecd55ea8996e74f62f06e0c66236212ecc87388..77ac61faed483ed316afbd6366fad26107bf2c00 100644 |
--- a/lib/Target/X86/X86NaClRewritePass.cpp |
+++ b/lib/Target/X86/X86NaClRewritePass.cpp |
@@ -462,8 +462,9 @@ bool X86NaClRewritePass::ApplyControlSFI(MachineBasicBlock &MBB, |
.addOperand(MI.getOperand(0)) |
.addReg(FlagUseZeroBasedSandbox ? 0 : X86::R15); |
} |
+ |
BuildMI(MBB, MBBI, DL, TII->get(X86::NACL_JMP64r)) |
- .addReg(RegTarget) |
+ .addReg(getX86SubSuperRegister(RegTarget, MVT::i32, false)) |
.addReg(FlagUseZeroBasedSandbox ? 0 : X86::R15); |
} else { |
RegTarget = X86::ECX; |
@@ -575,7 +576,8 @@ bool X86NaClRewritePass::ApplyRewrites(MachineBasicBlock &MBB, |
// and variable operands removed. |
unsigned NewOpc = 0; |
switch (Opc) { |
- case X86::CALLpcrel32 : NewOpc = X86::NACL_CALL32d; break; |
+ // 32-bit direct calls are handled unmodified by the assemblers |
+ case X86::CALLpcrel32 : return true; |
case X86::TAILJMPd : NewOpc = X86::JMP_4; break; |
case X86::NACL_CG_TAILJMPd64 : NewOpc = X86::JMP_4; break; |
case X86::NACL_CG_CALL64pcrel32: NewOpc = X86::NACL_CALL64d; break; |
@@ -631,7 +633,7 @@ bool X86NaClRewritePass::ApplyRewrites(MachineBasicBlock &MBB, |
LeaOpc = X86::LEA64r; |
Reg = X86::RAX; |
} else { |
- CallOpc = X86::NACL_CALL32d; |
+ CallOpc = X86::CALLpcrel32; |
LeaOpc = X86::LEA32r; |
Reg = X86::EAX; |
} |
@@ -661,7 +663,7 @@ bool X86NaClRewritePass::ApplyRewrites(MachineBasicBlock &MBB, |
Base = X86::RIP; |
Reg = X86::RAX; |
} else { |
- CallOpc = X86::NACL_CALL32d; |
+ CallOpc = X86::CALLpcrel32; |
AddOpc = X86::ADD32rm; |
Base = MI.getOperand(3).getTargetFlags() == X86II::MO_INDNTPOFF ? |
0 : X86::EBX; // EBX for GOTNTPOFF. |