Change usage of naclcall and nacljmp pseudo-instructions to match x86 gas

lib/Target/X86/X86NaClRewritePass.cpp

 //=== X86NaClRewritePAss.cpp - Rewrite instructions for NaCl SFI --*- C++ -*-=//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains a pass that ensures stores and loads and stack/frame
@@ skipping 444 matching lines @@
     // sandbox base address.
     unsigned RegTarget;
     if (Is64Bit) {
       RegTarget = (HideSandboxBase ? X86::R11 : X86::RCX);
       BuildMI(MBB, MBBI, DL, TII->get(X86::POP64r), RegTarget);
       if (Opc == X86::RETI) {
         BuildMI(MBB, MBBI, DL, TII->get(X86::NACL_ASPi32))
           .addOperand(MI.getOperand(0))
           .addReg(FlagUseZeroBasedSandbox ? 0 : X86::R15);
       }
+
       BuildMI(MBB, MBBI, DL, TII->get(X86::NACL_JMP64r))
-        .addReg(RegTarget)
+        .addReg(getX86SubSuperRegister(RegTarget, MVT::i32, false))
         .addReg(FlagUseZeroBasedSandbox ? 0 : X86::R15);
     } else {
       RegTarget = X86::ECX;
       BuildMI(MBB, MBBI, DL, TII->get(X86::POP32r), RegTarget);
       if (Opc == X86::RETI) {
         BuildMI(MBB, MBBI, DL, TII->get(X86::ADD32ri), X86::ESP)
           .addReg(X86::ESP)
           .addOperand(MI.getOperand(0));
       }
       BuildMI(MBB, MBBI, DL, TII->get(X86::NACL_JMP32r))
@@ skipping 91 matching lines @@
 bool X86NaClRewritePass::ApplyRewrites(MachineBasicBlock &MBB,
                                        MachineBasicBlock::iterator MBBI) {
   MachineInstr &MI = *MBBI;
   DebugLoc DL = MI.getDebugLoc();
   unsigned Opc = MI.getOpcode();
 
   // These direct jumps need their opcode rewritten
   // and variable operands removed.
   unsigned NewOpc = 0;
   switch (Opc) {
-  case X86::CALLpcrel32          : NewOpc = X86::NACL_CALL32d; break;
+  // 32-bit direct calls are handled unmodified by the assemblers
+  case X86::CALLpcrel32          : return true;
   case X86::TAILJMPd             : NewOpc = X86::JMP_4; break;
   case X86::NACL_CG_TAILJMPd64   : NewOpc = X86::JMP_4; break;
   case X86::NACL_CG_CALL64pcrel32: NewOpc = X86::NACL_CALL64d; break;
   }
   if (NewOpc) {
     BuildMI(MBB, MBBI, DL, TII->get(NewOpc))
       .addOperand(MI.getOperand(0));
     MI.eraseFromParent();
     return true;
   }
@@ skipping 28 matching lines @@
         .addExternalSymbol("__tls_get_addr", X86II::MO_PLT);
     MI.eraseFromParent();
     return true;
   }
 
   // Local Exec NaCl TLS Model
   if (Opc == X86::NACL_CG_LE_TLS_addr64 ||
       Opc == X86::NACL_CG_LE_TLS_addr32) {
     unsigned CallOpc, LeaOpc, Reg;
     // Rewrite to:
     //   naclcall __nacl_read_tp@PLT

[jvoung (off chromium), 2014/10/15 00:38:14]

"call __nacl_read_tp" now?

[Derek Schuff, 2014/10/15 17:14:14]

Done.

     //   lea $sym@flag(,%reg), %reg
     if (Opc == X86::NACL_CG_LE_TLS_addr64) {
       CallOpc = X86::NACL_CALL64d;
       LeaOpc = X86::LEA64r;
       Reg = X86::RAX;
     } else {
-      CallOpc = X86::NACL_CALL32d;
+      CallOpc = X86::CALLpcrel32;
       LeaOpc = X86::LEA32r;
       Reg = X86::EAX;
     }
     BuildMI(MBB, MBBI, DL, TII->get(CallOpc))
         .addExternalSymbol("__nacl_read_tp", X86II::MO_PLT);
     BuildMI(MBB, MBBI, DL, TII->get(LeaOpc), Reg)
         .addReg(0) // Base
         .addImm(1) // Scale
         .addReg(Reg) // Index
         .addGlobalAddress(MI.getOperand(3).getGlobal(), 0,
                           MI.getOperand(3).getTargetFlags())
         .addReg(0); // Segment
     MI.eraseFromParent();
     return true;
   }
 
   // Initial Exec NaCl TLS Model
   if (Opc == X86::NACL_CG_IE_TLS_addr64 ||
       Opc == X86::NACL_CG_IE_TLS_addr32) {
     unsigned CallOpc, AddOpc, Base, Reg;
     // Rewrite to:
     //   naclcall __nacl_read_tp@PLT

[jvoung (off chromium), 2014/10/15 00:38:14]

same

[Derek Schuff, 2014/10/15 17:14:13]

Done.

     //   addq sym@flag(%base), %reg
     if (Opc == X86::NACL_CG_IE_TLS_addr64) {
       CallOpc = X86::NACL_CALL64d;
       AddOpc = X86::ADD64rm;
       Base = X86::RIP;
       Reg = X86::RAX;
     } else {
-      CallOpc = X86::NACL_CALL32d;
+      CallOpc = X86::CALLpcrel32;
       AddOpc = X86::ADD32rm;
       Base = MI.getOperand(3).getTargetFlags() == X86II::MO_INDNTPOFF ?
           0 : X86::EBX; // EBX for GOTNTPOFF.
       Reg = X86::EAX;
     }
     BuildMI(MBB, MBBI, DL, TII->get(CallOpc))
         .addExternalSymbol("__nacl_read_tp", X86II::MO_PLT);
     BuildMI(MBB, MBBI, DL, TII->get(AddOpc), Reg)
         .addReg(Reg)
         .addReg(Base)
@@ skipping 72 matching lines @@
   }
   return Modified;
 }
 
 /// createX86NaClRewritePassPass - returns an instance of the pass.
 namespace llvm {
   FunctionPass* createX86NaClRewritePass() {
     return new X86NaClRewritePass();
   }
 }