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| 1 // ------------------------------------------------------------------ |
| 2 // Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. |
| 3 // |
| 4 // This program is free software; you can redistribute it and/or modify |
| 5 // it under the terms of the GNU General Public License version 2 as |
| 6 // published by the Free Software Foundation; |
| 7 // |
| 8 // Software distributed under the License is distributed on an "AS |
| 9 // IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or |
| 10 // implied. See the License for the specific language governing |
| 11 // rights and limitations under the License. |
| 12 // |
| 13 // |
| 14 // ------------------------------------------------------------------ |
| 15 //=================================================================== |
| 16 // Author(s): ="Atheros" |
| 17 //=================================================================== |
| 18 |
| 19 |
| 20 #ifndef _VMC_REG_REG_H_ |
| 21 #define _VMC_REG_REG_H_ |
| 22 |
| 23 #define MC_TCAM_VALID_ADDRESS 0x00000000 |
| 24 #define MC_TCAM_VALID_OFFSET 0x00000000 |
| 25 #define MC_TCAM_VALID_BIT_MSB 0 |
| 26 #define MC_TCAM_VALID_BIT_LSB 0 |
| 27 #define MC_TCAM_VALID_BIT_MASK 0x00000001 |
| 28 #define MC_TCAM_VALID_BIT_GET(x) (((x) & MC_TCAM_VALID_BIT_MASK)
>> MC_TCAM_VALID_BIT_LSB) |
| 29 #define MC_TCAM_VALID_BIT_SET(x) (((x) << MC_TCAM_VALID_BIT_LSB)
& MC_TCAM_VALID_BIT_MASK) |
| 30 |
| 31 #define MC_TCAM_MASK_ADDRESS 0x00000080 |
| 32 #define MC_TCAM_MASK_OFFSET 0x00000080 |
| 33 #define MC_TCAM_MASK_SIZE_MSB 2 |
| 34 #define MC_TCAM_MASK_SIZE_LSB 0 |
| 35 #define MC_TCAM_MASK_SIZE_MASK 0x00000007 |
| 36 #define MC_TCAM_MASK_SIZE_GET(x) (((x) & MC_TCAM_MASK_SIZE_MASK)
>> MC_TCAM_MASK_SIZE_LSB) |
| 37 #define MC_TCAM_MASK_SIZE_SET(x) (((x) << MC_TCAM_MASK_SIZE_LSB)
& MC_TCAM_MASK_SIZE_MASK) |
| 38 |
| 39 #define MC_TCAM_COMPARE_ADDRESS 0x00000100 |
| 40 #define MC_TCAM_COMPARE_OFFSET 0x00000100 |
| 41 #define MC_TCAM_COMPARE_KEY_MSB 21 |
| 42 #define MC_TCAM_COMPARE_KEY_LSB 5 |
| 43 #define MC_TCAM_COMPARE_KEY_MASK 0x003fffe0 |
| 44 #define MC_TCAM_COMPARE_KEY_GET(x) (((x) & MC_TCAM_COMPARE_KEY_MAS
K) >> MC_TCAM_COMPARE_KEY_LSB) |
| 45 #define MC_TCAM_COMPARE_KEY_SET(x) (((x) << MC_TCAM_COMPARE_KEY_LS
B) & MC_TCAM_COMPARE_KEY_MASK) |
| 46 |
| 47 #define MC_TCAM_TARGET_ADDRESS 0x00000180 |
| 48 #define MC_TCAM_TARGET_OFFSET 0x00000180 |
| 49 #define MC_TCAM_TARGET_ADDR_MSB 21 |
| 50 #define MC_TCAM_TARGET_ADDR_LSB 5 |
| 51 #define MC_TCAM_TARGET_ADDR_MASK 0x003fffe0 |
| 52 #define MC_TCAM_TARGET_ADDR_GET(x) (((x) & MC_TCAM_TARGET_ADDR_MAS
K) >> MC_TCAM_TARGET_ADDR_LSB) |
| 53 #define MC_TCAM_TARGET_ADDR_SET(x) (((x) << MC_TCAM_TARGET_ADDR_LS
B) & MC_TCAM_TARGET_ADDR_MASK) |
| 54 |
| 55 #define ADDR_ERROR_CONTROL_ADDRESS 0x00000200 |
| 56 #define ADDR_ERROR_CONTROL_OFFSET 0x00000200 |
| 57 #define ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB 1 |
| 58 #define ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB 1 |
| 59 #define ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK 0x00000002 |
| 60 #define ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) (((x) & ADDR_ERROR_CONTROL_QUAL
_ENABLE_MASK) >> ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) |
| 61 #define ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) (((x) << ADDR_ERROR_CONTROL_QUA
L_ENABLE_LSB) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) |
| 62 #define ADDR_ERROR_CONTROL_ENABLE_MSB 0 |
| 63 #define ADDR_ERROR_CONTROL_ENABLE_LSB 0 |
| 64 #define ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001 |
| 65 #define ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & ADDR_ERROR_CONTROL_ENAB
LE_MASK) >> ADDR_ERROR_CONTROL_ENABLE_LSB) |
| 66 #define ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << ADDR_ERROR_CONTROL_ENA
BLE_LSB) & ADDR_ERROR_CONTROL_ENABLE_MASK) |
| 67 |
| 68 #define ADDR_ERROR_STATUS_ADDRESS 0x00000204 |
| 69 #define ADDR_ERROR_STATUS_OFFSET 0x00000204 |
| 70 #define ADDR_ERROR_STATUS_WRITE_MSB 25 |
| 71 #define ADDR_ERROR_STATUS_WRITE_LSB 25 |
| 72 #define ADDR_ERROR_STATUS_WRITE_MASK 0x02000000 |
| 73 #define ADDR_ERROR_STATUS_WRITE_GET(x) (((x) & ADDR_ERROR_STATUS_WRITE
_MASK) >> ADDR_ERROR_STATUS_WRITE_LSB) |
| 74 #define ADDR_ERROR_STATUS_WRITE_SET(x) (((x) << ADDR_ERROR_STATUS_WRIT
E_LSB) & ADDR_ERROR_STATUS_WRITE_MASK) |
| 75 #define ADDR_ERROR_STATUS_ADDRESS_MSB 24 |
| 76 #define ADDR_ERROR_STATUS_ADDRESS_LSB 0 |
| 77 #define ADDR_ERROR_STATUS_ADDRESS_MASK 0x01ffffff |
| 78 #define ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & ADDR_ERROR_STATUS_ADDRE
SS_MASK) >> ADDR_ERROR_STATUS_ADDRESS_LSB) |
| 79 #define ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << ADDR_ERROR_STATUS_ADDR
ESS_LSB) & ADDR_ERROR_STATUS_ADDRESS_MASK) |
| 80 |
| 81 |
| 82 #ifndef __ASSEMBLER__ |
| 83 |
| 84 typedef struct vmc_reg_reg_s { |
| 85 volatile unsigned int mc_tcam_valid[32]; |
| 86 volatile unsigned int mc_tcam_mask[32]; |
| 87 volatile unsigned int mc_tcam_compare[32]; |
| 88 volatile unsigned int mc_tcam_target[32]; |
| 89 volatile unsigned int addr_error_control; |
| 90 volatile unsigned int addr_error_status; |
| 91 } vmc_reg_reg_t; |
| 92 |
| 93 #endif /* __ASSEMBLER__ */ |
| 94 |
| 95 #endif /* _VMC_REG_H_ */ |
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