Adds ldp and stp instructions to ARM64.

runtime/vm/constants_arm64.h

Index: runtime/vm/constants_arm64.h
===================================================================
--- runtime/vm/constants_arm64.h	(revision 40940)
+++ runtime/vm/constants_arm64.h	(working copy)
@@ -369,6 +369,14 @@
   FLDRQ = LDR | B26 | B23,
 };
 
+// C3.3.14-16
+enum LoadStoreRegPairOp {
+  LoadStoreRegPairMask = 0x3a000000,
+  LoadStoreRegPairFixed = LoadStoreFixed | B29,
+  STP = LoadStoreRegPairFixed,
+  LDP = LoadStoreRegPairFixed | B22,
+};
+
 // C3.4.1
 enum AddSubImmOp {
   AddSubImmMask = 0x1f000000,
@@ -581,6 +589,7 @@
 _V(UnconditionalBranch)                                                        \
 _V(UnconditionalBranchReg)                                                     \
 _V(LoadStoreReg)                                                               \
+_V(LoadStoreRegPair)                                                           \
 _V(LoadRegLiteral)                                                             \
 _V(AddSubImm)                                                                  \
 _V(LogicalImm)                                                                 \
@@ -654,6 +663,8 @@
   kRmBits = 5,
   kRtShift = 0,
   kRtBits = 5,
+  kRt2Shift = 10,
+  kRt2Bits = 5,
 
   // V Registers.
   kVdShift = 0,
@@ -674,6 +685,9 @@
   kImm5Bits = 5,
   kImm6Shift = 10,
   kImm6Bits = 6,
+  kImm7Shift = 15,
+  kImm7Bits = 7,
+  kImm7Mask = 0x7f << kImm7Shift,
   kImm8Shift = 13,
   kImm8Bits = 8,
   kImm9Shift = 12,
@@ -839,6 +853,8 @@
                                         Bits(kRmShift, kRmBits)); }
   inline Register RtField() const { return static_cast<Register>(
                                         Bits(kRtShift, kRtBits)); }
+  inline Register Rt2Field() const { return static_cast<Register>(
+                                        Bits(kRt2Shift, kRt2Bits)); }
 
   inline VRegister VdField() const { return static_cast<VRegister>(
                                         Bits(kVdShift, kVdBits)); }
@@ -852,6 +868,10 @@
   // Immediates
   inline int Imm3Field() const { return Bits(kImm3Shift, kImm3Bits); }
   inline int Imm6Field() const { return Bits(kImm6Shift, kImm6Bits); }
+  inline int Imm7Field() const { return Bits(kImm7Shift, kImm7Bits); }
+  // Sign-extended Imm7Field()
+  inline int64_t SImm7Field() const {
+      return (static_cast<int32_t>(Imm7Field()) << 25) >> 25; }
   inline int Imm8Field() const { return Bits(kImm8Shift, kImm8Bits); }
   inline int Imm9Field() const { return Bits(kImm9Shift, kImm9Bits); }
   // Sign-extended Imm9Field()