Adds ldp and stp instructions to ARM64.

runtime/vm/constants_arm64.h

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_CONSTANTS_ARM64_H_
 #define VM_CONSTANTS_ARM64_H_
 
 #include "platform/assert.h"
 
 namespace dart {
@@ skipping 351 matching lines @@
   LoadStoreRegFixed = LoadStoreFixed | B29 | B28,
   STR = LoadStoreRegFixed,
   LDR = LoadStoreRegFixed | B22,
   LDRS = LoadStoreRegFixed | B23,
   FSTR = STR | B26,
   FLDR = LDR | B26,
   FSTRQ = STR | B26 | B23,
   FLDRQ = LDR | B26 | B23,
 };
 
+// C3.3.14-16
+enum LoadStoreRegPairOp {
+  LoadStoreRegPairMask = 0x3a000000,
+  LoadStoreRegPairFixed = LoadStoreFixed | B29,
+  STP = LoadStoreRegPairFixed,
+  LDP = LoadStoreRegPairFixed | B22,
+};
+
 // C3.4.1
 enum AddSubImmOp {
   AddSubImmMask = 0x1f000000,
   AddSubImmFixed = DPImmediateFixed | B24,
   ADDI = AddSubImmFixed,
   SUBI = AddSubImmFixed | B30,
 };
 
 // C3.4.4
 enum LogicalImmOp {
@@ skipping 192 matching lines @@
 _V(DPSimd2)                                                                    \
 _V(FP)                                                                         \
 _V(CompareAndBranch)                                                           \
 _V(ConditionalBranch)                                                          \
 _V(ExceptionGen)                                                               \
 _V(System)                                                                     \
 _V(TestAndBranch)                                                              \
 _V(UnconditionalBranch)                                                        \
 _V(UnconditionalBranchReg)                                                     \
 _V(LoadStoreReg)                                                               \
+_V(LoadStoreRegPair)                                                           \
 _V(LoadRegLiteral)                                                             \
 _V(AddSubImm)                                                                  \
 _V(LogicalImm)                                                                 \
 _V(MoveWide)                                                                   \
 _V(PCRel)                                                                      \
 _V(AddSubShiftExt)                                                             \
 _V(ConditionalSelect)                                                          \
 _V(MiscDP2Source)                                                              \
 _V(MiscDP3Source)                                                              \
 _V(LogicalShift)                                                               \
@@ skipping 53 matching lines @@
   kRdShift = 0,
   kRdBits = 5,
   kRnShift = 5,
   kRnBits = 5,
   kRaShift = 10,
   kRaBits = 5,
   kRmShift = 16,
   kRmBits = 5,
   kRtShift = 0,
   kRtBits = 5,
+  kRt2Shift = 10,
+  kRt2Bits = 5,
 
   // V Registers.
   kVdShift = 0,
   kVdBits = 5,
   kVnShift = 5,
   kVnBits = 5,
   kVmShift = 16,
   kVmBits = 5,
   kVtShift = 0,
   kVtBits = 5,
 
   // Immediates.
   kImm3Shift = 10,
   kImm3Bits = 3,
   kImm4Shift = 11,
   kImm4Bits = 4,
   kImm5Shift = 16,
   kImm5Bits = 5,
   kImm6Shift = 10,
   kImm6Bits = 6,
+  kImm7Shift = 15,
+  kImm7Bits = 7,
+  kImm7Mask = 0x7f << kImm7Shift,
   kImm8Shift = 13,
   kImm8Bits = 8,
   kImm9Shift = 12,
   kImm9Bits = 9,
   kImm12Shift = 10,
   kImm12Bits = 12,
   kImm12Mask = 0xfff << kImm12Shift,
   kImm12ShiftShift = 22,
   kImm12ShiftBits = 2,
   kImm14Shift = 5,
@@ skipping 145 matching lines @@
   inline Register RdField() const { return static_cast<Register>(
                                         Bits(kRdShift, kRdBits)); }
   inline Register RnField() const { return static_cast<Register>(
                                         Bits(kRnShift, kRnBits)); }
   inline Register RaField() const { return static_cast<Register>(
                                         Bits(kRaShift, kRaBits)); }
   inline Register RmField() const { return static_cast<Register>(
                                         Bits(kRmShift, kRmBits)); }
   inline Register RtField() const { return static_cast<Register>(
                                         Bits(kRtShift, kRtBits)); }
+  inline Register Rt2Field() const { return static_cast<Register>(
+                                        Bits(kRt2Shift, kRt2Bits)); }
 
   inline VRegister VdField() const { return static_cast<VRegister>(
                                         Bits(kVdShift, kVdBits)); }
   inline VRegister VnField() const { return static_cast<VRegister>(
                                         Bits(kVnShift, kVnBits)); }
   inline VRegister VmField() const { return static_cast<VRegister>(
                                         Bits(kVmShift, kVmBits)); }
   inline VRegister VtField() const { return static_cast<VRegister>(
                                         Bits(kVtShift, kVtBits)); }
 
   // Immediates
   inline int Imm3Field() const { return Bits(kImm3Shift, kImm3Bits); }
   inline int Imm6Field() const { return Bits(kImm6Shift, kImm6Bits); }
+  inline int Imm7Field() const { return Bits(kImm7Shift, kImm7Bits); }
+  // Sign-extended Imm7Field()
+  inline int64_t SImm7Field() const {
+      return (static_cast<int32_t>(Imm7Field()) << 25) >> 25; }
   inline int Imm8Field() const { return Bits(kImm8Shift, kImm8Bits); }
   inline int Imm9Field() const { return Bits(kImm9Shift, kImm9Bits); }
   // Sign-extended Imm9Field()
   inline int64_t SImm9Field() const {
       return (static_cast<int32_t>(Imm9Field()) << 23) >> 23; }
 
   inline int Imm12Field() const { return Bits(kImm12Shift, kImm12Bits); }
   inline int Imm12ShiftField() const {
     return Bits(kImm12ShiftShift, kImm12ShiftBits); }
 
@@ skipping 152 matching lines @@
   static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); }
 
  private:
   DISALLOW_ALLOCATION();
   DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
 };
 
 }  // namespace dart
 
 #endif  // VM_CONSTANTS_ARM64_H_