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Unified Diff: third_party/yasm/patched-yasm/modules/arch/x86/gen_x86_insn.py

Issue 6170009: Update our yasm copy to yasm 1.1.0 (Part 1: yasm side)... (Closed) Base URL: svn://svn.chromium.org/chrome/trunk/deps/
Patch Set: Created 9 years, 11 months ago
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Index: third_party/yasm/patched-yasm/modules/arch/x86/gen_x86_insn.py
===================================================================
--- third_party/yasm/patched-yasm/modules/arch/x86/gen_x86_insn.py (revision 71129)
+++ third_party/yasm/patched-yasm/modules/arch/x86/gen_x86_insn.py (working copy)
@@ -25,8 +25,11 @@
# POSSIBILITY OF SUCH DAMAGE.
#
# NOTE: operands are arranged in NASM / Intel order (e.g. dest, src)
-rcstag = "$Id: gen_x86_insn.py 2193 2009-04-04 23:03:41Z peter $"
+from sys import stdout, version_info
+
+rcstag = "$Id: gen_x86_insn.py 2346 2010-08-01 01:37:37Z peter $"
+
import os
import sys
@@ -43,7 +46,8 @@
ordered_cpu_features = [
"FPU", "Cyrix", "AMD", "MMX", "3DNow", "SMM", "SSE", "SSE2",
"SSE3", "SVM", "PadLock", "SSSE3", "SSE41", "SSE42", "SSE4a", "SSE5",
- "AVX", "FMA", "AES", "CLMUL"]
+ "AVX", "FMA", "AES", "CLMUL", "MOVBE", "XOP", "FMA4", "F16C",
+ "FSGSBASE", "RDRAND", "XSAVEOPT", "EPTVPID", "SMX"]
unordered_cpu_features = ["Priv", "Prot", "Undoc", "Obs"]
# Predefined VEX prefix field values
@@ -53,6 +57,16 @@
VEXL1 = 0xC4
VEXpp = 0xC0 # OR with value
+# Predefined XOP prefix field values
+XOPW0 = 0x80
+XOPW1 = 0x88
+XOPL0 = 0x80
+XOPL1 = 0x84
+XOPpp = 0x80 # OR with value
+
+def lprint(s, f = stdout, e = '\n') :
+ f.write(s + e)
+
def cpu_lcd(cpu1, cpu2):
"""Find the lowest common denominator of two CPU sets."""
retval = set()
@@ -109,7 +123,7 @@
if kwargs:
for arg in kwargs:
- print "Warning: unrecognized arg %s" % arg
+ lprint("Warning: unrecognized arg %s" % arg)
def __str__(self):
return "{"+ ", ".join(["OPT_%s" % self.type,
@@ -175,6 +189,14 @@
suffix = kwargs.pop("suffix", None)
if suffix is not None:
self.suffixes = [suffix]
+
+ req_suffix = kwargs.pop("req_suffix", False)
+ if not req_suffix:
+ if self.suffixes is None:
+ self.suffixes = ["Z"]
+ else:
+ self.suffixes.append("Z")
+
if self.suffixes is not None:
self.suffixes = set(x.upper() for x in self.suffixes)
@@ -212,6 +234,27 @@
self.special_prefix = "0x%02X" % (0xC0 + vexW*8 + vexL*4 + vexpp)
+ # XOP prefix
+ if "xop" in kwargs:
+ xopW = kwargs.pop("xopw", 0)
+ if xopW not in [0, 1]:
+ raise ValueError("XOP.W must be 0 or 1")
+
+ xopL = kwargs.pop("xop")
+ if xopL == 128 or xopL == 0:
+ xopL = 0
+ elif xopL == 256:
+ xopL = 1
+ else:
+ raise ValueError("XOP.L must be 128 or 256")
+
+ # XOPpp is currently reserved (0)
+ xoppp = 0
+ if self.special_prefix not in ["0", "0x00"]:
+ raise ValueError("Cannot combine XOP and special prefix %s"
+ % self.special_prefix)
+ self.special_prefix = "0x%02X" % (0x80 + xopW*8 + xopL*4 + xoppp)
+
# Spare value
self.spare = kwargs.pop("spare", 0)
@@ -230,9 +273,6 @@
else:
raise KeyError("missing opcode")
- # DREX opcode0 field
- self.drex_oc0 = kwargs.pop("drex_oc0", 0) and 0x08 or 0
-
# Build operands string (C array initializer)
self.operands = kwargs.pop("operands")
for op in self.operands:
@@ -252,8 +292,6 @@
self.cpu.add("586")
if op.dest == "EA64":
self.misc_flags.add("ONLY_64")
- if op.dest == "DREX":
- self.drex_oc0 |= 0x80
# Modifiers
self.modifiers = kwargs.pop("modifiers", [])
@@ -276,7 +314,7 @@
if kwargs:
for arg in kwargs:
- print "Warning: unrecognized arg %s" % arg
+ lprint("Warning: unrecognized arg %s" % arg)
def __str__(self):
if hasattr(self, "opcode"):
@@ -331,8 +369,6 @@
"%d" % (self.opersize or 0),
"%d" % (self.def_opersize_64 or 0),
self.special_prefix or "0",
- self.drex_oc0 and
- ("0x%02X" % self.drex_oc0) or "0",
"%d" % self.opcode_len,
opcodes_str,
"%d" % (self.spare or 0),
@@ -435,7 +471,7 @@
def __str__(self):
if self.suffix is None:
- suffix_str = "NONE"
+ suffix_str = "SUF_Z"
elif len(self.suffix) == 1:
suffix_str = "SUF_" + self.suffix
else:
@@ -503,8 +539,8 @@
def finalize_insns():
unused_groups = set(groups.keys())
- for name, opts in insns.iteritems():
- for insn in opts:
+ for name in insns:
+ for insn in insns[name]:
group = groups[insn.groupname]
unused_groups.discard(insn.groupname)
@@ -515,30 +551,27 @@
parsers &= insn.parsers
if "gas" in parsers:
- keyword = name
- if keyword in gas_insns:
- raise ValueError("duplicate gas instruction %s" % keyword)
- newinsn = insn.copy()
- newinsn.auto_cpu("gas")
- newinsn.auto_misc_flags("gas")
- gas_insns[keyword] = newinsn
-
+ suffixes = set()
if insn.suffix is None:
- suffixes = set()
for form in group:
if form.gen_suffix and form.suffixes is not None:
suffixes |= form.suffixes
- for suffix in suffixes:
+ if not suffixes:
+ suffixes.add("Z")
+ for suffix in suffixes:
+ if suffix == "Z":
+ keyword = name
+ else:
keyword = name+suffix
- if keyword in gas_insns:
- raise ValueError("duplicate gas instruction %s" %
- keyword)
- newinsn = insn.copy()
- newinsn.suffix = suffix
- newinsn.auto_cpu("gas")
- newinsn.auto_misc_flags("gas")
- gas_insns[keyword] = newinsn
+ if keyword in gas_insns:
+ raise ValueError("duplicate gas instruction %s" %
+ keyword)
+ newinsn = insn.copy()
+ newinsn.suffix = suffix
+ newinsn.auto_cpu("gas")
+ newinsn.auto_misc_flags("gas")
+ gas_insns[keyword] = newinsn
if "nasm" in parsers:
keyword = name
@@ -552,12 +585,12 @@
unused_groups.discard("empty")
unused_groups.discard("not64")
if unused_groups:
- print "warning: unused groups: %s" % ", ".join(unused_groups)
+ lprint("warning: unused groups: %s" % ", ".join(unused_groups))
def output_insns(f, parser, insns):
- print >>f, "/* Generated by %s r%s, do not edit */" % \
- (scriptname, scriptrev)
- print >>f, """%%ignore-case
+ lprint("/* Generated by %s r%s, do not edit */" % \
+ (scriptname, scriptrev), f)
+ lprint("""%%ignore-case
%%language=ANSI-C
%%compare-strncmp
%%readonly-tables
@@ -566,9 +599,9 @@
%%define hash-function-name insnprefix_%s_hash
%%define lookup-function-name insnprefix_%s_find
struct insnprefix_parse_data;
-%%%%""" % (parser, parser)
+%%%%""" % (parser, parser), f)
for keyword in sorted(insns):
- print >>f, "%s,\t%s" % (keyword.lower(), insns[keyword])
+ lprint("%s,\t%s" % (keyword.lower(), insns[keyword]), f)
def output_gas_insns(f):
output_insns(f, "gas", gas_insns)
@@ -580,10 +613,14 @@
# Merge all operand lists into single list
# Sort by number of operands to shorten output
all_operands = []
- for form in sorted((form for g in groups.itervalues() for form in g),
+ if version_info[0] == 2:
+ gi = groups.itervalues()
+ else:
+ gi = groups.values()
+ for form in sorted((form for g in gi for form in g),
key=lambda x:len(x.operands), reverse=True):
num_operands = len(form.operands)
- for i in xrange(len(all_operands)):
+ for i in range(len(all_operands)):
if all_operands[i:i+num_operands] == form.operands:
form.all_operands_index = i
break
@@ -592,12 +629,12 @@
all_operands.extend(form.operands)
# Output operands list
- print >>f, "/* Generated by %s r%s, do not edit */" % \
- (scriptname, scriptrev)
- print >>f, "static const x86_info_operand insn_operands[] = {"
- print >>f, " ",
- print >>f, ",\n ".join(str(x) for x in all_operands)
- print >>f, "};\n"
+ lprint("/* Generated by %s r%s, do not edit */" % \
+ (scriptname, scriptrev), f)
+ lprint("static const x86_info_operand insn_operands[] = {", f)
+ lprint(" ", f, '')
+ lprint(",\n ".join(str(x) for x in all_operands), f)
+ lprint("};\n", f)
# Output groups
seen = set()
@@ -605,10 +642,10 @@
if name in seen:
continue
seen.add(name)
- print >>f, "static const x86_insn_info %s_insn[] = {" % name
- print >>f, " ",
- print >>f, ",\n ".join(str(x) for x in groups[name])
- print >>f, "};\n"
+ lprint("static const x86_insn_info %s_insn[] = {" % name, f)
+ lprint(" ", f, '')
+ lprint(",\n ".join(str(x) for x in groups[name]), f)
+ lprint("};\n", f)
#####################################################################
# General instruction groupings
@@ -2189,15 +2226,18 @@
opcode=[],
operands=[Operand(type="ImmNotSegOff", dest="JmpRel")])
add_group("call",
+ suffix="w",
opersize=16,
opcode=[],
operands=[Operand(type="ImmNotSegOff", size=16, dest="JmpRel")])
add_group("call",
+ suffix="l",
not64=True,
opersize=32,
opcode=[],
operands=[Operand(type="ImmNotSegOff", size=32, dest="JmpRel")])
add_group("call",
+ suffixes=["l", "q"],
only64=True,
opersize=64,
opcode=[],
@@ -2225,59 +2265,77 @@
operands=[Operand(type="Imm", tmod="Near", dest="JmpRel")])
add_group("call",
+ suffix="w",
+ req_suffix=True,
opersize=16,
opcode=[0xFF],
spare=2,
operands=[Operand(type="RM", size=16, dest="EA")])
add_group("call",
+ suffix="l",
+ req_suffix=True,
not64=True,
opersize=32,
opcode=[0xFF],
spare=2,
operands=[Operand(type="RM", size=32, dest="EA")])
add_group("call",
+ suffix="q",
+ req_suffix=True,
opersize=64,
def_opersize_64=64,
opcode=[0xFF],
spare=2,
operands=[Operand(type="RM", size=64, dest="EA")])
add_group("call",
+ parsers=["gas"],
def_opersize_64=64,
opcode=[0xFF],
spare=2,
+ operands=[Operand(type="Reg", size="BITS", dest="EA")])
+add_group("call",
+ def_opersize_64=64,
+ opcode=[0xFF],
+ spare=2,
operands=[Operand(type="Mem", dest="EA")])
add_group("call",
+ parsers=["nasm"],
opersize=16,
def_opersize_64=64,
opcode=[0xFF],
spare=2,
operands=[Operand(type="RM", size=16, tmod="Near", dest="EA")])
add_group("call",
+ parsers=["nasm"],
not64=True,
opersize=32,
opcode=[0xFF],
spare=2,
operands=[Operand(type="RM", size=32, tmod="Near", dest="EA")])
add_group("call",
+ parsers=["nasm"],
opersize=64,
def_opersize_64=64,
opcode=[0xFF],
spare=2,
operands=[Operand(type="RM", size=64, tmod="Near", dest="EA")])
add_group("call",
+ parsers=["nasm"],
def_opersize_64=64,
opcode=[0xFF],
spare=2,
operands=[Operand(type="Mem", tmod="Near", dest="EA")])
-# Far indirect (through memory). Needs explicit FAR override.
+# Far indirect (through memory). Needs explicit FAR override (NASM only)
for sz in [16, 32, 64]:
add_group("call",
+ parsers=["nasm"],
opersize=sz,
opcode=[0xFF],
spare=3,
operands=[Operand(type="Mem", size=sz, tmod="Far", dest="EA")])
add_group("call",
+ parsers=["nasm"],
opcode=[0xFF],
spare=3,
operands=[Operand(type="Mem", tmod="Far", dest="EA")])
@@ -2285,34 +2343,52 @@
# With explicit FAR override
for sz in [16, 32]:
add_group("call",
+ parsers=["nasm"],
not64=True,
opersize=sz,
opcode=[0x9A],
- spare=3,
operands=[Operand(type="Imm", size=sz, tmod="Far", dest="JmpFar")])
add_group("call",
+ parsers=["nasm"],
not64=True,
opcode=[0x9A],
- spare=3,
operands=[Operand(type="Imm", tmod="Far", dest="JmpFar")])
-# Since not caught by first ImmNotSegOff group, implicitly FAR.
+# Since not caught by first ImmNotSegOff group, implicitly FAR (in NASM).
for sz in [16, 32]:
add_group("call",
+ parsers=["nasm"],
not64=True,
opersize=sz,
opcode=[0x9A],
- spare=3,
operands=[Operand(type="Imm", size=sz, dest="JmpFar")])
add_group("call",
+ parsers=["nasm"],
not64=True,
opcode=[0x9A],
- spare=3,
operands=[Operand(type="Imm", dest="JmpFar")])
+# Two-operand FAR (GAS only)
+for sfx, sz in zip("wl", [16, 32]):
+ add_group("call",
+ suffix=sfx,
+ req_suffix=True,
+ parsers=["gas"],
+ not64=True,
+ gas_no_reverse=True,
+ opersize=sz,
+ opcode=[0x9A],
+ operands=[Operand(type="Imm", size=16, relaxed=True, dest="JmpFar"),
+ Operand(type="Imm", size=sz, relaxed=True, dest="JmpFar")])
+add_group("call",
+ parsers=["gas"],
+ not64=True,
+ gas_no_reverse=True,
+ opcode=[0x9A],
+ operands=[Operand(type="Imm", size=16, relaxed=True, dest="JmpFar"),
+ Operand(type="Imm", size="BITS", relaxed=True, dest="JmpFar")])
+
add_insn("call", "call")
-add_insn("calll", "call", parser="gas", not64=True)
-add_insn("callq", "call", parser="gas", only64=True)
#
# jmp
@@ -2321,15 +2397,18 @@
opcode=[],
operands=[Operand(type="ImmNotSegOff", dest="JmpRel")])
add_group("jmp",
+ suffix="w",
opersize=16,
opcode=[],
operands=[Operand(type="ImmNotSegOff", size=16, dest="JmpRel")])
add_group("jmp",
+ suffix="l",
not64=True,
opersize=32,
opcode=[0x00],
operands=[Operand(type="ImmNotSegOff", size=32, dest="JmpRel")])
add_group("jmp",
+ suffixes=["l", "q"],
only64=True,
opersize=64,
opcode=[0x00],
@@ -2362,35 +2441,49 @@
operands=[Operand(type="Imm", tmod="Near", dest="JmpRel")])
add_group("jmp",
+ suffix="w",
+ req_suffix=True,
opersize=16,
def_opersize_64=64,
opcode=[0xFF],
spare=4,
operands=[Operand(type="RM", size=16, dest="EA")])
add_group("jmp",
+ suffix="l",
+ req_suffix=True,
not64=True,
opersize=32,
opcode=[0xFF],
spare=4,
operands=[Operand(type="RM", size=32, dest="EA")])
add_group("jmp",
+ suffix="q",
+ req_suffix=True,
opersize=64,
def_opersize_64=64,
opcode=[0xFF],
spare=4,
operands=[Operand(type="RM", size=64, dest="EA")])
add_group("jmp",
+ parsers=["gas"],
def_opersize_64=64,
opcode=[0xFF],
spare=4,
+ operands=[Operand(type="Reg", size="BITS", dest="EA")])
+add_group("jmp",
+ def_opersize_64=64,
+ opcode=[0xFF],
+ spare=4,
operands=[Operand(type="Mem", dest="EA")])
add_group("jmp",
+ parsers=["nasm"],
opersize=16,
def_opersize_64=64,
opcode=[0xFF],
spare=4,
operands=[Operand(type="RM", size=16, tmod="Near", dest="EA")])
add_group("jmp",
+ parsers=["nasm"],
not64=True,
cpu=["386"],
opersize=32,
@@ -2398,12 +2491,14 @@
spare=4,
operands=[Operand(type="RM", size=32, tmod="Near", dest="EA")])
add_group("jmp",
+ parsers=["nasm"],
opersize=64,
def_opersize_64=64,
opcode=[0xFF],
spare=4,
operands=[Operand(type="RM", size=64, tmod="Near", dest="EA")])
add_group("jmp",
+ parsers=["nasm"],
def_opersize_64=64,
opcode=[0xFF],
spare=4,
@@ -2427,31 +2522,92 @@
not64=True,
opersize=sz,
opcode=[0xEA],
- spare=3,
operands=[Operand(type="Imm", size=sz, tmod="Far", dest="JmpFar")])
add_group("jmp",
not64=True,
opcode=[0xEA],
- spare=3,
operands=[Operand(type="Imm", tmod="Far", dest="JmpFar")])
-# Since not caught by first ImmNotSegOff group, implicitly FAR.
+# Since not caught by first ImmNotSegOff group, implicitly FAR (in NASM).
for sz in [16, 32]:
add_group("jmp",
+ parsers=["nasm"],
not64=True,
opersize=sz,
opcode=[0xEA],
- spare=3,
operands=[Operand(type="Imm", size=sz, dest="JmpFar")])
add_group("jmp",
+ parsers=["nasm"],
not64=True,
opcode=[0xEA],
- spare=3,
operands=[Operand(type="Imm", dest="JmpFar")])
+# Two-operand FAR (GAS only)
+for sfx, sz in zip("wl", [16, 32]):
+ add_group("jmp",
+ parsers=["gas"],
+ suffix=sfx,
+ req_suffix=True,
+ not64=True,
+ gas_no_reverse=True,
+ opersize=sz,
+ opcode=[0xEA],
+ operands=[Operand(type="Imm", size=16, relaxed=True, dest="JmpFar"),
+ Operand(type="Imm", size=sz, relaxed=True, dest="JmpFar")])
+add_group("jmp",
+ parsers=["gas"],
+ not64=True,
+ gas_no_reverse=True,
+ opcode=[0xEA],
+ operands=[Operand(type="Imm", size=16, relaxed=True, dest="JmpFar"),
+ Operand(type="Imm", size="BITS", relaxed=True, dest="JmpFar")])
+
add_insn("jmp", "jmp")
#
+# GAS far calls/jumps
+#
+
+# Far indirect (through memory)
+for sfx, sz in zip("wlq", [16, 32, 64]):
+ add_group("ljmpcall",
+ suffix=sfx,
+ req_suffix=True,
+ opersize=sz,
+ modifiers=["SpAdd"],
+ opcode=[0xFF],
+ spare=0,
+ operands=[Operand(type="Mem", size=sz, relaxed=True, dest="EA")])
+add_group("ljmpcall",
+ modifiers=["SpAdd"],
+ opcode=[0xFF],
+ spare=0,
+ operands=[Operand(type="Mem", size="BITS", relaxed=True, dest="EA")])
+
+# Two-operand far
+for sfx, sz in zip("wl", [16, 32]):
+ add_group("ljmpcall",
+ not64=True,
+ gas_no_reverse=True,
+ suffix=sfx,
+ req_suffix=True,
+ opersize=sz,
+ modifiers=["Gap", "Op0Add"],
+ opcode=[0x00],
+ operands=[Operand(type="Imm", size=16, relaxed=True, dest="JmpFar"),
+ Operand(type="Imm", size=sz, relaxed=True, dest="JmpFar")])
+add_group("ljmpcall",
+ not64=True,
+ gas_no_reverse=True,
+ modifiers=["Gap", "Op0Add"],
+ opcode=[0x00],
+ operands=[Operand(type="Imm", size=16, relaxed=True, dest="JmpFar"),
+ Operand(type="Imm", size="BITS", relaxed=True, dest="JmpFar")])
+
+add_insn("ljmp", "ljmpcall", parser="gas", modifiers=[5, 0xEA])
+add_insn("lcall", "ljmpcall", parser="gas", modifiers=[3, 0x9A])
+
+#
# ret
#
add_group("retnf",
@@ -2494,10 +2650,11 @@
add_insn("retq", "retnf", parser="gas", modifiers=[0xC2], only64=True)
add_insn("retn", "retnf", parser="nasm", modifiers=[0xC2])
add_insn("retf", "retnf", parser="nasm", modifiers=[0xCA, 64])
-add_insn("lretw", "retnf", parser="gas", modifiers=[0xCA, 16], suffix="NONE")
-add_insn("lretl", "retnf", parser="gas", modifiers=[0xCA], suffix="NONE")
+add_insn("lret", "retnf", parser="gas", modifiers=[0xCA], suffix="z")
+add_insn("lretw", "retnf", parser="gas", modifiers=[0xCA, 16], suffix="w")
+add_insn("lretl", "retnf", parser="gas", modifiers=[0xCA], suffix="l")
add_insn("lretq", "retnf", parser="gas", modifiers=[0xCA, 64], only64=True,
- suffix="NONE")
+ suffix="q")
#
# enter
@@ -2690,6 +2847,45 @@
add_insn("loopnz", "loop", modifiers=[0])
add_insn("loopne", "loop", modifiers=[0])
+# GAS w/l/q suffixes have to set addrsize via modifiers
+for sfx, sz in zip("wlq", [16, 32, 64]):
+ add_group("loop"+sfx,
+ not64=(sz == 16),
+ only64=(sz == 64),
+ modifiers=["Gap", "AdSizeR"],
+ def_opersize_64=64,
+ opcode=[],
+ operands=[Operand(type="Imm", dest="JmpRel")])
+ add_group("loop"+sfx,
+ not64=(sz == 16),
+ only64=(sz == 64),
+ modifiers=["Op0Add", "AdSizeR"],
+ def_opersize_64=64,
+ opcode=[0xE0],
+ operands=[Operand(type="Imm", tmod="Short", dest="JmpRel")])
+
+ add_group("loop"+sfx,
+ not64=(sz == 16),
+ only64=(sz == 64),
+ def_opersize_64=64,
+ opcode=[],
+ operands=[Operand(type="Imm", dest="JmpRel"),
+ Operand(type="Creg", size=sz, dest="AdSizeR")])
+ add_group("loop"+sfx,
+ not64=(sz == 16),
+ only64=(sz == 64),
+ modifiers=["Op0Add"],
+ def_opersize_64=64,
+ opcode=[0xE0],
+ operands=[Operand(type="Imm", tmod="Short", dest="JmpRel"),
+ Operand(type="Creg", size=sz, dest="AdSizeR")])
+
+ add_insn("loop"+sfx, "loop"+sfx, parser="gas", modifiers=[2, sz])
+ add_insn("loopz"+sfx, "loop"+sfx, parser="gas", modifiers=[1, sz])
+ add_insn("loope"+sfx, "loop"+sfx, parser="gas", modifiers=[1, sz])
+ add_insn("loopnz"+sfx, "loop"+sfx, parser="gas", modifiers=[0, sz])
+ add_insn("loopne"+sfx, "loop"+sfx, parser="gas", modifiers=[0, sz])
+
#####################################################################
# Set byte on flag instructions
#####################################################################
@@ -3074,10 +3270,10 @@
modifiers=["SpAdd"],
opcode=[0xDB],
spare=0,
- operands=[Operand(type="Mem", size=80, dest="EA")])
+ operands=[Operand(type="Mem", size=80, relaxed=True, dest="EA")])
-add_insn("fldt", "fldstpt", suffix="WEAK", modifiers=[5])
-add_insn("fstpt", "fldstpt", suffix="WEAK", modifiers=[7])
+add_insn("fldt", "fldstpt", modifiers=[5])
+add_insn("fstpt", "fldstpt", modifiers=[7])
add_group("fildstp",
suffix="s",
@@ -4660,6 +4856,7 @@
suffix="q",
cpu=["MMX", "P3"],
notavx=True,
+ def_opersize_64=64,
opersize=64,
opcode=[0x0F, 0xC4],
operands=[Operand(type="SIMDReg", size=64, dest="Spare"),
@@ -4686,6 +4883,7 @@
suffix="q",
cpu=["SSE2"],
modifiers=["SetVEX"],
+ def_opersize_64=64,
opersize=64,
prefix=0x66,
opcode=[0x0F, 0xC4],
@@ -4715,6 +4913,7 @@
suffix="q",
cpu=["AVX"],
vex=128,
+ def_opersize_64=64,
opersize=64,
prefix=0x66,
opcode=[0x0F, 0xC4],
@@ -5077,6 +5276,28 @@
# P4 VMX Instructions
#####################################################################
+add_group("eptvpid",
+ modifiers=["Op2Add"],
+ suffix="l",
+ not64=True,
+ cpu=["EPTVPID"],
+ opersize=32,
+ prefix=0x66,
+ opcode=[0x0F, 0x38, 0x80],
+ operands=[Operand(type="Reg", size=32, dest="Spare"),
+ Operand(type="Mem", size=128, relaxed=True, dest="EA")])
+add_group("eptvpid",
+ modifiers=["Op2Add"],
+ suffix="q",
+ cpu=["EPTVPID"],
+ opersize=64,
+ prefix=0x66,
+ opcode=[0x0F, 0x38, 0x80],
+ operands=[Operand(type="Reg", size=64, dest="Spare"),
+ Operand(type="Mem", size=128, relaxed=True, dest="EA")])
+add_insn("invept", "eptvpid", modifiers=[0])
+add_insn("invvpid", "eptvpid", modifiers=[1])
+
add_insn("vmcall", "threebyte", modifiers=[0x0F, 0x01, 0xC1], cpu=["P4"])
add_insn("vmlaunch", "threebyte", modifiers=[0x0F, 0x01, 0xC2], cpu=["P4"])
add_insn("vmresume", "threebyte", modifiers=[0x0F, 0x01, 0xC3], cpu=["P4"])
@@ -5137,6 +5358,11 @@
add_insn("vmclear", "vmxthreebytemem", modifiers=[0x66])
add_insn("vmxon", "vmxthreebytemem", modifiers=[0xF3])
+#####################################################################
+# Intel SMX Instructions
+#####################################################################
+add_insn("getsec", "twobyte", modifiers=[0x0F, 0x37], cpu=["SMX"])
+
add_insn("cvttpd2pi", "cvt_mm_xmm", modifiers=[0x66, 0x2C], cpu=["SSE2"])
add_insn("cvttsd2si", "cvt_rx_xmm64", modifiers=[0xF2, 0x2C], cpu=["SSE2"])
add_insn("cvttpd2dq", "xmm_xmm128", modifiers=[0x66, 0xE6], cpu=["SSE2"])
@@ -5584,7 +5810,6 @@
add_group("extractps",
cpu=["SSE41"],
modifiers=["SetVEX"],
- opersize=32,
prefix=0x66,
opcode=[0x0F, 0x3A, 0x17],
operands=[Operand(type="RM", size=32, relaxed=True, dest="EA"),
@@ -5679,16 +5904,23 @@
operands=[Operand(type="Mem", size=8, relaxed=True, dest="EA"),
Operand(type="SIMDReg", size=128, dest="Spare"),
Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
-for sz in [32, 64]:
- add_group("pextrb",
- cpu=["SSE41"],
- modifiers=["SetVEX"],
- opersize=sz,
- prefix=0x66,
- opcode=[0x0F, 0x3A, 0x14],
- operands=[Operand(type="Reg", size=sz, dest="EA"),
- Operand(type="SIMDReg", size=128, dest="Spare"),
- Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
+add_group("pextrb",
+ cpu=["SSE41"],
+ modifiers=["SetVEX"],
+ prefix=0x66,
+ opcode=[0x0F, 0x3A, 0x14],
+ operands=[Operand(type="Reg", size=32, dest="EA"),
+ Operand(type="SIMDReg", size=128, dest="Spare"),
+ Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
+add_group("pextrb",
+ cpu=["SSE41"],
+ modifiers=["SetVEX"],
+ opersize=64,
+ prefix=0x66,
+ opcode=[0x0F, 0x3A, 0x14],
+ operands=[Operand(type="Reg", size=64, dest="EA"),
+ Operand(type="SIMDReg", size=128, dest="Spare"),
+ Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
add_insn("pextrb", "pextrb")
add_insn("vpextrb", "pextrb", modifiers=[VEXL0], avx=True)
@@ -5696,7 +5928,6 @@
add_group("pextrd",
cpu=["SSE41"],
modifiers=["SetVEX"],
- opersize=32,
prefix=0x66,
opcode=[0x0F, 0x3A, 0x16],
operands=[Operand(type="RM", size=32, relaxed=True, dest="EA"),
@@ -5730,7 +5961,6 @@
add_group("pinsrb",
cpu=["SSE41"],
modifiers=["SetVEX"],
- opersize=32,
prefix=0x66,
opcode=[0x0F, 0x3A, 0x20],
operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"),
@@ -5748,7 +5978,6 @@
add_group("pinsrb",
cpu=["AVX"],
vex=128,
- opersize=32,
prefix=0x66,
opcode=[0x0F, 0x3A, 0x20],
operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"),
@@ -5762,7 +5991,6 @@
add_group("pinsrd",
cpu=["SSE41"],
modifiers=["SetVEX"],
- opersize=32,
prefix=0x66,
opcode=[0x0F, 0x3A, 0x22],
operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"),
@@ -5771,7 +5999,6 @@
add_group("pinsrd",
cpu=["AVX"],
vex=128,
- opersize=32,
prefix=0x66,
opcode=[0x0F, 0x3A, 0x22],
operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
@@ -6458,7 +6685,7 @@
modifiers=["Op1Add", "Op2Add", "SetVEX"],
prefix=0x66,
opcode=[0x0F, 0x00, 0x00],
- operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"),
+ operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
add_insn("aesimc", "aesimc", modifiers=[0x38, 0xDB])
@@ -6527,6 +6754,122 @@
modifiers=[combval, VEXL0], avx=True)
#####################################################################
+# AVX Post-32nm instructions
+#####################################################################
+
+# RDRAND
+add_group("rdrand",
+ cpu=["RDRAND"],
+ opersize=16,
+ opcode=[0x0F, 0xC7],
+ spare=6,
+ operands=[Operand(type="Reg", size=16, dest="EA")])
+add_group("rdrand",
+ #suffix="l",
+ cpu=["RDRAND"],
+ opersize=32,
+ opcode=[0x0F, 0xC7],
+ spare=6,
+ operands=[Operand(type="Reg", size=32, dest="EA")])
+add_group("rdrand",
+ cpu=["RDRAND"],
+ opersize=64,
+ opcode=[0x0F, 0xC7],
+ spare=6,
+ operands=[Operand(type="Reg", size=64, dest="EA")])
+add_insn("rdrand", "rdrand")
+
+# FSGSBASE instructions
+add_group("fs_gs_base",
+ only64=True,
+ cpu=["FSGSBASE"],
+ modifiers=['SpAdd'],
+ opersize=32,
+ prefix=0xF3,
+ opcode=[0x0F, 0xAE],
+ operands=[Operand(type="Reg", size=32, dest="EA")])
+add_group("fs_gs_base",
+ only64=True,
+ cpu=["FSGSBASE"],
+ opersize=64,
+ modifiers=['SpAdd'],
+ prefix=0xF3,
+ opcode=[0x0F, 0xAE],
+ operands=[Operand(type="Reg", size=64, dest="EA")])
+
+add_insn("rdfsbase", "fs_gs_base", modifiers=[0], only64=True)
+add_insn("rdgsbase", "fs_gs_base", modifiers=[1], only64=True)
+add_insn("wrfsbase", "fs_gs_base", modifiers=[2], only64=True)
+add_insn("wrgsbase", "fs_gs_base", modifiers=[3], only64=True)
+
+# Float-16 conversion instructions
+for g in ['ps2ph', 'ph2ps']:
+ operands1=[]
+ operands1.append(Operand(type="SIMDReg", size=128, dest="EA"))
+ operands1.append(Operand(type="SIMDReg", size=128, dest="Spare"))
+
+ operands2=[]
+ operands2.append(Operand(type="Mem", size=64, dest="EA"))
+ operands2.append(Operand(type="SIMDReg", size=128, dest="Spare"))
+
+ operands3=[]
+ operands3.append(Operand(type="SIMDReg", size=128, dest="EA"))
+ operands3.append(Operand(type="SIMDReg", size=256, dest="Spare"))
+
+ operands4=[]
+ operands4.append(Operand(type="Mem", size=128, dest="EA"))
+ operands4.append(Operand(type="SIMDReg", size=256, dest="Spare"))
+
+ if g == 'ph2ps':
+ operands1.reverse()
+ operands2.reverse()
+ operands3.reverse()
+ operands4.reverse()
+ map = 0x38
+ elif g == 'ps2ph':
+ immop = Operand(type="Imm", size=8, relaxed=True, dest="Imm")
+ operands1.append(immop)
+ operands2.append(immop)
+ operands3.append(immop)
+ operands4.append(immop)
+ map = 0x3A
+
+ add_group("avx_cvt" + g,
+ cpu=["F16C", "AVX"],
+ modifiers=["PreAdd", "Op2Add"],
+ vex=128,
+ prefix=0x00,
+ opcode=[0x0F, map, 0x00],
+ operands=operands1)
+
+ add_group("avx_cvt" + g,
+ cpu=["F16C", "AVX"],
+ modifiers=["PreAdd", "Op2Add"],
+ vex=128,
+ prefix=0x00,
+ opcode=[0x0F, map, 0x00],
+ operands=operands2)
+
+ add_group("avx_cvt" + g,
+ cpu=["F16C", "AVX"],
+ modifiers=["PreAdd", "Op2Add"],
+ vex=256,
+ prefix=0x00,
+ opcode=[0x0F, map, 0x00],
+ operands=operands3)
+
+ add_group("avx_cvt" + g,
+ cpu=["F16C", "AVX"],
+ modifiers=["PreAdd", "Op2Add"],
+ vex=256,
+ prefix=0x00,
+ opcode=[0x0F, map, 0x00],
+ operands=operands4)
+
+add_insn("vcvtps2ph", "avx_cvtps2ph", modifiers=[0x66, 0x1D], avx=True)
+add_insn("vcvtph2ps", "avx_cvtph2ps", modifiers=[0x66, 0x13], avx=True)
+
+#####################################################################
# AMD SSE4a instructions
#####################################################################
@@ -6582,404 +6925,354 @@
add_insn("movntss", "movntss")
#####################################################################
-# AMD SSE5 instructions
+# AMD XOP instructions
#####################################################################
-add_group("sse5com",
- cpu=["SSE5"],
- modifiers=["Op2Add"],
- opcode=[0x0F, 0x25, 0x00],
- drex_oc0=0,
- operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
- Operand(type="SIMDReg", size=128, dest="Spare"),
- Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
- Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
-
-for sz in [32, 64]:
- add_group("sse5com%d" % sz,
- cpu=["SSE5"],
- modifiers=["Op2Add"],
- opcode=[0x0F, 0x25, 0x00],
- drex_oc0=0,
- operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
- Operand(type="SIMDReg", size=128, dest="Spare"),
- Operand(type="SIMDReg", size=128, dest="EA"),
- Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
- add_group("sse5com%d" % sz,
- cpu=["SSE5"],
- modifiers=["Op2Add"],
- opcode=[0x0F, 0x25, 0x00],
- drex_oc0=0,
- operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
- Operand(type="SIMDReg", size=128, dest="Spare"),
- Operand(type="Mem", size=sz, relaxed=True, dest="EA"),
- Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
-
-# Condition code versions
-add_group("sse5comcc",
- cpu=["SSE5"],
- modifiers=["Op2Add", "Imm8"],
- opcode=[0x0F, 0x25, 0x00],
- drex_oc0=0,
- operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
- Operand(type="SIMDReg", size=128, dest="Spare"),
+add_group("vfrc_pdps",
+ cpu=["XOP"],
+ modifiers=["Op1Add"],
+ xop=128,
+ opcode=[0x09, 0x80],
+ operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
+add_group("vfrc_pdps",
+ cpu=["XOP"],
+ modifiers=["Op1Add"],
+ xop=256,
+ opcode=[0x09, 0x80],
+ operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
+ Operand(type="SIMDRM", size=256, relaxed=True, dest="EA")])
+add_insn("vfrczpd", "vfrc_pdps", modifiers=[0x01])
+add_insn("vfrczps", "vfrc_pdps", modifiers=[0x00])
-for sz in [32, 64]:
- add_group("sse5comcc%d" % sz,
- cpu=["SSE5"],
- modifiers=["Op2Add", "Imm8"],
- opcode=[0x0F, 0x25, 0x00],
- drex_oc0=0,
- operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
- Operand(type="SIMDReg", size=128, dest="Spare"),
- Operand(type="SIMDReg", size=128, dest="EA")])
- add_group("sse5comcc%d" % sz,
- cpu=["SSE5"],
- modifiers=["Op2Add", "Imm8"],
- opcode=[0x0F, 0x25, 0x00],
- drex_oc0=0,
- operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
- Operand(type="SIMDReg", size=128, dest="Spare"),
- Operand(type="Mem", size=sz, relaxed=True, dest="EA")])
-
-sse5coms = [(0, ""),
- (0x0, "eq"),
- (0x1, "lt"), (0x1, "unge"),
- (0x2, "le"), (0x2, "ungt"),
- (0x3, "unord"),
- (0x4, "ne"), (0x4, "neq"),
- (0x5, "nlt"), (0x5, "uge"),
- (0x6, "nle"), (0x6, "ugt"),
- (0x7, "ord"),
- (0x8, "ueq"),
- (0x9, "ult"), (0x9, "nge"),
- (0xa, "ule"), (0xa, "ngt"),
- (0xb, "false"),
- (0xc, "une"), (0xc, "uneq"),
- (0xd, "unlt"), (0xd, "ge"),
- (0xe, "unle"), (0xe, "gt"),
- (0xf, "true")]
-for ib, cc in sse5coms:
- if cc:
- iname = "sse5comcc"
- else:
- iname = "sse5com"
- add_insn("com"+cc+"ps", iname, modifiers=[0x2C, ib])
- add_insn("com"+cc+"pd", iname, modifiers=[0x2D, ib])
- add_insn("com"+cc+"ss", iname+"32", modifiers=[0x2E, ib])
- add_insn("com"+cc+"sd", iname+"64", modifiers=[0x2F, ib])
-
-sse5coms = list(enumerate(["lt", "le", "gt", "ge",
- "eq", "neq", "false", "true"]))
-sse5coms.append((5, "ne"))
-sse5coms.append((0, ""))
-for ib, cc in sse5coms:
- if cc:
- iname = "sse5comcc"
- else:
- iname = "sse5com"
- add_insn("pcom"+cc+"b", iname, modifiers=[0x4C, ib])
- add_insn("pcom"+cc+"w", iname, modifiers=[0x4D, ib])
- add_insn("pcom"+cc+"d", iname, modifiers=[0x4E, ib])
- add_insn("pcom"+cc+"q", iname, modifiers=[0x4F, ib])
-
- add_insn("pcom"+cc+"ub", iname, modifiers=[0x6C, ib])
- add_insn("pcom"+cc+"uw", iname, modifiers=[0x6D, ib])
- add_insn("pcom"+cc+"ud", iname, modifiers=[0x6E, ib])
- add_insn("pcom"+cc+"uq", iname, modifiers=[0x6F, ib])
-
-add_group("cvtph2ps",
- cpu=["SSE5"],
- opcode=[0x0F, 0x7A, 0x30],
+add_group("vfrczsd",
+ cpu=["XOP"],
+ xop=128,
+ opcode=[0x09, 0x83],
operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
Operand(type="SIMDReg", size=128, dest="EA")])
-add_group("cvtph2ps",
- cpu=["SSE5"],
- opcode=[0x0F, 0x7A, 0x30],
+add_group("vfrczsd",
+ cpu=["XOP"],
+ xop=128,
+ opcode=[0x09, 0x83],
operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
Operand(type="Mem", size=64, relaxed=True, dest="EA")])
+add_insn("vfrczsd", "vfrczsd")
-add_insn("cvtph2ps", "cvtph2ps")
+add_group("vfrczss",
+ cpu=["XOP"],
+ xop=128,
+ opcode=[0x09, 0x82],
+ operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+ Operand(type="SIMDReg", size=128, dest="EA")])
+add_group("vfrczss",
+ cpu=["XOP"],
+ xop=128,
+ opcode=[0x09, 0x82],
+ operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+ Operand(type="Mem", size=32, relaxed=True, dest="EA")])
+add_insn("vfrczss", "vfrczss")
-add_group("cvtps2ph",
- cpu=["SSE5"],
- opcode=[0x0F, 0x7A, 0x31],
- operands=[Operand(type="SIMDReg", size=128, dest="EA"),
- Operand(type="SIMDReg", size=128, dest="Spare")])
-add_group("cvtps2ph",
- cpu=["SSE5"],
- opcode=[0x0F, 0x7A, 0x31],
- operands=[Operand(type="Mem", size=64, relaxed=True, dest="EA"),
- Operand(type="SIMDReg", size=128, dest="Spare")])
+add_group("vpcmov",
+ cpu=["XOP"],
+ xop=128,
+ xopw=0,
+ opcode=[0x08, 0xA2],
+ operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+ Operand(type="SIMDReg", size=128, dest="VEX"),
+ Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
+ Operand(type="SIMDReg", size=128, dest="VEXImmSrc")])
+add_group("vpcmov",
+ cpu=["XOP"],
+ xop=128,
+ xopw=1,
+ opcode=[0x08, 0xA2],
+ operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+ Operand(type="SIMDReg", size=128, dest="VEX"),
+ Operand(type="SIMDReg", size=128, dest="VEXImmSrc"),
+ Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
+add_group("vpcmov",
+ cpu=["XOP"],
+ xop=256,
+ xopw=0,
+ opcode=[0x08, 0xA2],
+ operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
+ Operand(type="SIMDReg", size=256, dest="VEX"),
+ Operand(type="SIMDRM", size=256, relaxed=True, dest="EA"),
+ Operand(type="SIMDReg", size=256, dest="VEXImmSrc")])
+add_group("vpcmov",
+ cpu=["XOP"],
+ xop=256,
+ xopw=1,
+ opcode=[0x08, 0xA2],
+ operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
+ Operand(type="SIMDReg", size=256, dest="VEX"),
+ Operand(type="SIMDReg", size=256, dest="VEXImmSrc"),
+ Operand(type="SIMDRM", size=256, relaxed=True, dest="EA")])
-add_insn("cvtps2ph", "cvtps2ph")
+add_insn("vpcmov", "vpcmov")
-add_group("sse5arith",
- cpu=["SSE5"],
- modifiers=["Op2Add"],
- opcode=[0x0F, 0x24, 0x00],
- drex_oc0=0,
- operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
- Operand(type="SIMDRegMatch0", size=128, dest=None),
- Operand(type="SIMDReg", size=128, dest="Spare"),
+add_group("vpcom",
+ cpu=["XOP"],
+ modifiers=["Op1Add", "Imm8"],
+ xop=128,
+ opcode=[0x08, 0x00],
+ operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+ Operand(type="SIMDReg", size=128, dest="VEX"),
Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
-add_group("sse5arith",
- cpu=["SSE5"],
- modifiers=["Op2Add"],
- opcode=[0x0F, 0x24, 0x00],
- drex_oc0=1,
- operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
- Operand(type="SIMDRegMatch0", size=128, dest=None),
+add_group("vpcom_imm",
+ cpu=["XOP"],
+ modifiers=["Op1Add"],
+ xop=128,
+ opcode=[0x08, 0x00],
+ operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+ Operand(type="SIMDReg", size=128, dest="VEX"),
Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
- Operand(type="SIMDReg", size=128, dest="Spare")])
-add_group("sse5arith",
- cpu=["SSE5"],
- modifiers=["Op2Add"],
- opcode=[0x0F, 0x24, 0x04],
- drex_oc0=0,
- operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
- Operand(type="SIMDReg", size=128, dest="Spare"),
- Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
- Operand(type="SIMDRegMatch0", size=128, dest=None)])
-add_group("sse5arith",
- cpu=["SSE5"],
- modifiers=["Op2Add"],
- opcode=[0x0F, 0x24, 0x04],
- drex_oc0=1,
- operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
- Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
- Operand(type="SIMDReg", size=128, dest="Spare"),
- Operand(type="SIMDRegMatch0", size=128, dest=None)])
+ Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
-for sz in [32, 64]:
- add_group("sse5arith%d" % sz,
- cpu=["SSE5"],
- modifiers=["Op2Add"],
- opcode=[0x0F, 0x24, 0x00],
- drex_oc0=0,
- operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
- Operand(type="SIMDRegMatch0", size=128, dest=None),
- Operand(type="SIMDReg", size=128, dest="Spare"),
- Operand(type="SIMDReg", size=128, dest="EA")])
- add_group("sse5arith%d" % sz,
- cpu=["SSE5"],
- modifiers=["Op2Add"],
- opcode=[0x0F, 0x24, 0x00],
- drex_oc0=0,
- operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
- Operand(type="SIMDRegMatch0", size=128, dest=None),
- Operand(type="SIMDReg", size=128, dest="Spare"),
- Operand(type="Mem", size=sz, relaxed=True, dest="EA")])
- add_group("sse5arith%d" % sz,
- cpu=["SSE5"],
- modifiers=["Op2Add"],
- opcode=[0x0F, 0x24, 0x00],
- drex_oc0=1,
- operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
- Operand(type="SIMDRegMatch0", size=128, dest=None),
- Operand(type="SIMDReg", size=128, dest="EA"),
- Operand(type="SIMDReg", size=128, dest="Spare")])
- add_group("sse5arith%d" % sz,
- cpu=["SSE5"],
- modifiers=["Op2Add"],
- opcode=[0x0F, 0x24, 0x00],
- drex_oc0=1,
- operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
- Operand(type="SIMDRegMatch0", size=128, dest=None),
- Operand(type="Mem", size=sz, relaxed=True, dest="EA"),
- Operand(type="SIMDReg", size=128, dest="Spare")])
- add_group("sse5arith%d" % sz,
- cpu=["SSE5"],
- modifiers=["Op2Add"],
- opcode=[0x0F, 0x24, 0x04],
- drex_oc0=0,
- operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
- Operand(type="SIMDReg", size=128, dest="Spare"),
- Operand(type="SIMDReg", size=128, dest="EA"),
- Operand(type="SIMDRegMatch0", size=128, dest=None)])
- add_group("sse5arith%d" % sz,
- cpu=["SSE5"],
- modifiers=["Op2Add"],
- opcode=[0x0F, 0x24, 0x04],
- drex_oc0=0,
- operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
- Operand(type="SIMDReg", size=128, dest="Spare"),
- Operand(type="Mem", size=sz, relaxed=True, dest="EA"),
- Operand(type="SIMDRegMatch0", size=128, dest=None)])
- add_group("sse5arith%d" % sz,
- cpu=["SSE5"],
- modifiers=["Op2Add"],
- opcode=[0x0F, 0x24, 0x04],
- drex_oc0=1,
- operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
- Operand(type="SIMDReg", size=128, dest="EA"),
- Operand(type="SIMDReg", size=128, dest="Spare"),
- Operand(type="SIMDRegMatch0", size=128, dest=None)])
- add_group("sse5arith%d" % sz,
- cpu=["SSE5"],
- modifiers=["Op2Add"],
- opcode=[0x0F, 0x24, 0x04],
- drex_oc0=1,
- operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
- Operand(type="Mem", size=sz, relaxed=True, dest="EA"),
- Operand(type="SIMDReg", size=128, dest="Spare"),
- Operand(type="SIMDRegMatch0", size=128, dest=None)])
+for opc, sfx in [(0xCC, "b"),
+ (0xCE, "d"),
+ (0xCD, "w"),
+ (0xCF, "q"),
+ (0xEC, "ub"),
+ (0xEE, "ud"),
+ (0xEF, "uq"),
+ (0xED, "uw")]:
+ add_insn("vpcom"+sfx, "vpcom_imm", modifiers=[opc])
+ for ib, cc in enumerate(["lt", "le", "gt", "ge",
+ "eq", "neq", "false", "true"]):
+ add_insn("vpcom"+cc+sfx, "vpcom", modifiers=[opc, ib])
+ # ne alias for neq
+ add_insn("vpcomne"+sfx, "vpcom", modifiers=[opc, 5])
-add_insn("fmaddps", "sse5arith", modifiers=[0x00])
-add_insn("fmaddpd", "sse5arith", modifiers=[0x01])
-add_insn("fmaddss", "sse5arith32", modifiers=[0x02])
-add_insn("fmaddsd", "sse5arith64", modifiers=[0x03])
+add_group("vphaddsub",
+ cpu=["XOP"],
+ modifiers=["Op1Add"],
+ xop=128,
+ opcode=[0x09, 0x00],
+ operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+ Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
-add_insn("fmsubps", "sse5arith", modifiers=[0x08])
-add_insn("fmsubpd", "sse5arith", modifiers=[0x09])
-add_insn("fmsubss", "sse5arith32", modifiers=[0x0A])
-add_insn("fmsubsd", "sse5arith64", modifiers=[0x0B])
+add_insn("vphaddbw", "vphaddsub", modifiers=[0xC1])
+add_insn("vphaddbd", "vphaddsub", modifiers=[0xC2])
+add_insn("vphaddbq", "vphaddsub", modifiers=[0xC3])
+add_insn("vphaddwd", "vphaddsub", modifiers=[0xC6])
+add_insn("vphaddwq", "vphaddsub", modifiers=[0xC7])
+add_insn("vphadddq", "vphaddsub", modifiers=[0xCB])
-add_insn("fnmaddps", "sse5arith", modifiers=[0x10])
-add_insn("fnmaddpd", "sse5arith", modifiers=[0x11])
-add_insn("fnmaddss", "sse5arith32", modifiers=[0x12])
-add_insn("fnmaddsd", "sse5arith64", modifiers=[0x13])
+add_insn("vphaddubw", "vphaddsub", modifiers=[0xD1])
+add_insn("vphaddubd", "vphaddsub", modifiers=[0xD2])
+add_insn("vphaddubq", "vphaddsub", modifiers=[0xD3])
+add_insn("vphadduwd", "vphaddsub", modifiers=[0xD6])
+add_insn("vphadduwq", "vphaddsub", modifiers=[0xD7])
+add_insn("vphaddudq", "vphaddsub", modifiers=[0xD8])
-add_insn("fnmsubps", "sse5arith", modifiers=[0x18])
-add_insn("fnmsubpd", "sse5arith", modifiers=[0x19])
-add_insn("fnmsubss", "sse5arith32", modifiers=[0x1A])
-add_insn("fnmsubsd", "sse5arith64", modifiers=[0x1B])
+add_insn("vphsubbw", "vphaddsub", modifiers=[0xE1])
+add_insn("vphsubwd", "vphaddsub", modifiers=[0xE2])
+add_insn("vphsubdq", "vphaddsub", modifiers=[0xE3])
-add_insn("pcmov", "sse5arith", modifiers=[0x22])
+add_group("vpma",
+ cpu=["XOP"],
+ modifiers=["Op1Add"],
+ xop=128,
+ opcode=[0x08, 0x00],
+ operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+ Operand(type="SIMDReg", size=128, dest="VEX"),
+ Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
+ Operand(type="SIMDReg", size=128, dest="VEXImmSrc")])
-add_insn("permps", "sse5arith", modifiers=[0x20])
-add_insn("permpd", "sse5arith", modifiers=[0x21])
-add_insn("pperm", "sse5arith", modifiers=[0x23])
+add_insn("vpmacsdd", "vpma", modifiers=[0x9E])
+add_insn("vpmacsdqh", "vpma", modifiers=[0x9F])
+add_insn("vpmacsdql", "vpma", modifiers=[0x97])
+add_insn("vpmacssdd", "vpma", modifiers=[0x8E])
+add_insn("vpmacssdqh", "vpma", modifiers=[0x8F])
+add_insn("vpmacssdql", "vpma", modifiers=[0x87])
+add_insn("vpmacsswd", "vpma", modifiers=[0x86])
+add_insn("vpmacssww", "vpma", modifiers=[0x85])
+add_insn("vpmacswd", "vpma", modifiers=[0x96])
+add_insn("vpmacsww", "vpma", modifiers=[0x95])
+add_insn("vpmadcsswd", "vpma", modifiers=[0xA6])
+add_insn("vpmadcswd", "vpma", modifiers=[0xB6])
-add_group("sse5two",
- cpu=["SSE5"],
- modifiers=["Op2Add"],
- opcode=[0x0F, 0x7A, 0x00],
+add_group("vpperm",
+ cpu=["XOP"],
+ xop=128,
+ xopw=0,
+ opcode=[0x08, 0xA3],
operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+ Operand(type="SIMDReg", size=128, dest="VEX"),
+ Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
+ Operand(type="SIMDReg", size=128, dest="VEXImmSrc")])
+add_group("vpperm",
+ cpu=["XOP"],
+ xop=128,
+ xopw=1,
+ opcode=[0x08, 0xA3],
+ operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+ Operand(type="SIMDReg", size=128, dest="VEX"),
+ Operand(type="SIMDReg", size=128, dest="VEXImmSrc"),
Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
-for sz in [32, 64]:
- add_group("sse5two%d" % sz,
- cpu=["SSE5"],
- modifiers=["Op2Add"],
- opcode=[0x0F, 0x7A, 0x00],
- operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
- Operand(type="SIMDReg", size=128, dest="EA")])
- add_group("sse5two%d" % sz,
- cpu=["SSE5"],
- modifiers=["Op2Add"],
- opcode=[0x0F, 0x7A, 0x00],
- operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
- Operand(type="Mem", size=sz, relaxed=True, dest="EA")])
+add_insn("vpperm", "vpperm")
-add_insn("frczps", "sse5two", modifiers=[0x10])
-add_insn("frczpd", "sse5two", modifiers=[0x11])
-add_insn("frczss", "sse5two32", modifiers=[0x12])
-add_insn("frczsd", "sse5two64", modifiers=[0x13])
+add_group("vprot",
+ cpu=["XOP"],
+ modifiers=["Op1Add"],
+ xop=128,
+ xopw=0,
+ opcode=[0x09, 0x90],
+ operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+ Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
+ Operand(type="SIMDReg", size=128, dest="VEX")])
+add_group("vprot",
+ cpu=["XOP"],
+ modifiers=["Op1Add"],
+ xop=128,
+ xopw=1,
+ opcode=[0x09, 0x90],
+ operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+ Operand(type="SIMDReg", size=128, dest="VEX"),
+ Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
+add_group("vprot",
+ cpu=["XOP"],
+ modifiers=["Op1Add"],
+ xop=128,
+ opcode=[0x08, 0xC0],
+ operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+ Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
+ Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
+for opc, sfx in enumerate(["b", "w", "d", "q"]):
+ add_insn("vprot"+sfx, "vprot", modifiers=[opc])
-add_insn("phaddbw", "sse5two", modifiers=[0x41])
-add_insn("phaddbd", "sse5two", modifiers=[0x42])
-add_insn("phaddbq", "sse5two", modifiers=[0x43])
-add_insn("phaddwd", "sse5two", modifiers=[0x46])
-add_insn("phaddwq", "sse5two", modifiers=[0x47])
-add_insn("phadddq", "sse5two", modifiers=[0x4B])
-
-add_insn("phaddubw", "sse5two", modifiers=[0x51])
-add_insn("phaddubd", "sse5two", modifiers=[0x52])
-add_insn("phaddubq", "sse5two", modifiers=[0x53])
-add_insn("phadduwd", "sse5two", modifiers=[0x56])
-add_insn("phadduwq", "sse5two", modifiers=[0x57])
-add_insn("phaddudq", "sse5two", modifiers=[0x5B])
-
-add_insn("phsubbw", "sse5two", modifiers=[0x61])
-add_insn("phsubwd", "sse5two", modifiers=[0x62])
-add_insn("phsubdq", "sse5two", modifiers=[0x63])
-
-add_group("sse5pmacs",
- cpu=["SSE5"],
- modifiers=["Op2Add"],
- opcode=[0x0F, 0x24, 0x00],
- drex_oc0=0,
- operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
- Operand(type="SIMDReg", size=128, dest="Spare"),
+add_group("amd_vpshift",
+ cpu=["XOP"],
+ modifiers=["Op1Add"],
+ xop=128,
+ xopw=0,
+ opcode=[0x09, 0x00],
+ operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
- Operand(type="SIMDRegMatch0", size=128, dest=None)])
+ Operand(type="SIMDReg", size=128, dest="VEX")])
+add_group("amd_vpshift",
+ cpu=["XOP"],
+ modifiers=["Op1Add"],
+ xop=128,
+ xopw=1,
+ opcode=[0x09, 0x00],
+ operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+ Operand(type="SIMDReg", size=128, dest="VEX"),
+ Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
+for opc, sfx in enumerate(["b", "w", "d", "q"]):
+ add_insn("vpsha"+sfx, "amd_vpshift", modifiers=[0x98+opc])
+ add_insn("vpshl"+sfx, "amd_vpshift", modifiers=[0x94+opc])
-add_insn("pmacsww", "sse5pmacs", modifiers=[0x95])
-add_insn("pmacswd", "sse5pmacs", modifiers=[0x96])
-add_insn("pmacsdql", "sse5pmacs", modifiers=[0x97])
-add_insn("pmacsdd", "sse5pmacs", modifiers=[0x9E])
-add_insn("pmacsdqh", "sse5pmacs", modifiers=[0x9F])
+#####################################################################
+# AMD FMA4 instructions (same as original Intel FMA instructions)
+#####################################################################
-add_insn("pmacssww", "sse5pmacs", modifiers=[0x85])
-add_insn("pmacsswd", "sse5pmacs", modifiers=[0x86])
-add_insn("pmacssdql", "sse5pmacs", modifiers=[0x87])
-add_insn("pmacssdd", "sse5pmacs", modifiers=[0x8E])
-add_insn("pmacssdqh", "sse5pmacs", modifiers=[0x8F])
-
-add_insn("pmadcsswd", "sse5pmacs", modifiers=[0xA6])
-add_insn("pmadcswd", "sse5pmacs", modifiers=[0xB6])
-
-add_group("sse5prot",
- cpu=["SSE5"],
+add_group("fma_128_256",
+ cpu=["FMA4"],
modifiers=["Op2Add"],
- opcode=[0x0F, 0x24, 0x40],
- drex_oc0=0,
- operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
- Operand(type="SIMDReg", size=128, dest="Spare"),
- Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
-add_group("sse5prot",
- cpu=["SSE5"],
- modifiers=["Op2Add"],
- opcode=[0x0F, 0x24, 0x40],
- drex_oc0=1,
- operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
+ vex=128,
+ vexw=0,
+ prefix=0x66,
+ opcode=[0x0F, 0x3A, 0x00],
+ operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+ Operand(type="SIMDReg", size=128, dest="VEX"),
Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
- Operand(type="SIMDReg", size=128, dest="Spare")])
-add_group("sse5prot",
- cpu=["SSE5"],
+ Operand(type="SIMDReg", size=128, dest="VEXImmSrc")])
+add_group("fma_128_256",
+ cpu=["FMA4"],
modifiers=["Op2Add"],
- opcode=[0x0F, 0x7B, 0x40],
+ vex=128,
+ vexw=1,
+ prefix=0x66,
+ opcode=[0x0F, 0x3A, 0x00],
operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
- Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
- Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
-
-add_insn("protb", "sse5prot", modifiers=[0x00])
-add_insn("protw", "sse5prot", modifiers=[0x01])
-add_insn("protd", "sse5prot", modifiers=[0x02])
-add_insn("protq", "sse5prot", modifiers=[0x03])
-
-add_group("sse5psh",
- cpu=["SSE5"],
- modifiers=["Op2Add"],
- opcode=[0x0F, 0x24, 0x44],
- drex_oc0=0,
- operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
- Operand(type="SIMDReg", size=128, dest="Spare"),
+ Operand(type="SIMDReg", size=128, dest="VEX"),
+ Operand(type="SIMDReg", size=128, dest="VEXImmSrc"),
Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
-add_group("sse5psh",
- cpu=["SSE5"],
+add_group("fma_128_256",
+ cpu=["FMA4"],
modifiers=["Op2Add"],
- opcode=[0x0F, 0x24, 0x44],
- drex_oc0=1,
- operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
- Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
- Operand(type="SIMDReg", size=128, dest="Spare")])
+ vex=256,
+ vexw=0,
+ prefix=0x66,
+ opcode=[0x0F, 0x3A, 0x00],
+ operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
+ Operand(type="SIMDReg", size=256, dest="VEX"),
+ Operand(type="SIMDRM", size=256, relaxed=True, dest="EA"),
+ Operand(type="SIMDReg", size=256, dest="VEXImmSrc")])
+add_group("fma_128_256",
+ cpu=["FMA4"],
+ modifiers=["Op2Add"],
+ vex=256,
+ vexw=1,
+ prefix=0x66,
+ opcode=[0x0F, 0x3A, 0x00],
+ operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
+ Operand(type="SIMDReg", size=256, dest="VEX"),
+ Operand(type="SIMDReg", size=256, dest="VEXImmSrc"),
+ Operand(type="SIMDRM", size=256, relaxed=True, dest="EA")])
-add_insn("pshlb", "sse5psh", modifiers=[0x00])
-add_insn("pshlw", "sse5psh", modifiers=[0x01])
-add_insn("pshld", "sse5psh", modifiers=[0x02])
-add_insn("pshlq", "sse5psh", modifiers=[0x03])
+add_insn("vfmaddpd", "fma_128_256", modifiers=[0x69])
+add_insn("vfmaddps", "fma_128_256", modifiers=[0x68])
+add_insn("vfmaddsubpd", "fma_128_256", modifiers=[0x5D])
+add_insn("vfmaddsubps", "fma_128_256", modifiers=[0x5C])
+add_insn("vfmsubaddpd", "fma_128_256", modifiers=[0x5F])
+add_insn("vfmsubaddps", "fma_128_256", modifiers=[0x5E])
+add_insn("vfmsubpd", "fma_128_256", modifiers=[0x6D])
+add_insn("vfmsubps", "fma_128_256", modifiers=[0x6C])
+add_insn("vfnmaddpd", "fma_128_256", modifiers=[0x79])
+add_insn("vfnmaddps", "fma_128_256", modifiers=[0x78])
+add_insn("vfnmsubpd", "fma_128_256", modifiers=[0x7D])
+add_insn("vfnmsubps", "fma_128_256", modifiers=[0x7C])
-add_insn("pshab", "sse5psh", modifiers=[0x04])
-add_insn("pshaw", "sse5psh", modifiers=[0x05])
-add_insn("pshad", "sse5psh", modifiers=[0x06])
-add_insn("pshaq", "sse5psh", modifiers=[0x07])
+for sz in [32, 64]:
+ add_group("fma_128_m%d" % sz,
+ cpu=["FMA4"],
+ modifiers=["Op2Add"],
+ vex=128,
+ vexw=0,
+ prefix=0x66,
+ opcode=[0x0F, 0x3A, 0x00],
+ operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+ Operand(type="SIMDReg", size=128, dest="VEX"),
+ Operand(type="SIMDReg", size=128, dest="EA"),
+ Operand(type="SIMDReg", size=128, dest="VEXImmSrc")])
+ add_group("fma_128_m%d" % sz,
+ cpu=["FMA4"],
+ modifiers=["Op2Add"],
+ vex=128,
+ vexw=0,
+ prefix=0x66,
+ opcode=[0x0F, 0x3A, 0x00],
+ operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+ Operand(type="SIMDReg", size=128, dest="VEX"),
+ Operand(type="Mem", size=sz, relaxed=True, dest="EA"),
+ Operand(type="SIMDReg", size=128, dest="VEXImmSrc")])
+ add_group("fma_128_m%d" % sz,
+ cpu=["FMA4"],
+ modifiers=["Op2Add"],
+ vex=128,
+ vexw=1,
+ prefix=0x66,
+ opcode=[0x0F, 0x3A, 0x00],
+ operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+ Operand(type="SIMDReg", size=128, dest="VEX"),
+ Operand(type="SIMDReg", size=128, dest="VEXImmSrc"),
+ Operand(type="Mem", size=sz, relaxed=True, dest="EA")])
-# roundps, roundpd, roundss, roundsd, ptest are in SSE4.1
+add_insn("vfmaddsd", "fma_128_m64", modifiers=[0x6B])
+add_insn("vfmaddss", "fma_128_m32", modifiers=[0x6A])
+add_insn("vfmsubsd", "fma_128_m64", modifiers=[0x6F])
+add_insn("vfmsubss", "fma_128_m32", modifiers=[0x6E])
+add_insn("vfnmaddsd", "fma_128_m64", modifiers=[0x7B])
+add_insn("vfnmaddss", "fma_128_m32", modifiers=[0x7A])
+add_insn("vfnmsubsd", "fma_128_m64", modifiers=[0x7F])
+add_insn("vfnmsubss", "fma_128_m32", modifiers=[0x7E])
#####################################################################
-# Intel XSAVE instructions
+# Intel XSAVE and XSAVEOPT instructions
#####################################################################
add_insn("xgetbv", "threebyte", modifiers=[0x0F, 0x01, 0xD0],
cpu=["XSAVE", "386"])
@@ -6990,6 +7283,18 @@
add_insn("xrstor", "twobytemem", modifiers=[5, 0x0F, 0xAE],
cpu=["XSAVE", "386"])
+add_insn("xsaveopt", "twobytemem", modifiers=[6, 0x0F, 0xAE],
+ cpu=["XSAVEOPT"])
+
+add_group("xsaveopt64",
+ modifiers=["SpAdd", "Op0Add", "Op1Add"],
+ opcode=[0x00, 0x00],
+ spare=0,
+ opersize=64,
+ operands=[Operand(type="Mem", relaxed=True, dest="EA")])
+add_insn("xsaveopt64", "xsaveopt64", modifiers=[6, 0x0F, 0xAE],
+ cpu=["XSAVEOPT"], only64=True)
+
#####################################################################
# Intel MOVBE instruction
#####################################################################
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