Update our yasm copy to yasm 1.1.0 (Part 1: yasm side)...

third_party/yasm/patched-yasm/modules/arch/x86/gen_x86_insn.py

 #! /usr/bin/env python
 # x86 instructions and prefixes data and code generation
 #
 #  Copyright (C) 2002-2007  Peter Johnson
 #
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions
 # are met:
 # 1. Redistributions of source code must retain the above copyright
 #    notice, this list of conditions and the following disclaimer.
 # 2. Redistributions in binary form must reproduce the above copyright
 #    notice, this list of conditions and the following disclaimer in the
 #    documentation and/or other materials provided with the distribution.
 #
 # THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND OTHER CONTRIBUTORS ``AS IS''
 # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 # ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR OTHER CONTRIBUTORS BE
 # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 # POSSIBILITY OF SUCH DAMAGE.
 #
 # NOTE: operands are arranged in NASM / Intel order (e.g. dest, src)
-rcstag = "$Id: gen_x86_insn.py 2193 2009-04-04 23:03:41Z peter $"
+
+from sys import stdout, version_info
+
+rcstag = "$Id: gen_x86_insn.py 2346 2010-08-01 01:37:37Z peter $"
 
 import os
 import sys
 
 try:
     scriptname = rcstag.split()[1]
     scriptrev = rcstag.split()[2]
 except IndexError:
     scriptname = "gen_x86_insn.py"
     scriptrev = "HEAD"
 
 ordered_cpus = [
     "086", "186", "286", "386", "486", "586", "686", "K6", "Athlon", "P3",
     "P4", "IA64", "Hammer"]
 ordered_cpu_features = [
     "FPU", "Cyrix", "AMD", "MMX", "3DNow", "SMM", "SSE", "SSE2",
     "SSE3", "SVM", "PadLock", "SSSE3", "SSE41", "SSE42", "SSE4a", "SSE5",
-    "AVX", "FMA", "AES", "CLMUL"]
+    "AVX", "FMA", "AES", "CLMUL", "MOVBE", "XOP", "FMA4", "F16C",
+    "FSGSBASE", "RDRAND", "XSAVEOPT", "EPTVPID", "SMX"]
 unordered_cpu_features = ["Priv", "Prot", "Undoc", "Obs"]
 
 # Predefined VEX prefix field values
 VEXW0 = 0xC0
 VEXW1 = 0xC8
 VEXL0 = 0xC0
 VEXL1 = 0xC4
 VEXpp = 0xC0    # OR with value
 
+# Predefined XOP prefix field values
+XOPW0 = 0x80
+XOPW1 = 0x88
+XOPL0 = 0x80
+XOPL1 = 0x84
+XOPpp = 0x80    # OR with value
+
+def lprint(s, f = stdout, e = '\n') :
+    f.write(s + e)
+
 def cpu_lcd(cpu1, cpu2):
     """Find the lowest common denominator of two CPU sets."""
     retval = set()
 
     # CPU
     cpu1cpus = set(ordered_cpus) & set(cpu1)
     if not cpu1cpus:
         cpu1cpus.add("086")
     cpu1mincpu = min(ordered_cpus.index(x) for x in cpu1cpus)
     cpu2cpus = set(ordered_cpus) & set(cpu2)
@@ skipping 36 matching lines @@
     def __init__(self, **kwargs):
         self.type = kwargs.pop("type")
         self.size = kwargs.pop("size", "Any")
         self.relaxed = kwargs.pop("relaxed", False)
         self.dest = kwargs.pop("dest", None)
         self.tmod = kwargs.pop("tmod", None)
         self.opt = kwargs.pop("opt", None)
 
         if kwargs:
             for arg in kwargs:
-                print "Warning: unrecognized arg %s" % arg
+                lprint("Warning: unrecognized arg %s" % arg)
 
     def __str__(self):
         return "{"+ ", ".join(["OPT_%s" % self.type,
                                "OPS_%s" % self.size,
                                "%d" % self.relaxed,
                                self.dest == "EA64" and "1" or "0",
                                "OPTM_%s" % self.tmod,
                                "OPA_%s" % (self.dest == "EA64"
                                            and "EA" or self.dest),
                                "OPAP_%s" % self.opt]) + "}"
@@ skipping 45 matching lines @@
 
         # Default operation size in 64-bit mode
         self.def_opersize_64 = kwargs.pop("def_opersize_64", 0)
 
         # GAS suffix
         self.gen_suffix = kwargs.pop("gen_suffix", True)
         self.suffixes = kwargs.pop("suffixes", None)
         suffix = kwargs.pop("suffix", None)
         if suffix is not None:
             self.suffixes = [suffix]
+
+        req_suffix = kwargs.pop("req_suffix", False)
+        if not req_suffix:
+            if self.suffixes is None:
+                self.suffixes = ["Z"]
+            else:
+                self.suffixes.append("Z")
+
         if self.suffixes is not None:
             self.suffixes = set(x.upper() for x in self.suffixes)
 
         # Special instruction prefix
         self.special_prefix = "0"
         if "prefix" in kwargs:
             self.special_prefix = "0x%02X" % kwargs.pop("prefix")
 
         # VEX prefix
         if "vex" in kwargs:
@@ skipping 17 matching lines @@
             elif self.special_prefix == "0xF3":
                 vexpp = 2
             elif self.special_prefix == "0xF2":
                 vexpp = 3
             else:
                 raise ValueError("Cannot combine VEX and special prefix %s"
                                  % self.special_prefix)
 
             self.special_prefix = "0x%02X" % (0xC0 + vexW*8 + vexL*4 + vexpp)
 
+        # XOP prefix
+        if "xop" in kwargs:
+            xopW = kwargs.pop("xopw", 0)
+            if xopW not in [0, 1]:
+                raise ValueError("XOP.W must be 0 or 1")
+
+            xopL = kwargs.pop("xop")
+            if xopL == 128 or xopL == 0:
+                xopL = 0
+            elif xopL == 256:
+                xopL = 1
+            else:
+                raise ValueError("XOP.L must be 128 or 256")
+
+            # XOPpp is currently reserved (0)
+            xoppp = 0
+            if self.special_prefix not in ["0", "0x00"]:
+                raise ValueError("Cannot combine XOP and special prefix %s"
+                                 % self.special_prefix)
+            self.special_prefix = "0x%02X" % (0x80 + xopW*8 + xopL*4 + xoppp)
+
         # Spare value
         self.spare = kwargs.pop("spare", 0)
 
         # Build opcodes string (C array initializer)
         if "opcode" in kwargs:
             # Usual case, just a single opcode
             self.opcode = kwargs.pop("opcode")
             self.opcode_len = len(self.opcode)
         elif "opcode1" in kwargs and "opcode2" in kwargs:
             # Two opcode case; the first opcode is the "optimized" opcode,
             # the second is the "relaxed" opcode.  For this to work, an
             # opt="foo" must be set for one of the operands.
             self.opcode1 = kwargs.pop("opcode1")
             self.opcode2 = kwargs.pop("opcode2")
             self.opcode_len = len(self.opcode1)
         else:
             raise KeyError("missing opcode")
 
-        # DREX opcode0 field
-        self.drex_oc0 = kwargs.pop("drex_oc0", 0) and 0x08 or 0
-
         # Build operands string (C array initializer)
         self.operands = kwargs.pop("operands")
         for op in self.operands:
             if op.type in ["Reg", "RM", "Areg", "Creg", "Dreg"]:
                 if op.size == 64:
                     self.misc_flags.add("ONLY_64")
                 elif op.size == 32 and "ONLY_64" not in self.misc_flags:
                     self.cpu.add("386")
             if op.type in ["Imm", "ImmNotSegOff"]:
                 if op.size == 64:
                     self.misc_flags.add("ONLY_64")
                 elif op.size == 32 and "ONLY_64" not in self.misc_flags:
                     self.cpu.add("386")
             if op.type in ["FS", "GS"] and "ONLY_64" not in self.misc_flags:
                 self.cpu.add("386")
             if op.type in ["CR4"] and "ONLY_64" not in self.misc_flags:
                 self.cpu.add("586")
             if op.dest == "EA64":
                 self.misc_flags.add("ONLY_64")
-            if op.dest == "DREX":
-                self.drex_oc0 |= 0x80
 
         # Modifiers
         self.modifiers = kwargs.pop("modifiers", [])
 
         # GAS flags
         self.gas_only = ("nasm" not in self.parsers)
         self.gas_illegal = ("gas" not in self.parsers)
         self.gas_no_rev = (kwargs.pop("gas_no_reverse", False) or
                            kwargs.pop("gas_no_rev", False))
 
         # CPU feature flags finalization
         # Remove redundancies
         maxcpu = -1
         maxcpu_set = self.cpu & set(ordered_cpus)
         if maxcpu_set:
             maxcpu = max(ordered_cpus.index(x) for x in maxcpu_set)
         if maxcpu != -1:
             for cpu in ordered_cpus[0:maxcpu]:
                 self.cpu.discard(cpu)
 
         if kwargs:
             for arg in kwargs:
-                print "Warning: unrecognized arg %s" % arg
+                lprint("Warning: unrecognized arg %s" % arg)
 
     def __str__(self):
         if hasattr(self, "opcode"):
             opcodes_str = ["0x%02X" % x for x in self.opcode]
         elif hasattr(self, "opcode1") and hasattr(self, "opcode2"):
             opcodes_str = ["0x%02X" % x for x in self.opcode1]
             opcodes_str.extend("0x%02X" % x for x in self.opcode2)
         # Ensure opcodes initializer string is 3 long
         opcodes_str.extend(["0", "0", "0"])
         opcodes_str = "{" + ', '.join(opcodes_str[0:3]) + "}"
@@ skipping 34 matching lines @@
         # Build instruction info structure initializer
         return "{ "+ ", ".join([gas_flags or "0",
                                 "|".join(self.misc_flags) or "0",
                                 cpus_str[0],
                                 cpus_str[1],
                                 cpus_str[2],
                                 mod_str,
                                 "%d" % (self.opersize or 0),
                                 "%d" % (self.def_opersize_64 or 0),
                                 self.special_prefix or "0",
-                                self.drex_oc0 and
-                                    ("0x%02X" % self.drex_oc0) or "0",
                                 "%d" % self.opcode_len,
                                 opcodes_str,
                                 "%d" % (self.spare or 0),
                                 "%d" % len(self.operands),
                                 "%d" % self.all_operands_index]) + " }"
 
 groups = {}
 groupnames_ordered = []
 def add_group(name, **kwargs):
     forms = groups.setdefault(name, [])
@@ skipping 82 matching lines @@
     def copy(self):
         """Return a shallow copy."""
         return Insn(self.groupname,
                     suffix=self.suffix,
                     modifiers=self.modifiers,
                     cpu=self.cpu,
                     misc_flags=self.misc_flags)
 
     def __str__(self):
         if self.suffix is None:
-            suffix_str = "NONE"
+            suffix_str = "SUF_Z"
         elif len(self.suffix) == 1:
             suffix_str = "SUF_" + self.suffix
         else:
             suffix_str = self.suffix
 
         cpus_str = []
         if self.cpu is not None:
             if len(self.cpu) > 3:
                 raise ValueError("too many CPUs: %s" % (self.cpu,))
             cpus_str.extend("CPU_%s" % x for x in sorted(self.cpu))
@@ skipping 47 matching lines @@
 
 def add_prefix(name, groupname, value, parser=None, **kwargs):
     prefix = Prefix(groupname, value, **kwargs)
     if parser is None or parser == "gas":
         gas_insns[name] = prefix
     if parser is None or parser == "nasm":
         nasm_insns[name] = prefix
 
 def finalize_insns():
     unused_groups = set(groups.keys())
-    for name, opts in insns.iteritems():
-        for insn in opts:
+    for name in insns:
+        for insn in insns[name]:
             group = groups[insn.groupname]
             unused_groups.discard(insn.groupname)
 
             parsers = set()
             for form in group:
                 parsers |= form.parsers
             if insn.parsers is not None:
                 parsers &= insn.parsers
 
             if "gas" in parsers:
-                keyword = name
-                if keyword in gas_insns:
-                    raise ValueError("duplicate gas instruction %s" % keyword)
-                newinsn = insn.copy()
-                newinsn.auto_cpu("gas")
-                newinsn.auto_misc_flags("gas")
-                gas_insns[keyword] = newinsn
-
+                suffixes = set()
                 if insn.suffix is None:
-                    suffixes = set()
                     for form in group:
                         if form.gen_suffix and form.suffixes is not None:
                             suffixes |= form.suffixes
 
-                    for suffix in suffixes:
+                if not suffixes:
+                    suffixes.add("Z")
+                for suffix in suffixes:
+                    if suffix == "Z":
+                        keyword = name
+                    else:
                         keyword = name+suffix
-                        if keyword in gas_insns:
-                            raise ValueError("duplicate gas instruction %s" %
-                                             keyword)
-                        newinsn = insn.copy()
-                        newinsn.suffix = suffix
-                        newinsn.auto_cpu("gas")
-                        newinsn.auto_misc_flags("gas")
-                        gas_insns[keyword] = newinsn
+                    if keyword in gas_insns:
+                        raise ValueError("duplicate gas instruction %s" %
+                                         keyword)
+                    newinsn = insn.copy()
+                    newinsn.suffix = suffix
+                    newinsn.auto_cpu("gas")
+                    newinsn.auto_misc_flags("gas")
+                    gas_insns[keyword] = newinsn
 
             if "nasm" in parsers:
                 keyword = name
                 if keyword in nasm_insns:
                     raise ValueError("duplicate nasm instruction %s" % keyword)
                 newinsn = insn.copy()
                 newinsn.auto_cpu("nasm")
                 newinsn.auto_misc_flags("nasm")
                 nasm_insns[keyword] = newinsn
 
     unused_groups.discard("empty")
     unused_groups.discard("not64")
     if unused_groups:
-        print "warning: unused groups: %s" % ", ".join(unused_groups)
+        lprint("warning: unused groups: %s" % ", ".join(unused_groups))
 
 def output_insns(f, parser, insns):
-    print >>f, "/* Generated by %s r%s, do not edit */" % \
-        (scriptname, scriptrev)
-    print >>f, """%%ignore-case
+    lprint("/* Generated by %s r%s, do not edit */" % \
+        (scriptname, scriptrev), f)
+    lprint("""%%ignore-case
 %%language=ANSI-C
 %%compare-strncmp
 %%readonly-tables
 %%enum
 %%struct-type
 %%define hash-function-name insnprefix_%s_hash
 %%define lookup-function-name insnprefix_%s_find
 struct insnprefix_parse_data;
-%%%%""" % (parser, parser)
+%%%%""" % (parser, parser), f)
     for keyword in sorted(insns):
-        print >>f, "%s,\t%s" % (keyword.lower(), insns[keyword])
+        lprint("%s,\t%s" % (keyword.lower(), insns[keyword]), f)
 
 def output_gas_insns(f):
     output_insns(f, "gas", gas_insns)
 
 def output_nasm_insns(f):
     output_insns(f, "nasm", nasm_insns)
 
 def output_groups(f):
     # Merge all operand lists into single list
     # Sort by number of operands to shorten output
     all_operands = []
-    for form in sorted((form for g in groups.itervalues() for form in g),
+    if version_info[0] == 2:
+        gi = groups.itervalues()
+    else:
+        gi = groups.values()
+    for form in sorted((form for g in gi for form in g),
                        key=lambda x:len(x.operands), reverse=True):
         num_operands = len(form.operands)
-        for i in xrange(len(all_operands)):
+        for i in range(len(all_operands)):
             if all_operands[i:i+num_operands] == form.operands:
                 form.all_operands_index = i
                 break
         else:
             form.all_operands_index = len(all_operands)
             all_operands.extend(form.operands)
 
     # Output operands list
-    print >>f, "/* Generated by %s r%s, do not edit */" % \
-        (scriptname, scriptrev)
-    print >>f, "static const x86_info_operand insn_operands[] = {"
-    print >>f, "   ",
-    print >>f, ",\n    ".join(str(x) for x in all_operands)
-    print >>f, "};\n"
+    lprint("/* Generated by %s r%s, do not edit */" % \
+        (scriptname, scriptrev), f)
+    lprint("static const x86_info_operand insn_operands[] = {", f)
+    lprint("   ", f, '')
+    lprint(",\n    ".join(str(x) for x in all_operands), f)
+    lprint("};\n", f)
 
     # Output groups
     seen = set()
     for name in groupnames_ordered:
         if name in seen:
             continue
         seen.add(name)
-        print >>f, "static const x86_insn_info %s_insn[] = {" % name
-        print >>f, "   ",
-        print >>f, ",\n    ".join(str(x) for x in groups[name])
-        print >>f, "};\n"
+        lprint("static const x86_insn_info %s_insn[] = {" % name, f)
+        lprint("   ", f, '')
+        lprint(",\n    ".join(str(x) for x in groups[name]), f)
+        lprint("};\n", f)
 
 #####################################################################
 # General instruction groupings
 #####################################################################
 
 #
 # Empty instruction
 #
 add_group("empty", opcode=[], operands=[])
 
@@ skipping 1560 matching lines @@
 #####################################################################
 # Control transfer instructions (unconditional)
 #####################################################################
 #
 # call
 #
 add_group("call",
     opcode=[],
     operands=[Operand(type="ImmNotSegOff", dest="JmpRel")])
 add_group("call",
+    suffix="w",
     opersize=16,
     opcode=[],
     operands=[Operand(type="ImmNotSegOff", size=16, dest="JmpRel")])
 add_group("call",
+    suffix="l",
     not64=True,
     opersize=32,
     opcode=[],
     operands=[Operand(type="ImmNotSegOff", size=32, dest="JmpRel")])
 add_group("call",
+    suffixes=["l", "q"],
     only64=True,
     opersize=64,
     opcode=[],
     operands=[Operand(type="ImmNotSegOff", size=32, dest="JmpRel")])
 
 add_group("call",
     opersize=16,
     def_opersize_64=64,
     opcode=[0xE8],
     operands=[Operand(type="Imm", size=16, tmod="Near", dest="JmpRel")])
 add_group("call",
     not64=True,
     opersize=32,
     opcode=[0xE8],
     operands=[Operand(type="Imm", size=32, tmod="Near", dest="JmpRel")])
 add_group("call",
     only64=True,
     opersize=64,
     def_opersize_64=64,
     opcode=[0xE8],
     operands=[Operand(type="Imm", size=32, tmod="Near", dest="JmpRel")])
 add_group("call",
     def_opersize_64=64,
     opcode=[0xE8],
     operands=[Operand(type="Imm", tmod="Near", dest="JmpRel")])
 
 add_group("call",
+    suffix="w",
+    req_suffix=True,
     opersize=16,
     opcode=[0xFF],
     spare=2,
     operands=[Operand(type="RM", size=16, dest="EA")])
 add_group("call",
+    suffix="l",
+    req_suffix=True,
     not64=True,
     opersize=32,
     opcode=[0xFF],
     spare=2,
     operands=[Operand(type="RM", size=32, dest="EA")])
 add_group("call",
+    suffix="q",
+    req_suffix=True,
     opersize=64,
     def_opersize_64=64,
     opcode=[0xFF],
     spare=2,
     operands=[Operand(type="RM", size=64, dest="EA")])
 add_group("call",
+    parsers=["gas"],
+    def_opersize_64=64,
+    opcode=[0xFF],
+    spare=2,
+    operands=[Operand(type="Reg", size="BITS", dest="EA")])
+add_group("call",
     def_opersize_64=64,
     opcode=[0xFF],
     spare=2,
     operands=[Operand(type="Mem", dest="EA")])
 add_group("call",
+    parsers=["nasm"],
     opersize=16,
     def_opersize_64=64,
     opcode=[0xFF],
     spare=2,
     operands=[Operand(type="RM", size=16, tmod="Near", dest="EA")])
 add_group("call",
+    parsers=["nasm"],
     not64=True,
     opersize=32,
     opcode=[0xFF],
     spare=2,
     operands=[Operand(type="RM", size=32, tmod="Near", dest="EA")])
 add_group("call",
+    parsers=["nasm"],
     opersize=64,
     def_opersize_64=64,
     opcode=[0xFF],
     spare=2,
     operands=[Operand(type="RM", size=64, tmod="Near", dest="EA")])
 add_group("call",
+    parsers=["nasm"],
     def_opersize_64=64,
     opcode=[0xFF],
     spare=2,
     operands=[Operand(type="Mem", tmod="Near", dest="EA")])
 
-# Far indirect (through memory).  Needs explicit FAR override.
+# Far indirect (through memory).  Needs explicit FAR override (NASM only)
 for sz in [16, 32, 64]:
     add_group("call",
+        parsers=["nasm"],
         opersize=sz,
         opcode=[0xFF],
         spare=3,
         operands=[Operand(type="Mem", size=sz, tmod="Far", dest="EA")])
 add_group("call",
+    parsers=["nasm"],
     opcode=[0xFF],
     spare=3,
     operands=[Operand(type="Mem", tmod="Far", dest="EA")])
 
 # With explicit FAR override
 for sz in [16, 32]:
     add_group("call",
+        parsers=["nasm"],
         not64=True,
         opersize=sz,
         opcode=[0x9A],
-        spare=3,
         operands=[Operand(type="Imm", size=sz, tmod="Far", dest="JmpFar")])
 add_group("call",
+    parsers=["nasm"],
     not64=True,
     opcode=[0x9A],
-    spare=3,
     operands=[Operand(type="Imm", tmod="Far", dest="JmpFar")])
 
-# Since not caught by first ImmNotSegOff group, implicitly FAR.
+# Since not caught by first ImmNotSegOff group, implicitly FAR (in NASM).
 for sz in [16, 32]:
     add_group("call",
+        parsers=["nasm"],
         not64=True,
         opersize=sz,
         opcode=[0x9A],
-        spare=3,
         operands=[Operand(type="Imm", size=sz, dest="JmpFar")])
 add_group("call",
+    parsers=["nasm"],
     not64=True,
     opcode=[0x9A],
-    spare=3,
     operands=[Operand(type="Imm", dest="JmpFar")])
 
+# Two-operand FAR (GAS only)
+for sfx, sz in zip("wl", [16, 32]):
+    add_group("call",
+        suffix=sfx,
+        req_suffix=True,
+        parsers=["gas"],
+        not64=True,
+        gas_no_reverse=True,
+        opersize=sz,
+        opcode=[0x9A],
+        operands=[Operand(type="Imm", size=16, relaxed=True, dest="JmpFar"),
+                  Operand(type="Imm", size=sz, relaxed=True, dest="JmpFar")])
+add_group("call",
+    parsers=["gas"],
+    not64=True,
+    gas_no_reverse=True,
+    opcode=[0x9A],
+    operands=[Operand(type="Imm", size=16, relaxed=True, dest="JmpFar"),
+              Operand(type="Imm", size="BITS", relaxed=True, dest="JmpFar")])
+
 add_insn("call", "call")
-add_insn("calll", "call", parser="gas", not64=True)
-add_insn("callq", "call", parser="gas", only64=True)
 
 #
 # jmp
 #
 add_group("jmp",
     opcode=[],
     operands=[Operand(type="ImmNotSegOff", dest="JmpRel")])
 add_group("jmp",
+    suffix="w",
     opersize=16,
     opcode=[],
     operands=[Operand(type="ImmNotSegOff", size=16, dest="JmpRel")])
 add_group("jmp",
+    suffix="l",
     not64=True,
     opersize=32,
     opcode=[0x00],
     operands=[Operand(type="ImmNotSegOff", size=32, dest="JmpRel")])
 add_group("jmp",
+    suffixes=["l", "q"],
     only64=True,
     opersize=64,
     opcode=[0x00],
     operands=[Operand(type="ImmNotSegOff", size=32, dest="JmpRel")])
 
 add_group("jmp",
     def_opersize_64=64,
     opcode=[0xEB],
     operands=[Operand(type="Imm", tmod="Short", dest="JmpRel")])
 add_group("jmp",
@@ skipping 12 matching lines @@
     opersize=64,
     def_opersize_64=64,
     opcode=[0xE9],
     operands=[Operand(type="Imm", size=32, tmod="Near", dest="JmpRel")])
 add_group("jmp",
     def_opersize_64=64,
     opcode=[0xE9],
     operands=[Operand(type="Imm", tmod="Near", dest="JmpRel")])
 
 add_group("jmp",
+    suffix="w",
+    req_suffix=True,
     opersize=16,
     def_opersize_64=64,
     opcode=[0xFF],
     spare=4,
     operands=[Operand(type="RM", size=16, dest="EA")])
 add_group("jmp",
+    suffix="l",
+    req_suffix=True,
     not64=True,
     opersize=32,
     opcode=[0xFF],
     spare=4,
     operands=[Operand(type="RM", size=32, dest="EA")])
 add_group("jmp",
+    suffix="q",
+    req_suffix=True,
     opersize=64,
     def_opersize_64=64,
     opcode=[0xFF],
     spare=4,
     operands=[Operand(type="RM", size=64, dest="EA")])
 add_group("jmp",
+    parsers=["gas"],
+    def_opersize_64=64,
+    opcode=[0xFF],
+    spare=4,
+    operands=[Operand(type="Reg", size="BITS", dest="EA")])
+add_group("jmp",
     def_opersize_64=64,
     opcode=[0xFF],
     spare=4,
     operands=[Operand(type="Mem", dest="EA")])
 add_group("jmp",
+    parsers=["nasm"],
     opersize=16,
     def_opersize_64=64,
     opcode=[0xFF],
     spare=4,
     operands=[Operand(type="RM", size=16, tmod="Near", dest="EA")])
 add_group("jmp",
+    parsers=["nasm"],
     not64=True,
     cpu=["386"],
     opersize=32,
     opcode=[0xFF],
     spare=4,
     operands=[Operand(type="RM", size=32, tmod="Near", dest="EA")])
 add_group("jmp",
+    parsers=["nasm"],
     opersize=64,
     def_opersize_64=64,
     opcode=[0xFF],
     spare=4,
     operands=[Operand(type="RM", size=64, tmod="Near", dest="EA")])
 add_group("jmp",
+    parsers=["nasm"],
     def_opersize_64=64,
     opcode=[0xFF],
     spare=4,
     operands=[Operand(type="Mem", tmod="Near", dest="EA")])
 
 # Far indirect (through memory).  Needs explicit FAR override.
 for sz in [16, 32, 64]:
     add_group("jmp",
         opersize=sz,
         opcode=[0xFF],
         spare=5,
         operands=[Operand(type="Mem", size=sz, tmod="Far", dest="EA")])
 add_group("jmp",
     opcode=[0xFF],
     spare=5,
     operands=[Operand(type="Mem", tmod="Far", dest="EA")])
 
 # With explicit FAR override
 for sz in [16, 32]:
     add_group("jmp",
         not64=True,
         opersize=sz,
         opcode=[0xEA],
-        spare=3,
         operands=[Operand(type="Imm", size=sz, tmod="Far", dest="JmpFar")])
 add_group("jmp",
     not64=True,
     opcode=[0xEA],
-    spare=3,
     operands=[Operand(type="Imm", tmod="Far", dest="JmpFar")])
 
-# Since not caught by first ImmNotSegOff group, implicitly FAR.
+# Since not caught by first ImmNotSegOff group, implicitly FAR (in NASM).
 for sz in [16, 32]:
     add_group("jmp",
+        parsers=["nasm"],
         not64=True,
         opersize=sz,
         opcode=[0xEA],
-        spare=3,
         operands=[Operand(type="Imm", size=sz, dest="JmpFar")])
 add_group("jmp",
+    parsers=["nasm"],
     not64=True,
     opcode=[0xEA],
-    spare=3,
     operands=[Operand(type="Imm", dest="JmpFar")])
 
+# Two-operand FAR (GAS only)
+for sfx, sz in zip("wl", [16, 32]):
+    add_group("jmp",
+        parsers=["gas"],
+        suffix=sfx,
+        req_suffix=True,
+        not64=True,
+        gas_no_reverse=True,
+        opersize=sz,
+        opcode=[0xEA],
+        operands=[Operand(type="Imm", size=16, relaxed=True, dest="JmpFar"),
+                  Operand(type="Imm", size=sz, relaxed=True, dest="JmpFar")])
+add_group("jmp",
+    parsers=["gas"],
+    not64=True,
+    gas_no_reverse=True,
+    opcode=[0xEA],
+    operands=[Operand(type="Imm", size=16, relaxed=True, dest="JmpFar"),
+              Operand(type="Imm", size="BITS", relaxed=True, dest="JmpFar")])
+
 add_insn("jmp", "jmp")
 
 #
+# GAS far calls/jumps
+#
+
+# Far indirect (through memory)
+for sfx, sz in zip("wlq", [16, 32, 64]):
+    add_group("ljmpcall",
+        suffix=sfx,
+        req_suffix=True,
+        opersize=sz,
+        modifiers=["SpAdd"],
+        opcode=[0xFF],
+        spare=0,
+        operands=[Operand(type="Mem", size=sz, relaxed=True, dest="EA")])
+add_group("ljmpcall",
+    modifiers=["SpAdd"],
+    opcode=[0xFF],
+    spare=0,
+    operands=[Operand(type="Mem", size="BITS", relaxed=True, dest="EA")])
+
+# Two-operand far
+for sfx, sz in zip("wl", [16, 32]):
+    add_group("ljmpcall",
+        not64=True,
+        gas_no_reverse=True,
+        suffix=sfx,
+        req_suffix=True,
+        opersize=sz,
+        modifiers=["Gap", "Op0Add"],
+        opcode=[0x00],
+        operands=[Operand(type="Imm", size=16, relaxed=True, dest="JmpFar"),
+                  Operand(type="Imm", size=sz, relaxed=True, dest="JmpFar")])
+add_group("ljmpcall",
+    not64=True,
+    gas_no_reverse=True,
+    modifiers=["Gap", "Op0Add"],
+    opcode=[0x00],
+    operands=[Operand(type="Imm", size=16, relaxed=True, dest="JmpFar"),
+              Operand(type="Imm", size="BITS", relaxed=True, dest="JmpFar")])
+
+add_insn("ljmp", "ljmpcall", parser="gas", modifiers=[5, 0xEA])
+add_insn("lcall", "ljmpcall", parser="gas", modifiers=[3, 0x9A])
+
+#
 # ret
 #
 add_group("retnf",
     not64=True,
     modifiers=["Op0Add"],
     opcode=[0x01],
     operands=[])
 add_group("retnf",
     not64=True,
     modifiers=["Op0Add"],
@@ skipping 22 matching lines @@
     modifiers=["Op0Add", "OpSizeR"],
     opcode=[0x00],
     operands=[Operand(type="Imm", size=16, relaxed=True, dest="Imm")])
 
 add_insn("ret", "retnf", modifiers=[0xC2])
 add_insn("retw", "retnf", parser="gas", modifiers=[0xC2, 16])
 add_insn("retl", "retnf", parser="gas", modifiers=[0xC2], not64=True)
 add_insn("retq", "retnf", parser="gas", modifiers=[0xC2], only64=True)
 add_insn("retn", "retnf", parser="nasm", modifiers=[0xC2])
 add_insn("retf", "retnf", parser="nasm", modifiers=[0xCA, 64])
-add_insn("lretw", "retnf", parser="gas", modifiers=[0xCA, 16], suffix="NONE")
-add_insn("lretl", "retnf", parser="gas", modifiers=[0xCA], suffix="NONE")
+add_insn("lret", "retnf", parser="gas", modifiers=[0xCA], suffix="z")
+add_insn("lretw", "retnf", parser="gas", modifiers=[0xCA, 16], suffix="w")
+add_insn("lretl", "retnf", parser="gas", modifiers=[0xCA], suffix="l")
 add_insn("lretq", "retnf", parser="gas", modifiers=[0xCA, 64], only64=True,
-         suffix="NONE")
+         suffix="q")
 
 #
 # enter
 #
 add_group("enter",
     suffix="l",
     not64=True,
     cpu=["186"],
     gas_no_reverse=True,
     opcode=[0xC8],
@@ skipping 172 matching lines @@
         opcode=[0xE0],
         operands=[Operand(type="Imm", tmod="Short", dest="JmpRel"),
                   Operand(type="Creg", size=sz, dest="AdSizeR")])
 
 add_insn("loop", "loop", modifiers=[2])
 add_insn("loopz", "loop", modifiers=[1])
 add_insn("loope", "loop", modifiers=[1])
 add_insn("loopnz", "loop", modifiers=[0])
 add_insn("loopne", "loop", modifiers=[0])
 
+# GAS w/l/q suffixes have to set addrsize via modifiers
+for sfx, sz in zip("wlq", [16, 32, 64]):
+    add_group("loop"+sfx,
+        not64=(sz == 16),
+        only64=(sz == 64),
+        modifiers=["Gap", "AdSizeR"],
+        def_opersize_64=64,
+        opcode=[],
+        operands=[Operand(type="Imm", dest="JmpRel")])
+    add_group("loop"+sfx,
+        not64=(sz == 16),
+        only64=(sz == 64),
+        modifiers=["Op0Add", "AdSizeR"],
+        def_opersize_64=64,
+        opcode=[0xE0],
+        operands=[Operand(type="Imm", tmod="Short", dest="JmpRel")])
+
+    add_group("loop"+sfx,
+        not64=(sz == 16),
+        only64=(sz == 64),
+        def_opersize_64=64,
+        opcode=[],
+        operands=[Operand(type="Imm", dest="JmpRel"),
+                  Operand(type="Creg", size=sz, dest="AdSizeR")])
+    add_group("loop"+sfx,
+        not64=(sz == 16),
+        only64=(sz == 64),
+        modifiers=["Op0Add"],
+        def_opersize_64=64,
+        opcode=[0xE0],
+        operands=[Operand(type="Imm", tmod="Short", dest="JmpRel"),
+                  Operand(type="Creg", size=sz, dest="AdSizeR")])
+
+    add_insn("loop"+sfx, "loop"+sfx, parser="gas", modifiers=[2, sz])
+    add_insn("loopz"+sfx, "loop"+sfx, parser="gas", modifiers=[1, sz])
+    add_insn("loope"+sfx, "loop"+sfx, parser="gas", modifiers=[1, sz])
+    add_insn("loopnz"+sfx, "loop"+sfx, parser="gas", modifiers=[0, sz])
+    add_insn("loopne"+sfx, "loop"+sfx, parser="gas", modifiers=[0, sz])
+
 #####################################################################
 # Set byte on flag instructions
 #####################################################################
 add_group("setcc",
     suffix="b",
     cpu=["386"],
     modifiers=["Op1Add"],
     opcode=[0x0F, 0x90],
     spare=2,
     operands=[Operand(type="RM", size=8, relaxed=True, dest="EA")])
@@ skipping 364 matching lines @@
 add_insn("fstp", "fstp")
 
 #
 # Long memory version of floating point load/store for GAS
 #
 add_group("fldstpt",
     cpu=["FPU"],
     modifiers=["SpAdd"],
     opcode=[0xDB],
     spare=0,
-    operands=[Operand(type="Mem", size=80, dest="EA")])
+    operands=[Operand(type="Mem", size=80, relaxed=True, dest="EA")])
 
-add_insn("fldt", "fldstpt", suffix="WEAK", modifiers=[5])
-add_insn("fstpt", "fldstpt", suffix="WEAK", modifiers=[7])
+add_insn("fldt", "fldstpt", modifiers=[5])
+add_insn("fstpt", "fldstpt", modifiers=[7])
 
 add_group("fildstp",
     suffix="s",
     cpu=["FPU"],
     modifiers=["SpAdd"],
     opcode=[0xDF],
     spare=0,
     operands=[Operand(type="Mem", size=16, dest="EA")])
 add_group("fildstp",
     suffix="l",
@@ skipping 1562 matching lines @@
     cpu=["MMX", "P3"],
     notavx=True,
     opcode=[0x0F, 0xC4],
     operands=[Operand(type="SIMDReg", size=64, dest="Spare"),
               Operand(type="Reg", size=32, dest="EA"),
               Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
 add_group("pinsrw",
     suffix="q",
     cpu=["MMX", "P3"],
     notavx=True,
+    def_opersize_64=64,
     opersize=64,
     opcode=[0x0F, 0xC4],
     operands=[Operand(type="SIMDReg", size=64, dest="Spare"),
               Operand(type="Reg", size=64, dest="EA"),
               Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
 add_group("pinsrw",
     suffix="l",
     cpu=["MMX", "P3"],
     notavx=True,
     opcode=[0x0F, 0xC4],
     operands=[Operand(type="SIMDReg", size=64, dest="Spare"),
               Operand(type="Mem", size=16, relaxed=True, dest="EA"),
               Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
 add_group("pinsrw",
     suffix="l",
     cpu=["SSE2"],
     modifiers=["SetVEX"],
     prefix=0x66,
     opcode=[0x0F, 0xC4],
     operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"),
               Operand(type="Reg", size=32, dest="EA"),
               Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
 add_group("pinsrw",
     suffix="q",
     cpu=["SSE2"],
     modifiers=["SetVEX"],
+    def_opersize_64=64,
     opersize=64,
     prefix=0x66,
     opcode=[0x0F, 0xC4],
     operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"),
               Operand(type="Reg", size=64, dest="EA"),
               Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
 add_group("pinsrw",
     suffix="l",
     cpu=["SSE2"],
     modifiers=["SetVEX"],
     prefix=0x66,
     opcode=[0x0F, 0xC4],
     operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"),
               Operand(type="Mem", size=16, relaxed=True, dest="EA"),
               Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
 add_group("pinsrw",
     suffix="l",
     cpu=["AVX"],
     vex=128,
     prefix=0x66,
     opcode=[0x0F, 0xC4],
     operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
               Operand(type="SIMDReg", size=128, dest="VEX"),
               Operand(type="Reg", size=32, dest="EA"),
               Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
 add_group("pinsrw",
     suffix="q",
     cpu=["AVX"],
     vex=128,
+    def_opersize_64=64,
     opersize=64,
     prefix=0x66,
     opcode=[0x0F, 0xC4],
     operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
               Operand(type="SIMDReg", size=128, dest="VEX"),
               Operand(type="Reg", size=64, dest="EA"),
               Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
 add_group("pinsrw",
     suffix="l",
     cpu=["AVX"],
@@ skipping 342 matching lines @@
     operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
               Operand(type="SIMDReg", size=128, dest="VEX"),
               Operand(type="SIMDReg", size=128, dest="EA")])
 # movsd is added in string instructions above, so don't re-add_insn()
 add_insn("vmovsd", "movsd", modifiers=[VEXL0], avx=True)
 
 #####################################################################
 # P4 VMX Instructions
 #####################################################################
 
+add_group("eptvpid",
+    modifiers=["Op2Add"],
+    suffix="l",
+    not64=True,
+    cpu=["EPTVPID"],
+    opersize=32,
+    prefix=0x66,
+    opcode=[0x0F, 0x38, 0x80],
+    operands=[Operand(type="Reg", size=32, dest="Spare"),
+              Operand(type="Mem", size=128, relaxed=True, dest="EA")])
+add_group("eptvpid",
+    modifiers=["Op2Add"],
+    suffix="q",
+    cpu=["EPTVPID"],
+    opersize=64,
+    prefix=0x66,
+    opcode=[0x0F, 0x38, 0x80],
+    operands=[Operand(type="Reg", size=64, dest="Spare"),
+              Operand(type="Mem", size=128, relaxed=True, dest="EA")])
+add_insn("invept", "eptvpid", modifiers=[0])
+add_insn("invvpid", "eptvpid", modifiers=[1])
+
 add_insn("vmcall", "threebyte", modifiers=[0x0F, 0x01, 0xC1], cpu=["P4"])
 add_insn("vmlaunch", "threebyte", modifiers=[0x0F, 0x01, 0xC2], cpu=["P4"])
 add_insn("vmresume", "threebyte", modifiers=[0x0F, 0x01, 0xC3], cpu=["P4"])
 add_insn("vmxoff", "threebyte", modifiers=[0x0F, 0x01, 0xC4], cpu=["P4"])
 
 add_group("vmxmemrd",
     suffix="l",
     not64=True,
     cpu=["P4"],
     opersize=32,
@@ skipping 40 matching lines @@
 add_group("vmxthreebytemem",
     modifiers=["PreAdd"],
     cpu=["P4"],
     prefix=0x00,
     opcode=[0x0F, 0xC7],
     spare=6,
     operands=[Operand(type="Mem", size=64, relaxed=True, dest="EA")])
 add_insn("vmclear", "vmxthreebytemem", modifiers=[0x66])
 add_insn("vmxon", "vmxthreebytemem", modifiers=[0xF3])
 
+#####################################################################
+# Intel SMX Instructions
+#####################################################################
+add_insn("getsec", "twobyte", modifiers=[0x0F, 0x37], cpu=["SMX"])
+
 add_insn("cvttpd2pi", "cvt_mm_xmm", modifiers=[0x66, 0x2C], cpu=["SSE2"])
 add_insn("cvttsd2si", "cvt_rx_xmm64", modifiers=[0xF2, 0x2C], cpu=["SSE2"])
 add_insn("cvttpd2dq", "xmm_xmm128", modifiers=[0x66, 0xE6], cpu=["SSE2"])
 add_insn("cvttps2dq", "xmm_xmm128", modifiers=[0xF3, 0x5B], cpu=["SSE2"])
 add_insn("pmuludq", "mmxsse2", modifiers=[0xF4], cpu=["SSE2"])
 add_insn("pshufd", "xmm_xmm128_imm", modifiers=[0x66, 0x70], cpu=["SSE2"])
 add_insn("pshufhw", "xmm_xmm128_imm", modifiers=[0xF3, 0x70], cpu=["SSE2"])
 add_insn("pshuflw", "xmm_xmm128_imm", modifiers=[0xF2, 0x70], cpu=["SSE2"])
 add_insn("punpckhqdq", "xmm_xmm128", modifiers=[0x66, 0x6D], cpu=["SSE2"])
 add_insn("punpcklqdq", "xmm_xmm128", modifiers=[0x66, 0x6C], cpu=["SSE2"])
@@ skipping 427 matching lines @@
         prefix=0xF2,
         opcode=[0x0F, 0x38, 0xF0+(sz!=8)],
         operands=[Operand(type="Reg", size=64, dest="Spare"),
                   Operand(type="RM", size=sz, relaxed=(sz==64), dest="EA")])
 
 add_insn("crc32", "crc32")
 
 add_group("extractps",
     cpu=["SSE41"],
     modifiers=["SetVEX"],
-    opersize=32,
     prefix=0x66,
     opcode=[0x0F, 0x3A, 0x17],
     operands=[Operand(type="RM", size=32, relaxed=True, dest="EA"),
               Operand(type="SIMDReg", size=128, dest="Spare"),
               Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
 add_group("extractps",
     cpu=["SSE41"],
     modifiers=["SetVEX"],
     opersize=64,
     prefix=0x66,
@@ skipping 74 matching lines @@
 add_insn("vpcmpistrm", "sse4pcmpstr", modifiers=[0x62, VEXL0], avx=True)
 
 add_group("pextrb",
     cpu=["SSE41"],
     modifiers=["SetVEX"],
     prefix=0x66,
     opcode=[0x0F, 0x3A, 0x14],
     operands=[Operand(type="Mem", size=8, relaxed=True, dest="EA"),
               Operand(type="SIMDReg", size=128, dest="Spare"),
               Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
-for sz in [32, 64]:
-    add_group("pextrb",
-        cpu=["SSE41"],
-        modifiers=["SetVEX"],
-        opersize=sz,
-        prefix=0x66,
-        opcode=[0x0F, 0x3A, 0x14],
-        operands=[Operand(type="Reg", size=sz, dest="EA"),
-                  Operand(type="SIMDReg", size=128, dest="Spare"),
-                  Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
+add_group("pextrb",
+    cpu=["SSE41"],
+    modifiers=["SetVEX"],
+    prefix=0x66,
+    opcode=[0x0F, 0x3A, 0x14],
+    operands=[Operand(type="Reg", size=32, dest="EA"),
+              Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
+add_group("pextrb",
+    cpu=["SSE41"],
+    modifiers=["SetVEX"],
+    opersize=64,
+    prefix=0x66,
+    opcode=[0x0F, 0x3A, 0x14],
+    operands=[Operand(type="Reg", size=64, dest="EA"),
+              Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
 
 add_insn("pextrb", "pextrb")
 add_insn("vpextrb", "pextrb", modifiers=[VEXL0], avx=True)
 
 add_group("pextrd",
     cpu=["SSE41"],
     modifiers=["SetVEX"],
-    opersize=32,
     prefix=0x66,
     opcode=[0x0F, 0x3A, 0x16],
     operands=[Operand(type="RM", size=32, relaxed=True, dest="EA"),
               Operand(type="SIMDReg", size=128, dest="Spare"),
               Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
 
 add_insn("pextrd", "pextrd")
 add_insn("vpextrd", "pextrd", modifiers=[VEXL0], avx=True)
 
 add_group("pextrq",
@@ skipping 13 matching lines @@
     cpu=["SSE41"],
     modifiers=["SetVEX"],
     prefix=0x66,
     opcode=[0x0F, 0x3A, 0x20],
     operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"),
               Operand(type="Mem", size=8, relaxed=True, dest="EA"),
               Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
 add_group("pinsrb",
     cpu=["SSE41"],
     modifiers=["SetVEX"],
-    opersize=32,
     prefix=0x66,
     opcode=[0x0F, 0x3A, 0x20],
     operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"),
               Operand(type="Reg", size=32, dest="EA"),
               Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
 add_group("pinsrb",
     cpu=["AVX"],
     vex=128,
     prefix=0x66,
     opcode=[0x0F, 0x3A, 0x20],
     operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
               Operand(type="SIMDReg", size=128, dest="VEX"),
               Operand(type="Mem", size=8, relaxed=True, dest="EA"),
               Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
 add_group("pinsrb",
     cpu=["AVX"],
     vex=128,
-    opersize=32,
     prefix=0x66,
     opcode=[0x0F, 0x3A, 0x20],
     operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"),
               Operand(type="SIMDReg", size=128, dest="VEX"),
               Operand(type="Reg", size=32, dest="EA"),
               Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
 
 add_insn("pinsrb", "pinsrb")
 add_insn("vpinsrb", "pinsrb", modifiers=[VEXL0], avx=True)
 
 add_group("pinsrd",
     cpu=["SSE41"],
     modifiers=["SetVEX"],
-    opersize=32,
     prefix=0x66,
     opcode=[0x0F, 0x3A, 0x22],
     operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"),
               Operand(type="RM", size=32, relaxed=True, dest="EA"),
               Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
 add_group("pinsrd",
     cpu=["AVX"],
     vex=128,
-    opersize=32,
     prefix=0x66,
     opcode=[0x0F, 0x3A, 0x22],
     operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
               Operand(type="SIMDReg", size=128, dest="VEX"),
               Operand(type="RM", size=32, relaxed=True, dest="EA"),
               Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
 
 add_insn("pinsrd", "pinsrd")
 add_insn("vpinsrd", "pinsrd", modifiers=[VEXL0], avx=True)
 
@@ skipping 666 matching lines @@
 add_insn("vaesenc", "aes", modifiers=[0x38, 0xDC, VEXL0], avx=True)
 add_insn("vaesenclast", "aes", modifiers=[0x38, 0xDD, VEXL0], avx=True)
 add_insn("vaesdec", "aes", modifiers=[0x38, 0xDE, VEXL0], avx=True)
 add_insn("vaesdeclast", "aes", modifiers=[0x38, 0xDF, VEXL0], avx=True)
 
 add_group("aesimc",
     cpu=["AES"],
     modifiers=["Op1Add", "Op2Add", "SetVEX"],
     prefix=0x66,
     opcode=[0x0F, 0x00, 0x00],
-    operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"),
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
               Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
 
 add_insn("aesimc", "aesimc", modifiers=[0x38, 0xDB])
 add_insn("vaesimc", "aesimc", modifiers=[0x38, 0xDB, VEXL0], avx=True)
 
 
 add_group("aes_imm",
     cpu=["AES"],
     modifiers=["Op1Add", "Op2Add", "SetVEX"],
     prefix=0x66,
@@ skipping 48 matching lines @@
     operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
               Operand(type="SIMDReg", size=128, dest="VEX"),
               Operand(type="SIMDRM",  size=128, relaxed=True, dest="EA")])
 
 for comb, combval in zip(["lql","hql","lqh","hqh"], [0x00,0x01,0x10,0x11]):
     add_insn("pclmul"+comb+"qdq", "pclmulqdq_fixed", modifiers=[combval])
     add_insn("vpclmul"+comb+"qdq", "pclmulqdq_fixed",
              modifiers=[combval, VEXL0], avx=True)
 
 #####################################################################
+# AVX Post-32nm instructions
+#####################################################################
+
+# RDRAND
+add_group("rdrand",
+    cpu=["RDRAND"],
+    opersize=16,
+    opcode=[0x0F, 0xC7],
+    spare=6,
+    operands=[Operand(type="Reg", size=16, dest="EA")])
+add_group("rdrand",
+    #suffix="l",
+    cpu=["RDRAND"],
+    opersize=32,
+    opcode=[0x0F, 0xC7],
+    spare=6,
+    operands=[Operand(type="Reg", size=32, dest="EA")])
+add_group("rdrand",
+    cpu=["RDRAND"],
+    opersize=64,
+    opcode=[0x0F, 0xC7],
+    spare=6,
+    operands=[Operand(type="Reg", size=64, dest="EA")])
+add_insn("rdrand", "rdrand")
+
+# FSGSBASE instructions
+add_group("fs_gs_base",
+    only64=True,
+    cpu=["FSGSBASE"],
+    modifiers=['SpAdd'],
+    opersize=32,
+    prefix=0xF3,
+    opcode=[0x0F, 0xAE],
+    operands=[Operand(type="Reg", size=32, dest="EA")])
+add_group("fs_gs_base",
+    only64=True,
+    cpu=["FSGSBASE"],
+    opersize=64,
+    modifiers=['SpAdd'],
+    prefix=0xF3,
+    opcode=[0x0F, 0xAE],
+    operands=[Operand(type="Reg", size=64, dest="EA")])
+
+add_insn("rdfsbase", "fs_gs_base", modifiers=[0], only64=True)
+add_insn("rdgsbase", "fs_gs_base", modifiers=[1], only64=True)
+add_insn("wrfsbase", "fs_gs_base", modifiers=[2], only64=True)
+add_insn("wrgsbase", "fs_gs_base", modifiers=[3], only64=True)
+
+# Float-16 conversion instructions
+for g in ['ps2ph', 'ph2ps']:
+    operands1=[]
+    operands1.append(Operand(type="SIMDReg", size=128, dest="EA"))
+    operands1.append(Operand(type="SIMDReg", size=128, dest="Spare"))
+
+    operands2=[]
+    operands2.append(Operand(type="Mem", size=64, dest="EA"))
+    operands2.append(Operand(type="SIMDReg", size=128, dest="Spare"))
+
+    operands3=[]
+    operands3.append(Operand(type="SIMDReg", size=128, dest="EA"))
+    operands3.append(Operand(type="SIMDReg", size=256, dest="Spare"))
+
+    operands4=[]
+    operands4.append(Operand(type="Mem", size=128, dest="EA"))
+    operands4.append(Operand(type="SIMDReg", size=256, dest="Spare"))
+
+    if g == 'ph2ps':
+        operands1.reverse()
+        operands2.reverse()
+        operands3.reverse()
+        operands4.reverse()
+        map = 0x38
+    elif g == 'ps2ph':
+        immop = Operand(type="Imm", size=8, relaxed=True, dest="Imm")
+        operands1.append(immop)
+        operands2.append(immop)
+        operands3.append(immop)
+        operands4.append(immop)
+        map = 0x3A
+
+    add_group("avx_cvt" + g,
+        cpu=["F16C", "AVX"],
+        modifiers=["PreAdd", "Op2Add"],
+        vex=128,
+        prefix=0x00,
+        opcode=[0x0F, map, 0x00],
+        operands=operands1)
+
+    add_group("avx_cvt" + g,
+        cpu=["F16C", "AVX"],
+        modifiers=["PreAdd", "Op2Add"],
+        vex=128,
+        prefix=0x00,
+        opcode=[0x0F, map, 0x00],
+        operands=operands2)
+
+    add_group("avx_cvt" + g,
+        cpu=["F16C", "AVX"],
+        modifiers=["PreAdd", "Op2Add"],
+        vex=256,
+        prefix=0x00,
+        opcode=[0x0F, map, 0x00],
+        operands=operands3)
+
+    add_group("avx_cvt" + g,
+        cpu=["F16C", "AVX"],
+        modifiers=["PreAdd", "Op2Add"],
+        vex=256,
+        prefix=0x00,
+        opcode=[0x0F, map, 0x00],
+        operands=operands4)
+
+add_insn("vcvtps2ph", "avx_cvtps2ph", modifiers=[0x66, 0x1D], avx=True)
+add_insn("vcvtph2ps", "avx_cvtph2ps", modifiers=[0x66, 0x13], avx=True)
+
+#####################################################################
 # AMD SSE4a instructions
 #####################################################################
 
 add_group("extrq",
     cpu=["SSE4a"],
     prefix=0x66,
     opcode=[0x0F, 0x78],
     operands=[Operand(type="SIMDReg", size=128, dest="EA"),
               Operand(type="Imm", size=8, relaxed=True, dest="EA"),
               Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
@@ skipping 35 matching lines @@
 add_group("movntss",
     cpu=["SSE4a"],
     prefix=0xF3,
     opcode=[0x0F, 0x2B],
     operands=[Operand(type="Mem", size=32, relaxed=True, dest="EA"),
               Operand(type="SIMDReg", size=128, dest="Spare")])
 
 add_insn("movntss", "movntss")
 
 #####################################################################
-# AMD SSE5 instructions
-#####################################################################
-
-add_group("sse5com",
-    cpu=["SSE5"],
+# AMD XOP instructions
+#####################################################################
+
+add_group("vfrc_pdps",
+    cpu=["XOP"],
+    modifiers=["Op1Add"],
+    xop=128,
+    opcode=[0x09, 0x80],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
+add_group("vfrc_pdps",
+    cpu=["XOP"],
+    modifiers=["Op1Add"],
+    xop=256,
+    opcode=[0x09, 0x80],
+    operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
+              Operand(type="SIMDRM", size=256, relaxed=True, dest="EA")])
+add_insn("vfrczpd", "vfrc_pdps", modifiers=[0x01])
+add_insn("vfrczps", "vfrc_pdps", modifiers=[0x00])
+
+add_group("vfrczsd",
+    cpu=["XOP"],
+    xop=128,
+    opcode=[0x09, 0x83],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDReg", size=128, dest="EA")])
+add_group("vfrczsd",
+    cpu=["XOP"],
+    xop=128,
+    opcode=[0x09, 0x83],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="Mem", size=64, relaxed=True, dest="EA")])
+add_insn("vfrczsd", "vfrczsd")
+
+add_group("vfrczss",
+    cpu=["XOP"],
+    xop=128,
+    opcode=[0x09, 0x82],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDReg", size=128, dest="EA")])
+add_group("vfrczss",
+    cpu=["XOP"],
+    xop=128,
+    opcode=[0x09, 0x82],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="Mem", size=32, relaxed=True, dest="EA")])
+add_insn("vfrczss", "vfrczss")
+
+add_group("vpcmov",
+    cpu=["XOP"],
+    xop=128,
+    xopw=0,
+    opcode=[0x08, 0xA2],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDReg", size=128, dest="VEX"),
+              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
+              Operand(type="SIMDReg", size=128, dest="VEXImmSrc")])
+add_group("vpcmov",
+    cpu=["XOP"],
+    xop=128,
+    xopw=1,
+    opcode=[0x08, 0xA2],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDReg", size=128, dest="VEX"),
+              Operand(type="SIMDReg", size=128, dest="VEXImmSrc"),
+              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
+add_group("vpcmov",
+    cpu=["XOP"],
+    xop=256,
+    xopw=0,
+    opcode=[0x08, 0xA2],
+    operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
+              Operand(type="SIMDReg", size=256, dest="VEX"),
+              Operand(type="SIMDRM", size=256, relaxed=True, dest="EA"),
+              Operand(type="SIMDReg", size=256, dest="VEXImmSrc")])
+add_group("vpcmov",
+    cpu=["XOP"],
+    xop=256,
+    xopw=1,
+    opcode=[0x08, 0xA2],
+    operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
+              Operand(type="SIMDReg", size=256, dest="VEX"),
+              Operand(type="SIMDReg", size=256, dest="VEXImmSrc"),
+              Operand(type="SIMDRM", size=256, relaxed=True, dest="EA")])
+
+add_insn("vpcmov", "vpcmov")
+
+add_group("vpcom",
+    cpu=["XOP"],
+    modifiers=["Op1Add", "Imm8"],
+    xop=128,
+    opcode=[0x08, 0x00],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDReg", size=128, dest="VEX"),
+              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
+add_group("vpcom_imm",
+    cpu=["XOP"],
+    modifiers=["Op1Add"],
+    xop=128,
+    opcode=[0x08, 0x00],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDReg", size=128, dest="VEX"),
+              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
+              Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
+
+for opc, sfx in [(0xCC, "b"),
+                 (0xCE, "d"),
+                 (0xCD, "w"),
+                 (0xCF, "q"),
+                 (0xEC, "ub"),
+                 (0xEE, "ud"),
+                 (0xEF, "uq"),
+                 (0xED, "uw")]:
+    add_insn("vpcom"+sfx, "vpcom_imm", modifiers=[opc])
+    for ib, cc in enumerate(["lt", "le", "gt", "ge",
+                             "eq", "neq", "false", "true"]):
+        add_insn("vpcom"+cc+sfx, "vpcom", modifiers=[opc, ib])
+    # ne alias for neq
+    add_insn("vpcomne"+sfx, "vpcom", modifiers=[opc, 5])
+
+add_group("vphaddsub",
+    cpu=["XOP"],
+    modifiers=["Op1Add"],
+    xop=128,
+    opcode=[0x09, 0x00],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
+
+add_insn("vphaddbw", "vphaddsub", modifiers=[0xC1])
+add_insn("vphaddbd", "vphaddsub", modifiers=[0xC2])
+add_insn("vphaddbq", "vphaddsub", modifiers=[0xC3])
+add_insn("vphaddwd", "vphaddsub", modifiers=[0xC6])
+add_insn("vphaddwq", "vphaddsub", modifiers=[0xC7])
+add_insn("vphadddq", "vphaddsub", modifiers=[0xCB])
+
+add_insn("vphaddubw", "vphaddsub", modifiers=[0xD1])
+add_insn("vphaddubd", "vphaddsub", modifiers=[0xD2])
+add_insn("vphaddubq", "vphaddsub", modifiers=[0xD3])
+add_insn("vphadduwd", "vphaddsub", modifiers=[0xD6])
+add_insn("vphadduwq", "vphaddsub", modifiers=[0xD7])
+add_insn("vphaddudq", "vphaddsub", modifiers=[0xD8])
+
+add_insn("vphsubbw", "vphaddsub", modifiers=[0xE1])
+add_insn("vphsubwd", "vphaddsub", modifiers=[0xE2])
+add_insn("vphsubdq", "vphaddsub", modifiers=[0xE3])
+
+add_group("vpma",
+    cpu=["XOP"],
+    modifiers=["Op1Add"],
+    xop=128,
+    opcode=[0x08, 0x00],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDReg", size=128, dest="VEX"),
+              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
+              Operand(type="SIMDReg", size=128, dest="VEXImmSrc")])
+
+add_insn("vpmacsdd", "vpma", modifiers=[0x9E])
+add_insn("vpmacsdqh", "vpma", modifiers=[0x9F])
+add_insn("vpmacsdql", "vpma", modifiers=[0x97])
+add_insn("vpmacssdd", "vpma", modifiers=[0x8E])
+add_insn("vpmacssdqh", "vpma", modifiers=[0x8F])
+add_insn("vpmacssdql", "vpma", modifiers=[0x87])
+add_insn("vpmacsswd", "vpma", modifiers=[0x86])
+add_insn("vpmacssww", "vpma", modifiers=[0x85])
+add_insn("vpmacswd", "vpma", modifiers=[0x96])
+add_insn("vpmacsww", "vpma", modifiers=[0x95])
+add_insn("vpmadcsswd", "vpma", modifiers=[0xA6])
+add_insn("vpmadcswd", "vpma", modifiers=[0xB6])
+
+add_group("vpperm",
+    cpu=["XOP"],
+    xop=128,
+    xopw=0,
+    opcode=[0x08, 0xA3],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDReg", size=128, dest="VEX"),
+              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
+              Operand(type="SIMDReg", size=128, dest="VEXImmSrc")])
+add_group("vpperm",
+    cpu=["XOP"],
+    xop=128,
+    xopw=1,
+    opcode=[0x08, 0xA3],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDReg", size=128, dest="VEX"),
+              Operand(type="SIMDReg", size=128, dest="VEXImmSrc"),
+              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
+add_insn("vpperm", "vpperm")
+
+add_group("vprot",
+    cpu=["XOP"],
+    modifiers=["Op1Add"],
+    xop=128,
+    xopw=0,
+    opcode=[0x09, 0x90],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
+              Operand(type="SIMDReg", size=128, dest="VEX")])
+add_group("vprot",
+    cpu=["XOP"],
+    modifiers=["Op1Add"],
+    xop=128,
+    xopw=1,
+    opcode=[0x09, 0x90],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDReg", size=128, dest="VEX"),
+              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
+add_group("vprot",
+    cpu=["XOP"],
+    modifiers=["Op1Add"],
+    xop=128,
+    opcode=[0x08, 0xC0],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
+              Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
+for opc, sfx in enumerate(["b", "w", "d", "q"]):
+    add_insn("vprot"+sfx, "vprot", modifiers=[opc])
+
+add_group("amd_vpshift",
+    cpu=["XOP"],
+    modifiers=["Op1Add"],
+    xop=128,
+    xopw=0,
+    opcode=[0x09, 0x00],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
+              Operand(type="SIMDReg", size=128, dest="VEX")])
+add_group("amd_vpshift",
+    cpu=["XOP"],
+    modifiers=["Op1Add"],
+    xop=128,
+    xopw=1,
+    opcode=[0x09, 0x00],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDReg", size=128, dest="VEX"),
+              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
+for opc, sfx in enumerate(["b", "w", "d", "q"]):
+    add_insn("vpsha"+sfx, "amd_vpshift", modifiers=[0x98+opc])
+    add_insn("vpshl"+sfx, "amd_vpshift", modifiers=[0x94+opc])
+
+#####################################################################
+# AMD FMA4 instructions (same as original Intel FMA instructions)
+#####################################################################
+
+add_group("fma_128_256",
+    cpu=["FMA4"],
     modifiers=["Op2Add"],
-    opcode=[0x0F, 0x25, 0x00],
-    drex_oc0=0,
-    operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
-              Operand(type="SIMDReg", size=128, dest="Spare"),
-              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
-              Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
+    vex=128,
+    vexw=0,
+    prefix=0x66,
+    opcode=[0x0F, 0x3A, 0x00],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDReg", size=128, dest="VEX"),
+              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
+              Operand(type="SIMDReg", size=128, dest="VEXImmSrc")])
+add_group("fma_128_256",
+    cpu=["FMA4"],
+    modifiers=["Op2Add"],
+    vex=128,
+    vexw=1,
+    prefix=0x66,
+    opcode=[0x0F, 0x3A, 0x00],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDReg", size=128, dest="VEX"),
+              Operand(type="SIMDReg", size=128, dest="VEXImmSrc"),
+              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
+add_group("fma_128_256",
+    cpu=["FMA4"],
+    modifiers=["Op2Add"],
+    vex=256,
+    vexw=0,
+    prefix=0x66,
+    opcode=[0x0F, 0x3A, 0x00],
+    operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
+              Operand(type="SIMDReg", size=256, dest="VEX"),
+              Operand(type="SIMDRM", size=256, relaxed=True, dest="EA"),
+              Operand(type="SIMDReg", size=256, dest="VEXImmSrc")])
+add_group("fma_128_256",
+    cpu=["FMA4"],
+    modifiers=["Op2Add"],
+    vex=256,
+    vexw=1,
+    prefix=0x66,
+    opcode=[0x0F, 0x3A, 0x00],
+    operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
+              Operand(type="SIMDReg", size=256, dest="VEX"),
+              Operand(type="SIMDReg", size=256, dest="VEXImmSrc"),
+              Operand(type="SIMDRM", size=256, relaxed=True, dest="EA")])
+
+add_insn("vfmaddpd", "fma_128_256", modifiers=[0x69])
+add_insn("vfmaddps", "fma_128_256", modifiers=[0x68])
+add_insn("vfmaddsubpd", "fma_128_256", modifiers=[0x5D])
+add_insn("vfmaddsubps", "fma_128_256", modifiers=[0x5C])
+add_insn("vfmsubaddpd", "fma_128_256", modifiers=[0x5F])
+add_insn("vfmsubaddps", "fma_128_256", modifiers=[0x5E])
+add_insn("vfmsubpd", "fma_128_256", modifiers=[0x6D])
+add_insn("vfmsubps", "fma_128_256", modifiers=[0x6C])
+add_insn("vfnmaddpd", "fma_128_256", modifiers=[0x79])
+add_insn("vfnmaddps", "fma_128_256", modifiers=[0x78])
+add_insn("vfnmsubpd", "fma_128_256", modifiers=[0x7D])
+add_insn("vfnmsubps", "fma_128_256", modifiers=[0x7C])
 
 for sz in [32, 64]:
-    add_group("sse5com%d" % sz,
-        cpu=["SSE5"],
+    add_group("fma_128_m%d" % sz,
+        cpu=["FMA4"],
         modifiers=["Op2Add"],
-        opcode=[0x0F, 0x25, 0x00],
-        drex_oc0=0,
-        operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
-                  Operand(type="SIMDReg", size=128, dest="Spare"),
+        vex=128,
+        vexw=0,
+        prefix=0x66,
+        opcode=[0x0F, 0x3A, 0x00],
+        operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+                  Operand(type="SIMDReg", size=128, dest="VEX"),
                   Operand(type="SIMDReg", size=128, dest="EA"),
-                  Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
-    add_group("sse5com%d" % sz,
-        cpu=["SSE5"],
+                  Operand(type="SIMDReg", size=128, dest="VEXImmSrc")])
+    add_group("fma_128_m%d" % sz,
+        cpu=["FMA4"],
         modifiers=["Op2Add"],
-        opcode=[0x0F, 0x25, 0x00],
-        drex_oc0=0,
-        operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
-                  Operand(type="SIMDReg", size=128, dest="Spare"),
+        vex=128,
+        vexw=0,
+        prefix=0x66,
+        opcode=[0x0F, 0x3A, 0x00],
+        operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+                  Operand(type="SIMDReg", size=128, dest="VEX"),
                   Operand(type="Mem", size=sz, relaxed=True, dest="EA"),
-                  Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
-
-# Condition code versions
-add_group("sse5comcc",
-    cpu=["SSE5"],
-    modifiers=["Op2Add", "Imm8"],
-    opcode=[0x0F, 0x25, 0x00],
-    drex_oc0=0,
-    operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
-              Operand(type="SIMDReg", size=128, dest="Spare"),
-              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
-
-for sz in [32, 64]:
-    add_group("sse5comcc%d" % sz,
-        cpu=["SSE5"],
-        modifiers=["Op2Add", "Imm8"],
-        opcode=[0x0F, 0x25, 0x00],
-        drex_oc0=0,
-        operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
-                  Operand(type="SIMDReg", size=128, dest="Spare"),
-                  Operand(type="SIMDReg", size=128, dest="EA")])
-    add_group("sse5comcc%d" % sz,
-        cpu=["SSE5"],
-        modifiers=["Op2Add", "Imm8"],
-        opcode=[0x0F, 0x25, 0x00],
-        drex_oc0=0,
-        operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
-                  Operand(type="SIMDReg", size=128, dest="Spare"),
+                  Operand(type="SIMDReg", size=128, dest="VEXImmSrc")])
+    add_group("fma_128_m%d" % sz,
+        cpu=["FMA4"],
+        modifiers=["Op2Add"],
+        vex=128,
+        vexw=1,
+        prefix=0x66,
+        opcode=[0x0F, 0x3A, 0x00],
+        operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+                  Operand(type="SIMDReg", size=128, dest="VEX"),
+                  Operand(type="SIMDReg", size=128, dest="VEXImmSrc"),
                   Operand(type="Mem", size=sz, relaxed=True, dest="EA")])
 
-sse5coms = [(0, ""),
-            (0x0, "eq"),
-            (0x1, "lt"), (0x1, "unge"),
-            (0x2, "le"), (0x2, "ungt"),
-            (0x3, "unord"),
-            (0x4, "ne"), (0x4, "neq"),
-            (0x5, "nlt"), (0x5, "uge"),
-            (0x6, "nle"), (0x6, "ugt"),
-            (0x7, "ord"),
-            (0x8, "ueq"),
-            (0x9, "ult"), (0x9, "nge"),
-            (0xa, "ule"), (0xa, "ngt"),
-            (0xb, "false"),
-            (0xc, "une"), (0xc, "uneq"),
-            (0xd, "unlt"), (0xd, "ge"),
-            (0xe, "unle"), (0xe, "gt"),
-            (0xf, "true")]
-for ib, cc in sse5coms:
-    if cc:
-        iname = "sse5comcc"
-    else:
-        iname = "sse5com"
-    add_insn("com"+cc+"ps", iname, modifiers=[0x2C, ib])
-    add_insn("com"+cc+"pd", iname, modifiers=[0x2D, ib])
-    add_insn("com"+cc+"ss", iname+"32", modifiers=[0x2E, ib])
-    add_insn("com"+cc+"sd", iname+"64", modifiers=[0x2F, ib])
-
-sse5coms = list(enumerate(["lt", "le", "gt", "ge",
-                           "eq", "neq", "false", "true"]))
-sse5coms.append((5, "ne"))
-sse5coms.append((0, ""))
-for ib, cc in sse5coms:
-    if cc:
-        iname = "sse5comcc"
-    else:
-        iname = "sse5com"
-    add_insn("pcom"+cc+"b", iname, modifiers=[0x4C, ib])
-    add_insn("pcom"+cc+"w", iname, modifiers=[0x4D, ib])
-    add_insn("pcom"+cc+"d", iname, modifiers=[0x4E, ib])
-    add_insn("pcom"+cc+"q", iname, modifiers=[0x4F, ib])
-
-    add_insn("pcom"+cc+"ub", iname, modifiers=[0x6C, ib])
-    add_insn("pcom"+cc+"uw", iname, modifiers=[0x6D, ib])
-    add_insn("pcom"+cc+"ud", iname, modifiers=[0x6E, ib])
-    add_insn("pcom"+cc+"uq", iname, modifiers=[0x6F, ib])
-
-add_group("cvtph2ps",
-    cpu=["SSE5"],
-    opcode=[0x0F, 0x7A, 0x30],
-    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
-              Operand(type="SIMDReg", size=128, dest="EA")])
-add_group("cvtph2ps",
-    cpu=["SSE5"],
-    opcode=[0x0F, 0x7A, 0x30],
-    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
-              Operand(type="Mem", size=64, relaxed=True, dest="EA")])
-
-add_insn("cvtph2ps", "cvtph2ps")
-
-add_group("cvtps2ph",
-    cpu=["SSE5"],
-    opcode=[0x0F, 0x7A, 0x31],
-    operands=[Operand(type="SIMDReg", size=128, dest="EA"),
-              Operand(type="SIMDReg", size=128, dest="Spare")])
-add_group("cvtps2ph",
-    cpu=["SSE5"],
-    opcode=[0x0F, 0x7A, 0x31],
-    operands=[Operand(type="Mem", size=64, relaxed=True, dest="EA"),
-              Operand(type="SIMDReg", size=128, dest="Spare")])
-
-add_insn("cvtps2ph", "cvtps2ph")
-
-add_group("sse5arith",
-    cpu=["SSE5"],
-    modifiers=["Op2Add"],
-    opcode=[0x0F, 0x24, 0x00],
-    drex_oc0=0,
-    operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
-              Operand(type="SIMDRegMatch0", size=128, dest=None),
-              Operand(type="SIMDReg", size=128, dest="Spare"),
-              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
-add_group("sse5arith",
-    cpu=["SSE5"],
-    modifiers=["Op2Add"],
-    opcode=[0x0F, 0x24, 0x00],
-    drex_oc0=1,
-    operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
-              Operand(type="SIMDRegMatch0", size=128, dest=None),
-              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
-              Operand(type="SIMDReg", size=128, dest="Spare")])
-add_group("sse5arith",
-    cpu=["SSE5"],
-    modifiers=["Op2Add"],
-    opcode=[0x0F, 0x24, 0x04],
-    drex_oc0=0,
-    operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
-              Operand(type="SIMDReg", size=128, dest="Spare"),
-              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
-              Operand(type="SIMDRegMatch0", size=128, dest=None)])
-add_group("sse5arith",
-    cpu=["SSE5"],
-    modifiers=["Op2Add"],
-    opcode=[0x0F, 0x24, 0x04],
-    drex_oc0=1,
-    operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
-              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
-              Operand(type="SIMDReg", size=128, dest="Spare"),
-              Operand(type="SIMDRegMatch0", size=128, dest=None)])
-
-for sz in [32, 64]:
-    add_group("sse5arith%d" % sz,
-        cpu=["SSE5"],
-        modifiers=["Op2Add"],
-        opcode=[0x0F, 0x24, 0x00],
-        drex_oc0=0,
-        operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
-                  Operand(type="SIMDRegMatch0", size=128, dest=None),
-                  Operand(type="SIMDReg", size=128, dest="Spare"),
-                  Operand(type="SIMDReg", size=128, dest="EA")])
-    add_group("sse5arith%d" % sz,
-        cpu=["SSE5"],
-        modifiers=["Op2Add"],
-        opcode=[0x0F, 0x24, 0x00],
-        drex_oc0=0,
-        operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
-                  Operand(type="SIMDRegMatch0", size=128, dest=None),
-                  Operand(type="SIMDReg", size=128, dest="Spare"),
-                  Operand(type="Mem", size=sz, relaxed=True, dest="EA")])
-    add_group("sse5arith%d" % sz,
-        cpu=["SSE5"],
-        modifiers=["Op2Add"],
-        opcode=[0x0F, 0x24, 0x00],
-        drex_oc0=1,
-        operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
-                  Operand(type="SIMDRegMatch0", size=128, dest=None),
-                  Operand(type="SIMDReg", size=128, dest="EA"),
-                  Operand(type="SIMDReg", size=128, dest="Spare")])
-    add_group("sse5arith%d" % sz,
-        cpu=["SSE5"],
-        modifiers=["Op2Add"],
-        opcode=[0x0F, 0x24, 0x00],
-        drex_oc0=1,
-        operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
-                  Operand(type="SIMDRegMatch0", size=128, dest=None),
-                  Operand(type="Mem", size=sz, relaxed=True, dest="EA"),
-                  Operand(type="SIMDReg", size=128, dest="Spare")])
-    add_group("sse5arith%d" % sz,
-        cpu=["SSE5"],
-        modifiers=["Op2Add"],
-        opcode=[0x0F, 0x24, 0x04],
-        drex_oc0=0,
-        operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
-                  Operand(type="SIMDReg", size=128, dest="Spare"),
-                  Operand(type="SIMDReg", size=128, dest="EA"),
-                  Operand(type="SIMDRegMatch0", size=128, dest=None)])
-    add_group("sse5arith%d" % sz,
-        cpu=["SSE5"],
-        modifiers=["Op2Add"],
-        opcode=[0x0F, 0x24, 0x04],
-        drex_oc0=0,
-        operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
-                  Operand(type="SIMDReg", size=128, dest="Spare"),
-                  Operand(type="Mem", size=sz, relaxed=True, dest="EA"),
-                  Operand(type="SIMDRegMatch0", size=128, dest=None)])
-    add_group("sse5arith%d" % sz,
-        cpu=["SSE5"],
-        modifiers=["Op2Add"],
-        opcode=[0x0F, 0x24, 0x04],
-        drex_oc0=1,
-        operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
-                  Operand(type="SIMDReg", size=128, dest="EA"),
-                  Operand(type="SIMDReg", size=128, dest="Spare"),
-                  Operand(type="SIMDRegMatch0", size=128, dest=None)])
-    add_group("sse5arith%d" % sz,
-        cpu=["SSE5"],
-        modifiers=["Op2Add"],
-        opcode=[0x0F, 0x24, 0x04],
-        drex_oc0=1,
-        operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
-                  Operand(type="Mem", size=sz, relaxed=True, dest="EA"),
-                  Operand(type="SIMDReg", size=128, dest="Spare"),
-                  Operand(type="SIMDRegMatch0", size=128, dest=None)])
-
-add_insn("fmaddps", "sse5arith", modifiers=[0x00])
-add_insn("fmaddpd", "sse5arith", modifiers=[0x01])
-add_insn("fmaddss", "sse5arith32", modifiers=[0x02])
-add_insn("fmaddsd", "sse5arith64", modifiers=[0x03])
-
-add_insn("fmsubps", "sse5arith", modifiers=[0x08])
-add_insn("fmsubpd", "sse5arith", modifiers=[0x09])
-add_insn("fmsubss", "sse5arith32", modifiers=[0x0A])
-add_insn("fmsubsd", "sse5arith64", modifiers=[0x0B])
-
-add_insn("fnmaddps", "sse5arith", modifiers=[0x10])
-add_insn("fnmaddpd", "sse5arith", modifiers=[0x11])
-add_insn("fnmaddss", "sse5arith32", modifiers=[0x12])
-add_insn("fnmaddsd", "sse5arith64", modifiers=[0x13])
-
-add_insn("fnmsubps", "sse5arith", modifiers=[0x18])
-add_insn("fnmsubpd", "sse5arith", modifiers=[0x19])
-add_insn("fnmsubss", "sse5arith32", modifiers=[0x1A])
-add_insn("fnmsubsd", "sse5arith64", modifiers=[0x1B])
-
-add_insn("pcmov", "sse5arith", modifiers=[0x22])
-
-add_insn("permps", "sse5arith", modifiers=[0x20])
-add_insn("permpd", "sse5arith", modifiers=[0x21])
-add_insn("pperm", "sse5arith", modifiers=[0x23])
-
-add_group("sse5two",
-    cpu=["SSE5"],
-    modifiers=["Op2Add"],
-    opcode=[0x0F, 0x7A, 0x00],
-    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
-              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
-for sz in [32, 64]:
-    add_group("sse5two%d" % sz,
-        cpu=["SSE5"],
-        modifiers=["Op2Add"],
-        opcode=[0x0F, 0x7A, 0x00],
-        operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
-                  Operand(type="SIMDReg", size=128, dest="EA")])
-    add_group("sse5two%d" % sz,
-        cpu=["SSE5"],
-        modifiers=["Op2Add"],
-        opcode=[0x0F, 0x7A, 0x00],
-        operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
-                  Operand(type="Mem", size=sz, relaxed=True, dest="EA")])
-
-add_insn("frczps", "sse5two", modifiers=[0x10])
-add_insn("frczpd", "sse5two", modifiers=[0x11])
-add_insn("frczss", "sse5two32", modifiers=[0x12])
-add_insn("frczsd", "sse5two64", modifiers=[0x13])
-
-add_insn("phaddbw", "sse5two", modifiers=[0x41])
-add_insn("phaddbd", "sse5two", modifiers=[0x42])
-add_insn("phaddbq", "sse5two", modifiers=[0x43])
-add_insn("phaddwd", "sse5two", modifiers=[0x46])
-add_insn("phaddwq", "sse5two", modifiers=[0x47])
-add_insn("phadddq", "sse5two", modifiers=[0x4B])
-
-add_insn("phaddubw", "sse5two", modifiers=[0x51])
-add_insn("phaddubd", "sse5two", modifiers=[0x52])
-add_insn("phaddubq", "sse5two", modifiers=[0x53])
-add_insn("phadduwd", "sse5two", modifiers=[0x56])
-add_insn("phadduwq", "sse5two", modifiers=[0x57])
-add_insn("phaddudq", "sse5two", modifiers=[0x5B])
-
-add_insn("phsubbw", "sse5two", modifiers=[0x61])
-add_insn("phsubwd", "sse5two", modifiers=[0x62])
-add_insn("phsubdq", "sse5two", modifiers=[0x63])
-
-add_group("sse5pmacs",
-    cpu=["SSE5"],
-    modifiers=["Op2Add"],
-    opcode=[0x0F, 0x24, 0x00],
-    drex_oc0=0,
-    operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
-              Operand(type="SIMDReg", size=128, dest="Spare"),
-              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
-              Operand(type="SIMDRegMatch0", size=128, dest=None)])
-
-add_insn("pmacsww", "sse5pmacs", modifiers=[0x95])
-add_insn("pmacswd", "sse5pmacs", modifiers=[0x96])
-add_insn("pmacsdql", "sse5pmacs", modifiers=[0x97])
-add_insn("pmacsdd", "sse5pmacs", modifiers=[0x9E])
-add_insn("pmacsdqh", "sse5pmacs", modifiers=[0x9F])
-
-add_insn("pmacssww", "sse5pmacs", modifiers=[0x85])
-add_insn("pmacsswd", "sse5pmacs", modifiers=[0x86])
-add_insn("pmacssdql", "sse5pmacs", modifiers=[0x87])
-add_insn("pmacssdd", "sse5pmacs", modifiers=[0x8E])
-add_insn("pmacssdqh", "sse5pmacs", modifiers=[0x8F])
-
-add_insn("pmadcsswd", "sse5pmacs", modifiers=[0xA6])
-add_insn("pmadcswd", "sse5pmacs", modifiers=[0xB6])
-
-add_group("sse5prot",
-    cpu=["SSE5"],
-    modifiers=["Op2Add"],
-    opcode=[0x0F, 0x24, 0x40],
-    drex_oc0=0,
-    operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
-              Operand(type="SIMDReg", size=128, dest="Spare"),
-              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
-add_group("sse5prot",
-    cpu=["SSE5"],
-    modifiers=["Op2Add"],
-    opcode=[0x0F, 0x24, 0x40],
-    drex_oc0=1,
-    operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
-              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
-              Operand(type="SIMDReg", size=128, dest="Spare")])
-add_group("sse5prot",
-    cpu=["SSE5"],
-    modifiers=["Op2Add"],
-    opcode=[0x0F, 0x7B, 0x40],
-    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
-              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
-              Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
-
-add_insn("protb", "sse5prot", modifiers=[0x00])
-add_insn("protw", "sse5prot", modifiers=[0x01])
-add_insn("protd", "sse5prot", modifiers=[0x02])
-add_insn("protq", "sse5prot", modifiers=[0x03])
-
-add_group("sse5psh",
-    cpu=["SSE5"],
-    modifiers=["Op2Add"],
-    opcode=[0x0F, 0x24, 0x44],
-    drex_oc0=0,
-    operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
-              Operand(type="SIMDReg", size=128, dest="Spare"),
-              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
-add_group("sse5psh",
-    cpu=["SSE5"],
-    modifiers=["Op2Add"],
-    opcode=[0x0F, 0x24, 0x44],
-    drex_oc0=1,
-    operands=[Operand(type="SIMDReg", size=128, dest="DREX"),
-              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
-              Operand(type="SIMDReg", size=128, dest="Spare")])
-
-add_insn("pshlb", "sse5psh", modifiers=[0x00])
-add_insn("pshlw", "sse5psh", modifiers=[0x01])
-add_insn("pshld", "sse5psh", modifiers=[0x02])
-add_insn("pshlq", "sse5psh", modifiers=[0x03])
-
-add_insn("pshab", "sse5psh", modifiers=[0x04])
-add_insn("pshaw", "sse5psh", modifiers=[0x05])
-add_insn("pshad", "sse5psh", modifiers=[0x06])
-add_insn("pshaq", "sse5psh", modifiers=[0x07])
-
-# roundps, roundpd, roundss, roundsd, ptest are in SSE4.1
-
-#####################################################################
-# Intel XSAVE instructions
+add_insn("vfmaddsd", "fma_128_m64", modifiers=[0x6B])
+add_insn("vfmaddss", "fma_128_m32", modifiers=[0x6A])
+add_insn("vfmsubsd", "fma_128_m64", modifiers=[0x6F])
+add_insn("vfmsubss", "fma_128_m32", modifiers=[0x6E])
+add_insn("vfnmaddsd", "fma_128_m64", modifiers=[0x7B])
+add_insn("vfnmaddss", "fma_128_m32", modifiers=[0x7A])
+add_insn("vfnmsubsd", "fma_128_m64", modifiers=[0x7F])
+add_insn("vfnmsubss", "fma_128_m32", modifiers=[0x7E])
+
+#####################################################################
+# Intel XSAVE and XSAVEOPT instructions
 #####################################################################
 add_insn("xgetbv", "threebyte", modifiers=[0x0F, 0x01, 0xD0],
          cpu=["XSAVE", "386"])
 add_insn("xsetbv", "threebyte", modifiers=[0x0F, 0x01, 0xD1],
          cpu=["XSAVE", "386", "Priv"])
 add_insn("xsave", "twobytemem", modifiers=[4, 0x0F, 0xAE],
          cpu=["XSAVE", "386"])
 add_insn("xrstor", "twobytemem", modifiers=[5, 0x0F, 0xAE],
          cpu=["XSAVE", "386"])
 
+add_insn("xsaveopt", "twobytemem", modifiers=[6, 0x0F, 0xAE],
+         cpu=["XSAVEOPT"])
+
+add_group("xsaveopt64",
+    modifiers=["SpAdd", "Op0Add", "Op1Add"],
+    opcode=[0x00, 0x00],
+    spare=0,
+    opersize=64,
+    operands=[Operand(type="Mem", relaxed=True, dest="EA")])
+add_insn("xsaveopt64", "xsaveopt64", modifiers=[6, 0x0F, 0xAE],
+         cpu=["XSAVEOPT"], only64=True)
+
 #####################################################################
 # Intel MOVBE instruction
 #####################################################################
 for sz in (16, 32, 64):
     add_group("movbe",
         cpu=["MOVBE"],
         opersize=sz,
         opcode=[0x0F, 0x38, 0xF0],
         operands=[Operand(type="Reg", size=sz, dest="Spare"),
                   Operand(type="Mem", size=sz, relaxed=True, dest="EA")])
@@ skipping 334 matching lines @@
 # Output generation
 #####################################################################
 
 out_dir = ""
 if len(sys.argv) > 1:
   out_dir = sys.argv[1]
 
 output_groups(file(os.path.join(out_dir, "x86insns.c"), "wt"))
 output_gas_insns(file(os.path.join(out_dir, "x86insn_gas.gperf"), "wt"))
 output_nasm_insns(file(os.path.join(out_dir, "x86insn_nasm.gperf"), "wt"))