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Unified Diff: third_party/yasm/patched-yasm/x86insns.c

Issue 6170009: Update our yasm copy to yasm 1.1.0 (Part 1: yasm side)... (Closed) Base URL: svn://svn.chromium.org/chrome/trunk/deps/
Patch Set: Created 9 years, 11 months ago
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Index: third_party/yasm/patched-yasm/x86insns.c
===================================================================
--- third_party/yasm/patched-yasm/x86insns.c (revision 71129)
+++ third_party/yasm/patched-yasm/x86insns.c (working copy)
@@ -1,6 +1,6 @@
-/* Generated by gen_x86_insn.py r2193, do not edit */
+/* Generated by gen_x86_insn.py r2346, do not edit */
static const x86_info_operand insn_operands[] = {
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
@@ -30,6 +30,18 @@
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
+ {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
+ {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_Mem, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
@@ -56,94 +68,30 @@
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
- {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
- {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
+ {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
+ {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
- {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
- {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
- {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
- {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
- {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
- {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
- {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
+ {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+ {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
+ {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
+ {OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
- {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
- {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
- {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
- {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
- {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
- {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
- {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
- {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
- {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
- {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
- {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
- {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
- {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
- {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
- {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
- {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
- {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
- {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+ {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
- {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
- {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
- {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
- {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
- {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
- {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
- {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
- {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
- {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
@@ -222,6 +170,9 @@
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+ {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+ {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
@@ -233,7 +184,7 @@
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
- {OPT_XMM0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDRM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
@@ -243,9 +194,24 @@
{OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+ {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
+ {OPT_Mem, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+ {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
+ {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+ {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
+ {OPT_Mem, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
+ {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+ {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+ {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+ {OPT_XMM0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
@@ -435,6 +401,8 @@
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+ {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
@@ -451,10 +419,24 @@
{OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
+ {OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
+ {OPT_Creg, OPS_32, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
+ {OPT_Imm, OPS_Any, 0, 0, OPTM_Short, OPA_JmpRel, OPAP_None},
+ {OPT_Creg, OPS_32, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+ {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+ {OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
+ {OPT_Creg, OPS_64, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
+ {OPT_Imm, OPS_Any, 0, 0, OPTM_Short, OPA_JmpRel, OPAP_None},
+ {OPT_Creg, OPS_64, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
+ {OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
+ {OPT_Creg, OPS_16, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
+ {OPT_Imm, OPS_Any, 0, 0, OPTM_Short, OPA_JmpRel, OPAP_None},
+ {OPT_Creg, OPS_16, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
@@ -493,8 +475,6 @@
{OPT_Mem, OPS_Any, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_Any, 1, 0, OPTM_None, OPA_EA, OPAP_None},
- {OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None},
- {OPT_Mem, OPS_80, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
@@ -517,6 +497,14 @@
{OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm1, OPS_8, 1, 0, OPTM_None, OPA_None, OPAP_None},
+ {OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None},
+ {OPT_Mem, OPS_80, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+ {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_JmpFar, OPAP_None},
+ {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_JmpFar, OPAP_None},
+ {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_JmpFar, OPAP_None},
+ {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_JmpFar, OPAP_None},
+ {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_JmpFar, OPAP_None},
+ {OPT_Imm, OPS_BITS, 1, 0, OPTM_None, OPA_JmpFar, OPAP_None},
{OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
@@ -541,6 +529,8 @@
{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+ {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
@@ -553,18 +543,6 @@
{OPT_SIMDRM, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDRM, OPS_256, 0, 0, OPTM_None, OPA_EA, OPAP_None},
- {OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
- {OPT_Creg, OPS_16, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
- {OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
- {OPT_Creg, OPS_32, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
- {OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
- {OPT_Creg, OPS_64, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
- {OPT_Imm, OPS_Any, 0, 0, OPTM_Short, OPA_JmpRel, OPAP_None},
- {OPT_Creg, OPS_16, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
- {OPT_Imm, OPS_Any, 0, 0, OPTM_Short, OPA_JmpRel, OPAP_None},
- {OPT_Creg, OPS_32, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
- {OPT_Imm, OPS_Any, 0, 0, OPTM_Short, OPA_JmpRel, OPAP_None},
- {OPT_Creg, OPS_64, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
@@ -573,13 +551,21 @@
{OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Mem, OPS_80, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None},
+ {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+ {OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
+ {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+ {OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
+ {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+ {OPT_Mem, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
+ {OPT_Mem, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
+ {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
@@ -591,10 +577,10 @@
{OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
{OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
- {OPT_Mem, OPS_80, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Mem, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Mem, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
- {OPT_Mem, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
+ {OPT_MemEAX, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
+ {OPT_Mem, OPS_80, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_SS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_SS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
@@ -610,7 +596,6 @@
{OPT_GS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_GS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_GS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
- {OPT_MemEAX, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Mem, OPS_Any, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_ImmNotSegOff, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
{OPT_ImmNotSegOff, OPS_16, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
@@ -618,6 +603,7 @@
{OPT_Imm, OPS_16, 0, 0, OPTM_Near, OPA_JmpRel, OPAP_None},
{OPT_Imm, OPS_32, 0, 0, OPTM_Near, OPA_JmpRel, OPAP_None},
{OPT_Imm, OPS_Any, 0, 0, OPTM_Near, OPA_JmpRel, OPAP_None},
+ {OPT_Reg, OPS_BITS, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_RM, OPS_16, 0, 0, OPTM_Near, OPA_EA, OPAP_None},
{OPT_RM, OPS_32, 0, 0, OPTM_Near, OPA_EA, OPAP_None},
{OPT_RM, OPS_64, 0, 0, OPTM_Near, OPA_EA, OPAP_None},
@@ -635,6 +621,7 @@
{OPT_Reg, OPS_80, 0, 0, OPTM_To, OPA_Op1Add, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Op1Add, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Op1Add, OPAP_None},
+ {OPT_Mem, OPS_BITS, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_16, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
{OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_SImm, OPAP_None},
@@ -646,1437 +633,1487 @@
};
static const x86_insn_info empty_insn[] = {
- { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0 }
+ { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0 }
};
static const x86_insn_info not64_insn[] = {
- { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0 }
+ { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0 }
};
static const x86_insn_info onebyte_insn[] = {
- { 0, 0, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, MOD_DOpS64R}, 0, 0, 0, 0, 1, {0x00, 0, 0}, 0, 0, 0 }
+ { SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, MOD_DOpS64R}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 0, 0 }
};
static const x86_insn_info onebyte_prefix_insn[] = {
- { 0, 0, 0, 0, 0, {MOD_PreAdd, MOD_Op0Add, 0}, 0, 0, 0x00, 0, 1, {0x00, 0, 0}, 0, 0, 0 }
+ { SUF_Z, 0, 0, 0, 0, {MOD_PreAdd, MOD_Op0Add, 0}, 0, 0, 0x00, 1, {0x00, 0, 0}, 0, 0, 0 }
};
static const x86_insn_info twobyte_insn[] = {
- { SUF_L|SUF_Q, 0, 0, 0, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 0, 0 }
+ { SUF_L|SUF_Q|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 0, 0 }
};
static const x86_insn_info threebyte_insn[] = {
- { 0, 0, 0, 0, 0, {MOD_Op0Add, MOD_Op1Add, MOD_Op2Add}, 0, 0, 0, 0, 3, {0x00, 0x00, 0x00}, 0, 0, 0 }
+ { SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, MOD_Op1Add, MOD_Op2Add}, 0, 0, 0, 3, {0x00, 0x00, 0x00}, 0, 0, 0 }
};
static const x86_insn_info onebytemem_insn[] = {
- { SUF_L|SUF_Q|SUF_S, 0, 0, 0, 0, {MOD_SpAdd, MOD_Op0Add, 0}, 0, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 611 }
+ { SUF_L|SUF_Q|SUF_S|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, MOD_Op0Add, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 596 }
};
static const x86_insn_info twobytemem_insn[] = {
- { SUF_L|SUF_Q|SUF_S|SUF_W, 0, 0, 0, 0, {MOD_SpAdd, MOD_Op0Add, MOD_Op1Add}, 0, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 1, 488 }
+ { SUF_L|SUF_Q|SUF_S|SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, MOD_Op0Add, MOD_Op1Add}, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 1, 470 }
};
static const x86_insn_info mov_insn[] = {
- { SUF_B, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 351 },
- { SUF_W, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 353 },
- { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 355 },
- { SUF_B, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 357 },
- { SUF_W, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 359 },
- { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 361 },
- { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 327 },
- { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 329 },
- { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 331 },
- { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 333 },
- { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 335 },
- { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 337 },
- { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 339 },
- { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 341 },
- { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x88, 0xA2, 0}, 0, 2, 363 },
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 365 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 367 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 369 },
- { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x88, 0, 0}, 0, 2, 309 },
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x89, 0, 0}, 0, 2, 246 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x89, 0, 0}, 0, 2, 252 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x89, 0, 0}, 0, 2, 258 },
- { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x8A, 0xA0, 0}, 0, 2, 371 },
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 373 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 375 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 377 },
- { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x8A, 0, 0}, 0, 2, 311 },
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x8B, 0, 0}, 0, 2, 150 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x8B, 0, 0}, 0, 2, 153 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x8B, 0, 0}, 0, 2, 156 },
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 379 },
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 381 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 383 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 385 },
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 387 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 382 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 384 },
- { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xB0, 0, 0}, 0, 2, 389 },
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 391 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 393 },
- { GAS_ILLEGAL, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 395 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xB8, 0xC7, 0}, 0, 2, 397 },
- { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xC6, 0, 0}, 0, 2, 399 },
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 401 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 403 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 405 },
- { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xC6, 0, 0}, 0, 2, 407 },
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 409 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 411 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 413 },
- { SUF_L, NOT_64, CPU_586, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, 415 },
- { SUF_L, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, 417 },
- { SUF_Q, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, 419 },
- { SUF_L, NOT_64, CPU_586, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, 421 },
- { SUF_L, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, 416 },
- { SUF_Q, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, 423 },
- { SUF_L, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x23, 0}, 0, 2, 425 },
- { SUF_Q, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x23, 0}, 0, 2, 427 },
- { SUF_L, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x21, 0}, 0, 2, 426 },
- { SUF_Q, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x21, 0}, 0, 2, 429 },
- { GAS_ONLY|SUF_Q, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x6F, 0}, 0, 2, 234 },
- { GAS_ONLY|SUF_Q, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 281 },
- { GAS_ONLY|SUF_Q, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x7F, 0}, 0, 2, 317 },
- { GAS_ONLY|SUF_Q, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 283 },
- { GAS_ONLY|SUF_Q, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 64 },
- { GAS_ONLY|SUF_Q, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 319 },
- { GAS_ONLY|SUF_Q, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 287 },
- { GAS_ONLY|SUF_Q, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0xD6, 0}, 0, 2, 321 },
- { GAS_ONLY|SUF_Q, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 219 }
+ { SUF_B|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 317 },
+ { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 319 },
+ { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 321 },
+ { SUF_B|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 323 },
+ { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 325 },
+ { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 327 },
+ { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 293 },
+ { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 295 },
+ { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 297 },
+ { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 299 },
+ { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 301 },
+ { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 303 },
+ { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 305 },
+ { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 307 },
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x88, 0xA2, 0}, 0, 2, 329 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 331 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 333 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 335 },
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x88, 0, 0}, 0, 2, 275 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x89, 0, 0}, 0, 2, 212 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x89, 0, 0}, 0, 2, 218 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x89, 0, 0}, 0, 2, 224 },
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8A, 0xA0, 0}, 0, 2, 337 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 339 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 341 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 343 },
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8A, 0, 0}, 0, 2, 277 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x8B, 0, 0}, 0, 2, 98 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8B, 0, 0}, 0, 2, 101 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x8B, 0, 0}, 0, 2, 104 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 345 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 347 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 349 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 351 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 353 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 348 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 350 },
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xB0, 0, 0}, 0, 2, 355 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 357 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 359 },
+ { GAS_ILLEGAL|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 361 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xB8, 0xC7, 0}, 0, 2, 363 },
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xC6, 0, 0}, 0, 2, 365 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 367 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 369 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 371 },
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xC6, 0, 0}, 0, 2, 373 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 375 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 377 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 379 },
+ { SUF_L|SUF_Z, NOT_64, CPU_586, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, 381 },
+ { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, 383 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, 385 },
+ { SUF_L|SUF_Z, NOT_64, CPU_586, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, 387 },
+ { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, 382 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, 389 },
+ { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x23, 0}, 0, 2, 391 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x23, 0}, 0, 2, 393 },
+ { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x21, 0}, 0, 2, 392 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x21, 0}, 0, 2, 395 },
+ { GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x6F, 0}, 0, 2, 185 },
+ { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 247 },
+ { GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x7F, 0}, 0, 2, 283 },
+ { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 249 },
+ { GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2, 88 },
+ { GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2, 285 },
+ { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x6E, 0}, 0, 2, 253 },
+ { GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xD6, 0}, 0, 2, 287 },
+ { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x7E, 0}, 0, 2, 167 }
};
static const x86_insn_info movabs_insn[] = {
- { SUF_B, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 327 },
- { SUF_W, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 329 },
- { SUF_L, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 331 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 333 },
- { SUF_B, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 335 },
- { SUF_W, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 337 },
- { SUF_L, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 339 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 341 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 343 }
+ { SUF_B|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 293 },
+ { SUF_W|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 295 },
+ { SUF_L|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 297 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 299 },
+ { SUF_B|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 301 },
+ { SUF_W|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 303 },
+ { SUF_L|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 305 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 307 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 309 }
};
static const x86_insn_info movszx_insn[] = {
- { SUF_B, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 545 },
- { SUF_B, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 495 },
- { SUF_B, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 499 },
- { SUF_W, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 497 },
- { SUF_W, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 547 }
+ { SUF_B|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 535 },
+ { SUF_B|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 475 },
+ { SUF_B|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 479 },
+ { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 477 },
+ { SUF_W|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 537 }
};
static const x86_insn_info movsxd_insn[] = {
- { SUF_L, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x63, 0, 0}, 0, 2, 585 }
+ { SUF_L|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x63, 0, 0}, 0, 2, 571 }
};
static const x86_insn_info push_insn[] = {
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0x50, 0, 0}, 0, 1, 391 },
- { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x50, 0, 0}, 0, 1, 393 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0x50, 0, 0}, 0, 1, 343 },
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0xFF, 0, 0}, 6, 1, 273 },
- { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xFF, 0, 0}, 6, 1, 269 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0xFF, 0, 0}, 6, 1, 272 },
- { GAS_ILLEGAL, 0, CPU_186, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0x6A, 0, 0}, 0, 1, 152 },
- { GAS_ONLY, 0, CPU_186, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0x6A, 0, 0}, 0, 1, 637 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 1, {0x6A, 0x68, 0}, 0, 1, 164 },
- { GAS_ILLEGAL, NOT_64, CPU_186, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x6A, 0x68, 0}, 0, 1, 638 },
- { SUF_W, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0x6A, 0x68, 0}, 0, 1, 518 },
- { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x6A, 0x68, 0}, 0, 1, 520 },
- { GAS_ILLEGAL, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0x68, 0, 0}, 0, 1, 402 },
- { GAS_ILLEGAL, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x68, 0, 0}, 0, 1, 404 },
- { GAS_ILLEGAL, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 1, {0x68, 0, 0}, 0, 1, 639 },
- { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 640 },
- { SUF_W, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 641 },
- { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 642 },
- { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x16, 0, 0}, 0, 1, 595 },
- { SUF_W, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x16, 0, 0}, 0, 1, 596 },
- { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x16, 0, 0}, 0, 1, 597 },
- { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 598 },
- { SUF_W, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 599 },
- { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 600 },
- { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x06, 0, 0}, 0, 1, 601 },
- { SUF_W, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x06, 0, 0}, 0, 1, 602 },
- { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x06, 0, 0}, 0, 1, 603 },
- { 0, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 604 },
- { SUF_W, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 605 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 606 },
- { 0, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 607 },
- { SUF_W, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 608 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 609 }
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x50, 0, 0}, 0, 1, 357 },
+ { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x50, 0, 0}, 0, 1, 359 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x50, 0, 0}, 0, 1, 309 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xFF, 0, 0}, 6, 1, 239 },
+ { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 6, 1, 235 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 6, 1, 238 },
+ { GAS_ILLEGAL|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x6A, 0, 0}, 0, 1, 100 },
+ { GAS_ONLY|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x6A, 0, 0}, 0, 1, 624 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0x6A, 0x68, 0}, 0, 1, 112 },
+ { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_186, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x6A, 0x68, 0}, 0, 1, 625 },
+ { SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x6A, 0x68, 0}, 0, 1, 506 },
+ { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6A, 0x68, 0}, 0, 1, 508 },
+ { GAS_ILLEGAL|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x68, 0, 0}, 0, 1, 368 },
+ { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x68, 0, 0}, 0, 1, 370 },
+ { GAS_ILLEGAL|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0x68, 0, 0}, 0, 1, 626 },
+ { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 627 },
+ { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 628 },
+ { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 629 },
+ { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x16, 0, 0}, 0, 1, 581 },
+ { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x16, 0, 0}, 0, 1, 582 },
+ { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x16, 0, 0}, 0, 1, 583 },
+ { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 584 },
+ { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 585 },
+ { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 586 },
+ { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x06, 0, 0}, 0, 1, 587 },
+ { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x06, 0, 0}, 0, 1, 588 },
+ { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x06, 0, 0}, 0, 1, 589 },
+ { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 590 },
+ { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 591 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 592 },
+ { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 593 },
+ { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 594 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 595 }
};
static const x86_insn_info pop_insn[] = {
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0x58, 0, 0}, 0, 1, 391 },
- { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x58, 0, 0}, 0, 1, 393 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0x58, 0, 0}, 0, 1, 343 },
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0x8F, 0, 0}, 0, 1, 273 },
- { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x8F, 0, 0}, 0, 1, 269 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0x8F, 0, 0}, 0, 1, 272 },
- { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x17, 0, 0}, 0, 1, 595 },
- { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x17, 0, 0}, 0, 1, 596 },
- { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x17, 0, 0}, 0, 1, 597 },
- { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 598 },
- { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 599 },
- { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 600 },
- { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x07, 0, 0}, 0, 1, 601 },
- { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x07, 0, 0}, 0, 1, 602 },
- { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x07, 0, 0}, 0, 1, 603 },
- { 0, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 604 },
- { 0, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 605 },
- { 0, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 606 },
- { 0, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 607 },
- { 0, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 608 },
- { 0, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 609 }
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x58, 0, 0}, 0, 1, 357 },
+ { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x58, 0, 0}, 0, 1, 359 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x58, 0, 0}, 0, 1, 309 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x8F, 0, 0}, 0, 1, 239 },
+ { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8F, 0, 0}, 0, 1, 235 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x8F, 0, 0}, 0, 1, 238 },
+ { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x17, 0, 0}, 0, 1, 581 },
+ { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x17, 0, 0}, 0, 1, 582 },
+ { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x17, 0, 0}, 0, 1, 583 },
+ { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 584 },
+ { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 585 },
+ { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 586 },
+ { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x07, 0, 0}, 0, 1, 587 },
+ { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x07, 0, 0}, 0, 1, 588 },
+ { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x07, 0, 0}, 0, 1, 589 },
+ { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 590 },
+ { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 591 },
+ { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 592 },
+ { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 593 },
+ { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 594 },
+ { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 595 }
};
static const x86_insn_info xchg_insn[] = {
- { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x86, 0, 0}, 0, 2, 309 },
- { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x86, 0, 0}, 0, 2, 311 },
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, 473 },
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, 475 },
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x87, 0, 0}, 0, 2, 246 },
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x87, 0, 0}, 0, 2, 150 },
- { SUF_L, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x87, 0, 0}, 0, 2, 477 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, 479 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, 481 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x87, 0, 0}, 0, 2, 252 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x87, 0, 0}, 0, 2, 153 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, 483 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, 342 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, 485 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x87, 0, 0}, 0, 2, 258 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x87, 0, 0}, 0, 2, 156 }
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x86, 0, 0}, 0, 2, 275 },
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x86, 0, 0}, 0, 2, 277 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x90, 0, 0}, 0, 2, 455 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x90, 0, 0}, 0, 2, 457 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x87, 0, 0}, 0, 2, 212 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x87, 0, 0}, 0, 2, 98 },
+ { SUF_L|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x87, 0, 0}, 0, 2, 459 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x90, 0, 0}, 0, 2, 461 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x90, 0, 0}, 0, 2, 463 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x87, 0, 0}, 0, 2, 218 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x87, 0, 0}, 0, 2, 101 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, 465 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x90, 0, 0}, 0, 2, 308 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x90, 0, 0}, 0, 2, 467 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x87, 0, 0}, 0, 2, 224 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x87, 0, 0}, 0, 2, 104 }
};
static const x86_insn_info in_insn[] = {
- { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xE4, 0, 0}, 0, 2, 458 },
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xE5, 0, 0}, 0, 2, 460 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xE5, 0, 0}, 0, 2, 567 },
- { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xEC, 0, 0}, 0, 2, 464 },
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xED, 0, 0}, 0, 2, 466 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xED, 0, 0}, 0, 2, 462 },
- { GAS_ONLY|SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xE4, 0, 0}, 0, 1, 3 },
- { GAS_ONLY|SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xE5, 0, 0}, 0, 1, 3 },
- { GAS_ONLY|SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xE5, 0, 0}, 0, 1, 3 },
- { GAS_ONLY|SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xEC, 0, 0}, 0, 1, 463 },
- { GAS_ONLY|SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xED, 0, 0}, 0, 1, 463 },
- { GAS_ONLY|SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xED, 0, 0}, 0, 1, 463 }
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xE4, 0, 0}, 0, 2, 440 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xE5, 0, 0}, 0, 2, 442 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE5, 0, 0}, 0, 2, 545 },
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEC, 0, 0}, 0, 2, 446 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xED, 0, 0}, 0, 2, 448 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xED, 0, 0}, 0, 2, 444 },
+ { GAS_ONLY|SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xE4, 0, 0}, 0, 1, 3 },
+ { GAS_ONLY|SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xE5, 0, 0}, 0, 1, 3 },
+ { GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE5, 0, 0}, 0, 1, 3 },
+ { GAS_ONLY|SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEC, 0, 0}, 0, 1, 445 },
+ { GAS_ONLY|SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xED, 0, 0}, 0, 1, 445 },
+ { GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xED, 0, 0}, 0, 1, 445 }
};
static const x86_insn_info out_insn[] = {
- { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xE6, 0, 0}, 0, 2, 457 },
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xE7, 0, 0}, 0, 2, 459 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xE7, 0, 0}, 0, 2, 461 },
- { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xEE, 0, 0}, 0, 2, 463 },
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xEF, 0, 0}, 0, 2, 465 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xEF, 0, 0}, 0, 2, 467 },
- { GAS_ONLY|SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xE6, 0, 0}, 0, 1, 3 },
- { GAS_ONLY|SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xE7, 0, 0}, 0, 1, 3 },
- { GAS_ONLY|SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xE7, 0, 0}, 0, 1, 3 },
- { GAS_ONLY|SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xEE, 0, 0}, 0, 1, 463 },
- { GAS_ONLY|SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xEF, 0, 0}, 0, 1, 463 },
- { GAS_ONLY|SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xEF, 0, 0}, 0, 1, 463 }
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xE6, 0, 0}, 0, 2, 439 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xE7, 0, 0}, 0, 2, 441 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE7, 0, 0}, 0, 2, 443 },
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEE, 0, 0}, 0, 2, 445 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEF, 0, 0}, 0, 2, 447 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEF, 0, 0}, 0, 2, 449 },
+ { GAS_ONLY|SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xE6, 0, 0}, 0, 1, 3 },
+ { GAS_ONLY|SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xE7, 0, 0}, 0, 1, 3 },
+ { GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE7, 0, 0}, 0, 1, 3 },
+ { GAS_ONLY|SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEE, 0, 0}, 0, 1, 445 },
+ { GAS_ONLY|SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEF, 0, 0}, 0, 1, 445 },
+ { GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEF, 0, 0}, 0, 1, 445 }
};
static const x86_insn_info lea_insn[] = {
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 487 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 489 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 491 }
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 469 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 471 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 473 }
};
static const x86_insn_info ldes_insn[] = {
- { SUF_W, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 0, 1, {0x00, 0, 0}, 0, 2, 487 },
- { SUF_L, NOT_64, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 0, 1, {0x00, 0, 0}, 0, 2, 489 }
+ { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 1, {0x00, 0, 0}, 0, 2, 469 },
+ { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 1, {0x00, 0, 0}, 0, 2, 471 }
};
static const x86_insn_info lfgss_insn[] = {
- { SUF_W, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 487 },
- { SUF_L, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 489 }
+ { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 469 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 471 }
};
static const x86_insn_info arith_insn[] = {
- { SUF_B, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 0, 1, {0x04, 0, 0}, 0, 2, 458 },
- { SUF_W, 0, 0, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 16, 0, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, 517 },
- { SUF_L, 0, CPU_386, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 32, 0, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, 519 },
- { SUF_Q, ONLY_64, 0, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 64, 0, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, 521 },
- { SUF_B, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 0, 1, {0x80, 0, 0}, 0, 2, 407 },
- { SUF_B, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 0, 1, {0x80, 0, 0}, 0, 2, 399 },
- { SUF_W, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 0, 1, {0x83, 0, 0}, 0, 2, 523 },
- { GAS_ILLEGAL, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 525 },
- { SUF_W, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 527 },
- { SUF_L, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 0, 1, {0x83, 0, 0}, 0, 2, 529 },
- { GAS_ILLEGAL, NOT_64, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 531 },
- { SUF_L, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 533 },
- { SUF_Q, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 0, 1, {0x83, 0, 0}, 0, 2, 535 },
- { SUF_Q, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 537 },
- { SUF_B, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 0, 1, {0x00, 0, 0}, 0, 2, 309 },
- { SUF_W, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 0, 1, {0x01, 0, 0}, 0, 2, 246 },
- { SUF_L, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 0, 1, {0x01, 0, 0}, 0, 2, 252 },
- { SUF_Q, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 64, 0, 0, 0, 1, {0x01, 0, 0}, 0, 2, 258 },
- { SUF_B, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 0, 1, {0x02, 0, 0}, 0, 2, 311 },
- { SUF_W, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 0, 1, {0x03, 0, 0}, 0, 2, 150 },
- { SUF_L, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 0, 1, {0x03, 0, 0}, 0, 2, 153 },
- { SUF_Q, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 64, 0, 0, 0, 1, {0x03, 0, 0}, 0, 2, 156 }
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x04, 0, 0}, 0, 2, 440 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 16, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, 505 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 32, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, 507 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 64, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, 509 },
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0x80, 0, 0}, 0, 2, 373 },
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0x80, 0, 0}, 0, 2, 365 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 1, {0x83, 0, 0}, 0, 2, 511 },
+ { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 513 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 515 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 1, {0x83, 0, 0}, 0, 2, 517 },
+ { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 519 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 521 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 1, {0x83, 0, 0}, 0, 2, 523 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 525 },
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 2, 275 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 1, {0x01, 0, 0}, 0, 2, 212 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 1, {0x01, 0, 0}, 0, 2, 218 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 64, 0, 0, 1, {0x01, 0, 0}, 0, 2, 224 },
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x02, 0, 0}, 0, 2, 277 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 1, {0x03, 0, 0}, 0, 2, 98 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 1, {0x03, 0, 0}, 0, 2, 101 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 64, 0, 0, 1, {0x03, 0, 0}, 0, 2, 104 }
};
static const x86_insn_info incdec_insn[] = {
- { SUF_B, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 0, 1, {0xFE, 0, 0}, 0, 1, 407 },
- { SUF_W, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 391 },
- { SUF_W, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 273 },
- { SUF_L, NOT_64, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 393 },
- { SUF_L, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 269 },
- { SUF_Q, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 272 }
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0xFE, 0, 0}, 0, 1, 373 },
+ { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 1, {0x00, 0, 0}, 0, 1, 357 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 239 },
+ { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 1, {0x00, 0, 0}, 0, 1, 359 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 235 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 238 }
};
static const x86_insn_info f6_insn[] = {
- { SUF_B, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 1, 407 },
- { SUF_W, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 273 },
- { SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 269 },
- { SUF_Q, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 272 }
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 1, 373 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 239 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 235 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 238 }
};
static const x86_insn_info div_insn[] = {
- { SUF_B, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 1, 407 },
- { SUF_W, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 273 },
- { SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 269 },
- { SUF_Q, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 272 },
- { SUF_B, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 443 },
- { SUF_W, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 445 },
- { SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 447 },
- { SUF_Q, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 449 }
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 1, 373 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 239 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 235 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 238 },
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 411 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 413 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 415 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 417 }
};
static const x86_insn_info test_insn[] = {
- { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xA8, 0, 0}, 0, 2, 458 },
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 573 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 575 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 577 },
- { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 407 },
- { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 399 },
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 409 },
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 401 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 411 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 403 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 413 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 405 },
- { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x84, 0, 0}, 0, 2, 309 },
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x85, 0, 0}, 0, 2, 246 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x85, 0, 0}, 0, 2, 252 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x85, 0, 0}, 0, 2, 258 },
- { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x84, 0, 0}, 0, 2, 311 },
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x85, 0, 0}, 0, 2, 150 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x85, 0, 0}, 0, 2, 153 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x85, 0, 0}, 0, 2, 156 }
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA8, 0, 0}, 0, 2, 440 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 555 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 557 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 559 },
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 373 },
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 365 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 375 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 367 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 377 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 369 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 379 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 371 },
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x84, 0, 0}, 0, 2, 275 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x85, 0, 0}, 0, 2, 212 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x85, 0, 0}, 0, 2, 218 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x85, 0, 0}, 0, 2, 224 },
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x84, 0, 0}, 0, 2, 277 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x85, 0, 0}, 0, 2, 98 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x85, 0, 0}, 0, 2, 101 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x85, 0, 0}, 0, 2, 104 }
};
static const x86_insn_info aadm_insn[] = {
- { 0, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 0, 2, {0xD4, 0x0A, 0}, 0, 0, 0 },
- { 0, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 0, 1, {0xD4, 0, 0}, 0, 1, 3 }
+ { SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 2, {0xD4, 0x0A, 0}, 0, 0, 0 },
+ { SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0xD4, 0, 0}, 0, 1, 3 }
};
static const x86_insn_info imul_insn[] = {
- { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xF6, 0, 0}, 5, 1, 407 },
- { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 273 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 269 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 272 },
- { SUF_W, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, 150 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, 153 },
- { SUF_Q, ONLY_64, CPU_386, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, 156 },
- { SUF_W, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x6B, 0, 0}, 0, 3, 150 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x6B, 0, 0}, 0, 3, 153 },
- { SUF_Q, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x6B, 0, 0}, 0, 3, 156 },
- { SUF_W, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 289 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 291 },
- { SUF_Q, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 293 },
- { SUF_W, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, 159 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, 162 },
- { SUF_Q, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, 165 },
- { SUF_W, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 295 },
- { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 297 },
- { SUF_Q, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 299 }
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 5, 1, 373 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 239 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 235 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 238 },
+ { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, 98 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, 101 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, 104 },
+ { SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x6B, 0, 0}, 0, 3, 98 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6B, 0, 0}, 0, 3, 101 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x6B, 0, 0}, 0, 3, 104 },
+ { SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 255 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 257 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 259 },
+ { SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, 107 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, 110 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, 113 },
+ { SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 261 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 263 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 265 }
};
static const x86_insn_info shift_insn[] = {
- { SUF_B, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xD2, 0, 0}, 0, 2, 501 },
- { SUF_B, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xD0, 0, 0}, 0, 2, 503 },
- { SUF_B, 0, CPU_186, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xC0, 0, 0}, 0, 2, 407 },
- { SUF_W, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 0, 1, {0xD3, 0, 0}, 0, 2, 505 },
- { SUF_W, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 0, 1, {0xD1, 0, 0}, 0, 2, 507 },
- { SUF_W, 0, CPU_186, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 0, 1, {0xC1, 0, 0}, 0, 2, 273 },
- { SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 0, 1, {0xD3, 0, 0}, 0, 2, 509 },
- { SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 0, 1, {0xD1, 0, 0}, 0, 2, 511 },
- { SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 0, 1, {0xC1, 0, 0}, 0, 2, 275 },
- { SUF_Q, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 0, 1, {0xD3, 0, 0}, 0, 2, 513 },
- { SUF_Q, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 0, 1, {0xD1, 0, 0}, 0, 2, 515 },
- { SUF_Q, ONLY_64, CPU_186, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 0, 1, {0xC1, 0, 0}, 0, 2, 277 },
- { GAS_ONLY|SUF_B, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xD0, 0, 0}, 0, 1, 407 },
- { GAS_ONLY|SUF_W, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 0, 1, {0xD1, 0, 0}, 0, 1, 273 },
- { GAS_ONLY|SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 0, 1, {0xD1, 0, 0}, 0, 1, 269 },
- { GAS_ONLY|SUF_Q, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 0, 1, {0xD1, 0, 0}, 0, 1, 272 }
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xD2, 0, 0}, 0, 2, 481 },
+ { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xD0, 0, 0}, 0, 2, 483 },
+ { SUF_B|SUF_Z, 0, CPU_186, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xC0, 0, 0}, 0, 2, 373 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xD3, 0, 0}, 0, 2, 485 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xD1, 0, 0}, 0, 2, 487 },
+ { SUF_W|SUF_Z, 0, CPU_186, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xC1, 0, 0}, 0, 2, 239 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xD3, 0, 0}, 0, 2, 489 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xD1, 0, 0}, 0, 2, 491 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xC1, 0, 0}, 0, 2, 241 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xD3, 0, 0}, 0, 2, 493 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xD1, 0, 0}, 0, 2, 495 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xC1, 0, 0}, 0, 2, 243 },
+ { GAS_ONLY|SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xD0, 0, 0}, 0, 1, 373 },
+ { GAS_ONLY|SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xD1, 0, 0}, 0, 1, 239 },
+ { GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xD1, 0, 0}, 0, 1, 235 },
+ { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xD1, 0, 0}, 0, 1, 238 }
};
static const x86_insn_info shlrd_insn[] = {
- { SUF_W, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 246 },
- { SUF_W, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 3, 249 },
- { SUF_L, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 252 },
- { SUF_L, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 3, 255 },
- { SUF_Q, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 258 },
- { SUF_Q, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 3, 261 },
- { GAS_ONLY|SUF_W, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 246 },
- { GAS_ONLY|SUF_L, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 252 },
- { GAS_ONLY|SUF_Q, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 258 }
+ { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 212 },
+ { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x01, 0}, 0, 3, 215 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 218 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x01, 0}, 0, 3, 221 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 224 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x01, 0}, 0, 3, 227 },
+ { GAS_ONLY|SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 212 },
+ { GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 218 },
+ { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 224 }
};
static const x86_insn_info call_insn[] = {
- { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 612 },
- { 0, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 613 },
- { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 614 },
- { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 614 },
- { 0, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0xE8, 0, 0}, 0, 1, 615 },
- { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xE8, 0, 0}, 0, 1, 616 },
- { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 1, {0xE8, 0, 0}, 0, 1, 616 },
- { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0xE8, 0, 0}, 0, 1, 617 },
- { 0, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 273 },
- { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 269 },
- { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 272 },
- { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 611 },
- { 0, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 618 },
- { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 619 },
- { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 620 },
- { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 621 },
- { 0, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 622 },
- { 0, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 623 },
- { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 624 },
- { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 625 },
- { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x9A, 0, 0}, 3, 1, 626 },
- { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x9A, 0, 0}, 3, 1, 627 },
- { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x9A, 0, 0}, 3, 1, 628 },
- { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x9A, 0, 0}, 3, 1, 629 },
- { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x9A, 0, 0}, 3, 1, 630 },
- { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x9A, 0, 0}, 3, 1, 631 }
+ { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 597 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, {0, 0, 0}, 0, 1, 598 },
+ { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, {0, 0, 0}, 0, 1, 599 },
+ { SUF_L|SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, {0, 0, 0}, 0, 1, 599 },
+ { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xE8, 0, 0}, 0, 1, 600 },
+ { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE8, 0, 0}, 0, 1, 601 },
+ { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xE8, 0, 0}, 0, 1, 601 },
+ { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xE8, 0, 0}, 0, 1, 602 },
+ { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 239 },
+ { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 235 },
+ { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 238 },
+ { GAS_ONLY|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 603 },
+ { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 596 },
+ { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 604 },
+ { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 605 },
+ { GAS_ILLEGAL|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 606 },
+ { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 607 },
+ { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 608 },
+ { GAS_ILLEGAL|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 609 },
+ { GAS_ILLEGAL|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 610 },
+ { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 611 },
+ { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x9A, 0, 0}, 0, 1, 612 },
+ { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x9A, 0, 0}, 0, 1, 613 },
+ { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x9A, 0, 0}, 0, 1, 614 },
+ { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x9A, 0, 0}, 0, 1, 615 },
+ { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x9A, 0, 0}, 0, 1, 616 },
+ { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x9A, 0, 0}, 0, 1, 617 },
+ { GAS_ONLY|GAS_NO_REV|SUF_W, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x9A, 0, 0}, 0, 2, 499 },
+ { GAS_ONLY|GAS_NO_REV|SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x9A, 0, 0}, 0, 2, 501 },
+ { GAS_ONLY|GAS_NO_REV|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x9A, 0, 0}, 0, 2, 503 }
};
static const x86_insn_info jmp_insn[] = {
- { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 612 },
- { 0, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 613 },
- { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 614 },
- { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 614 },
- { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0xEB, 0, 0}, 0, 1, 559 },
- { 0, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0xE9, 0, 0}, 0, 1, 615 },
- { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xE9, 0, 0}, 0, 1, 616 },
- { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 1, {0xE9, 0, 0}, 0, 1, 616 },
- { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0xE9, 0, 0}, 0, 1, 617 },
- { 0, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 273 },
- { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 269 },
- { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 272 },
- { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 611 },
- { 0, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 618 },
- { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 619 },
- { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 620 },
- { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 621 },
- { 0, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 622 },
- { 0, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 623 },
- { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 624 },
- { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 625 },
- { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xEA, 0, 0}, 3, 1, 626 },
- { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xEA, 0, 0}, 3, 1, 627 },
- { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xEA, 0, 0}, 3, 1, 628 },
- { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xEA, 0, 0}, 3, 1, 629 },
- { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xEA, 0, 0}, 3, 1, 630 },
- { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xEA, 0, 0}, 3, 1, 631 }
+ { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 597 },
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, {0, 0, 0}, 0, 1, 598 },
+ { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x00, 0, 0}, 0, 1, 599 },
+ { SUF_L|SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x00, 0, 0}, 0, 1, 599 },
+ { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xEB, 0, 0}, 0, 1, 421 },
+ { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xE9, 0, 0}, 0, 1, 600 },
+ { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE9, 0, 0}, 0, 1, 601 },
+ { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xE9, 0, 0}, 0, 1, 601 },
+ { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xE9, 0, 0}, 0, 1, 602 },
+ { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 239 },
+ { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 235 },
+ { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 238 },
+ { GAS_ONLY|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 603 },
+ { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 596 },
+ { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 604 },
+ { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 605 },
+ { GAS_ILLEGAL|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 606 },
+ { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 607 },
+ { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 608 },
+ { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 609 },
+ { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 610 },
+ { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 611 },
+ { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEA, 0, 0}, 0, 1, 612 },
+ { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEA, 0, 0}, 0, 1, 613 },
+ { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEA, 0, 0}, 0, 1, 614 },
+ { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEA, 0, 0}, 0, 1, 615 },
+ { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEA, 0, 0}, 0, 1, 616 },
+ { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEA, 0, 0}, 0, 1, 617 },
+ { GAS_ONLY|GAS_NO_REV|SUF_W, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEA, 0, 0}, 0, 2, 499 },
+ { GAS_ONLY|GAS_NO_REV|SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEA, 0, 0}, 0, 2, 501 },
+ { GAS_ONLY|GAS_NO_REV|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEA, 0, 0}, 0, 2, 503 }
};
+static const x86_insn_info ljmpcall_insn[] = {
+ { SUF_W, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 22 },
+ { SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 50 },
+ { SUF_Q, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 6 },
+ { SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 621 },
+ { GAS_NO_REV|SUF_W, NOT_64, 0, 0, 0, {MOD_Gap, MOD_Op0Add, 0}, 16, 0, 0, 1, {0x00, 0, 0}, 0, 2, 499 },
+ { GAS_NO_REV|SUF_L, NOT_64, CPU_386, 0, 0, {MOD_Gap, MOD_Op0Add, 0}, 32, 0, 0, 1, {0x00, 0, 0}, 0, 2, 501 },
+ { GAS_NO_REV|SUF_Z, NOT_64, 0, 0, 0, {MOD_Gap, MOD_Op0Add, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 2, 503 }
+};
+
static const x86_insn_info retnf_insn[] = {
- { 0, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 0, 1, {0x01, 0, 0}, 0, 0, 0 },
- { 0, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 392 },
- { 0, ONLY_64, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 0, 1, {0x01, 0, 0}, 0, 0, 0 },
- { 0, ONLY_64, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 392 },
- { SUF_L|SUF_Q|SUF_W, 0, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 0, 1, {0x01, 0, 0}, 0, 0, 0 },
- { SUF_L|SUF_Q|SUF_W, 0, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 392 }
+ { SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x01, 0, 0}, 0, 0, 0 },
+ { SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 358 },
+ { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 1, {0x01, 0, 0}, 0, 0, 0 },
+ { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 358 },
+ { SUF_L|SUF_Q|SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 1, {0x01, 0, 0}, 0, 0, 0 },
+ { SUF_L|SUF_Q|SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 358 }
};
static const x86_insn_info enter_insn[] = {
- { GAS_NO_REV|SUF_L, NOT_64, CPU_186, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xC8, 0, 0}, 0, 2, 583 },
- { GAS_NO_REV|SUF_Q, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 1, {0xC8, 0, 0}, 0, 2, 583 },
- { GAS_ONLY|GAS_NO_REV|SUF_W, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xC8, 0, 0}, 0, 2, 583 }
+ { GAS_NO_REV|SUF_L|SUF_Z, NOT_64, CPU_186, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xC8, 0, 0}, 0, 2, 569 },
+ { GAS_NO_REV|SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xC8, 0, 0}, 0, 2, 569 },
+ { GAS_ONLY|GAS_NO_REV|SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xC8, 0, 0}, 0, 2, 569 }
};
static const x86_insn_info jcc_insn[] = {
- { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 553 },
- { 0, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 635 },
- { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 636 },
- { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 636 },
- { 0, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 0, 1, {0x70, 0, 0}, 0, 1, 559 },
- { 0, 0, CPU_186, 0, 0, {MOD_Op1Add, 0, 0}, 16, 64, 0, 0, 2, {0x0F, 0x80, 0}, 0, 1, 615 },
- { 0, NOT_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x80, 0}, 0, 1, 616 },
- { 0, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 64, 0, 0, 2, {0x0F, 0x80, 0}, 0, 1, 616 },
- { 0, 0, CPU_186, 0, 0, {MOD_Op1Add, 0, 0}, 0, 64, 0, 0, 2, {0x0F, 0x80, 0}, 0, 1, 617 }
+ { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 419 },
+ { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, {0, 0, 0}, 0, 1, 622 },
+ { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, {0, 0, 0}, 0, 1, 623 },
+ { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, {0, 0, 0}, 0, 1, 623 },
+ { SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0x70, 0, 0}, 0, 1, 421 },
+ { SUF_Z, 0, CPU_186, 0, 0, {MOD_Op1Add, 0, 0}, 16, 64, 0, 2, {0x0F, 0x80, 0}, 0, 1, 600 },
+ { SUF_Z, NOT_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x80, 0}, 0, 1, 601 },
+ { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 64, 0, 2, {0x0F, 0x80, 0}, 0, 1, 601 },
+ { SUF_Z, 0, CPU_186, 0, 0, {MOD_Op1Add, 0, 0}, 0, 64, 0, 2, {0x0F, 0x80, 0}, 0, 1, 602 }
};
static const x86_insn_info jcxz_insn[] = {
- { 0, 0, 0, 0, 0, {MOD_AdSizeR, 0, 0}, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 553 },
- { 0, 0, 0, 0, 0, {MOD_AdSizeR, 0, 0}, 0, 64, 0, 0, 1, {0xE3, 0, 0}, 0, 1, 559 }
+ { SUF_Z, 0, 0, 0, 0, {MOD_AdSizeR, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 419 },
+ { SUF_Z, 0, 0, 0, 0, {MOD_AdSizeR, 0, 0}, 0, 64, 0, 1, {0xE3, 0, 0}, 0, 1, 421 }
};
static const x86_insn_info loop_insn[] = {
- { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 553 },
- { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 2, 553 },
- { 0, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 0, {0, 0, 0}, 0, 2, 555 },
- { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 0, {0, 0, 0}, 0, 2, 557 },
- { 0, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 0, 1, {0xE0, 0, 0}, 0, 1, 559 },
- { 0, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 0, 1, {0xE0, 0, 0}, 0, 2, 559 },
- { 0, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 0, 1, {0xE0, 0, 0}, 0, 2, 561 },
- { 0, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 0, 1, {0xE0, 0, 0}, 0, 2, 563 }
+ { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 419 },
+ { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 2, 433 },
+ { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 2, 419 },
+ { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 2, 429 },
+ { SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0xE0, 0, 0}, 0, 1, 421 },
+ { SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 435 },
+ { SUF_Z, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 421 },
+ { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 431 }
};
+static const x86_insn_info loopw_insn[] = {
+ { SUF_Z, NOT_64, 0, 0, 0, {MOD_Gap, MOD_AdSizeR, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 1, 419 },
+ { SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, MOD_AdSizeR, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 1, 421 },
+ { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 2, 433 },
+ { SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 435 }
+};
+
+static const x86_insn_info loopl_insn[] = {
+ { SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_AdSizeR, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 1, 419 },
+ { SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, MOD_AdSizeR, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 1, 421 },
+ { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 2, 419 },
+ { SUF_Z, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 421 }
+};
+
+static const x86_insn_info loopq_insn[] = {
+ { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_AdSizeR, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 1, 419 },
+ { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, MOD_AdSizeR, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 1, 421 },
+ { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 2, 429 },
+ { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 431 }
+};
+
static const x86_insn_info setcc_insn[] = {
- { SUF_B, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x90, 0}, 2, 1, 309 }
+ { SUF_B|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x90, 0}, 2, 1, 275 }
};
static const x86_insn_info cmpsd_insn[] = {
- { GAS_ILLEGAL, NOT_AVX, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xA7, 0, 0}, 0, 0, 0 },
- { 0, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0xC2, 0}, 0, 3, 144 },
- { 0, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0xC2, 0}, 0, 3, 147 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC3, 0, 2, {0x0F, 0xC2, 0}, 0, 4, 0 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC3, 0, 2, {0x0F, 0xC2, 0}, 0, 4, 4 }
+ { GAS_ILLEGAL|SUF_Z, NOT_AVX, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA7, 0, 0}, 0, 0, 0 },
+ { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0xC2, 0}, 0, 3, 92 },
+ { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0xC2, 0}, 0, 3, 95 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC3, 2, {0x0F, 0xC2, 0}, 0, 4, 0 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC3, 2, {0x0F, 0xC2, 0}, 0, 4, 4 }
};
static const x86_insn_info movsd_insn[] = {
- { 0, NOT_AVX, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xA5, 0, 0}, 0, 0, 0 },
- { 0, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0x10, 0}, 0, 2, 144 },
- { 0, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0x10, 0}, 0, 2, 73 },
- { 0, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0x11, 0}, 0, 2, 106 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC3, 0, 2, {0x0F, 0x10, 0}, 0, 3, 0 }
+ { SUF_Z, NOT_AVX, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA5, 0, 0}, 0, 0, 0 },
+ { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x10, 0}, 0, 2, 92 },
+ { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x10, 0}, 0, 2, 401 },
+ { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x11, 0}, 0, 2, 39 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC3, 2, {0x0F, 0x10, 0}, 0, 3, 0 }
};
static const x86_insn_info bittest_insn[] = {
- { SUF_W, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 246 },
- { SUF_L, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 252 },
- { SUF_Q, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 258 },
- { SUF_W, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 0, 2, {0x0F, 0xBA, 0}, 0, 2, 273 },
- { SUF_L, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 0, 2, {0x0F, 0xBA, 0}, 0, 2, 275 },
- { SUF_Q, ONLY_64, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 0, 2, {0x0F, 0xBA, 0}, 0, 2, 277 }
+ { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 212 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 218 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 224 },
+ { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 2, {0x0F, 0xBA, 0}, 0, 2, 239 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 2, {0x0F, 0xBA, 0}, 0, 2, 241 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 2, {0x0F, 0xBA, 0}, 0, 2, 243 }
};
static const x86_insn_info bsfr_insn[] = {
- { SUF_W, 0, 0, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 150 },
- { SUF_L, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 153 },
- { SUF_Q, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 156 }
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 98 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 101 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 104 }
};
static const x86_insn_info int_insn[] = {
- { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xCD, 0, 0}, 0, 1, 3 }
+ { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xCD, 0, 0}, 0, 1, 3 }
};
static const x86_insn_info bound_insn[] = {
- { SUF_W, NOT_64, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x62, 0, 0}, 0, 2, 437 },
- { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x62, 0, 0}, 0, 2, 345 }
+ { SUF_W|SUF_Z, NOT_64, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x62, 0, 0}, 0, 2, 405 },
+ { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x62, 0, 0}, 0, 2, 311 }
};
static const x86_insn_info arpl_insn[] = {
- { SUF_W, NOT_64, CPU_286, CPU_Prot, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x63, 0, 0}, 0, 2, 246 }
+ { SUF_W|SUF_Z, NOT_64, CPU_286, CPU_Prot, 0, {0, 0, 0}, 0, 0, 0, 1, {0x63, 0, 0}, 0, 2, 212 }
};
static const x86_insn_info str_insn[] = {
- { SUF_W, 0, CPU_286, CPU_Prot, 0, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 381 },
- { SUF_L, 0, CPU_386, CPU_Prot, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 14 },
- { SUF_Q, ONLY_64, CPU_286, CPU_Prot, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 18 },
- { SUF_L|SUF_W, 0, CPU_286, CPU_Prot, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 151 }
+ { SUF_W|SUF_Z, 0, CPU_286, CPU_Prot, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 347 },
+ { SUF_L|SUF_Z, 0, CPU_386, CPU_Prot, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 14 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_286, CPU_Prot, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 18 },
+ { SUF_L|SUF_W|SUF_Z, 0, CPU_286, CPU_Prot, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 99 }
};
static const x86_insn_info prot286_insn[] = {
- { SUF_W, 0, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 151 }
+ { SUF_W|SUF_Z, 0, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 99 }
};
static const x86_insn_info sldtmsw_insn[] = {
- { SUF_W, 0, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 22 },
- { SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 38 },
- { SUF_Q, ONLY_64, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 6 },
- { SUF_W, 0, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 16, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 381 },
- { SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 32, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 14 },
- { SUF_Q, ONLY_64, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 64, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 18 }
+ { SUF_W|SUF_Z, 0, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 22 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 50 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 6 },
+ { SUF_W|SUF_Z, 0, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 347 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 14 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 18 }
};
static const x86_insn_info fld_insn[] = {
- { SUF_S, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xD9, 0, 0}, 0, 1, 593 },
- { SUF_L, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xDD, 0, 0}, 0, 1, 594 },
- { 0, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xDB, 0, 0}, 5, 1, 591 },
- { 0, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0xD9, 0xC0, 0}, 0, 1, 314 }
+ { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xD9, 0, 0}, 0, 1, 578 },
+ { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDD, 0, 0}, 0, 1, 197 },
+ { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDB, 0, 0}, 5, 1, 580 },
+ { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC0, 0}, 0, 1, 280 }
};
static const x86_insn_info fstp_insn[] = {
- { SUF_S, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xD9, 0, 0}, 3, 1, 593 },
- { SUF_L, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xDD, 0, 0}, 3, 1, 594 },
- { 0, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xDB, 0, 0}, 7, 1, 591 },
- { 0, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0xDD, 0xD8, 0}, 0, 1, 314 }
+ { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xD9, 0, 0}, 3, 1, 578 },
+ { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDD, 0, 0}, 3, 1, 197 },
+ { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDB, 0, 0}, 7, 1, 580 },
+ { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xDD, 0xD8, 0}, 0, 1, 280 }
};
static const x86_insn_info fldstpt_insn[] = {
- { 0, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xDB, 0, 0}, 0, 1, 591 }
+ { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDB, 0, 0}, 0, 1, 498 }
};
static const x86_insn_info fildstp_insn[] = {
- { SUF_S, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xDF, 0, 0}, 0, 1, 592 },
- { SUF_L, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xDB, 0, 0}, 0, 1, 593 },
- { SUF_Q, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op0Add, MOD_SpAdd}, 0, 0, 0, 0, 1, {0xDD, 0, 0}, 0, 1, 594 },
- { GAS_ONLY, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xDF, 0, 0}, 0, 1, 22 }
+ { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDF, 0, 0}, 0, 1, 577 },
+ { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDB, 0, 0}, 0, 1, 578 },
+ { SUF_Q|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op0Add, MOD_SpAdd}, 0, 0, 0, 1, {0xDD, 0, 0}, 0, 1, 197 },
+ { GAS_ONLY|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDF, 0, 0}, 0, 1, 22 }
};
static const x86_insn_info fbldstp_insn[] = {
- { 0, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xDF, 0, 0}, 0, 1, 494 }
+ { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDF, 0, 0}, 0, 1, 498 }
};
static const x86_insn_info fst_insn[] = {
- { SUF_S, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xD9, 0, 0}, 2, 1, 593 },
- { SUF_L, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xDD, 0, 0}, 2, 1, 594 },
- { 0, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0xDD, 0xD0, 0}, 0, 1, 314 }
+ { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xD9, 0, 0}, 2, 1, 578 },
+ { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDD, 0, 0}, 2, 1, 197 },
+ { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xDD, 0xD0, 0}, 0, 1, 280 }
};
static const x86_insn_info fxch_insn[] = {
- { 0, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 1, 314 },
- { 0, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 2, 313 },
- { 0, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 2, 315 },
- { 0, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0xD9, 0xC9, 0}, 0, 0, 0 }
+ { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 1, 280 },
+ { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 2, 279 },
+ { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 2, 281 },
+ { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC9, 0}, 0, 0, 0 }
};
static const x86_insn_info fcom_insn[] = {
- { SUF_S, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 0, 1, {0xD8, 0, 0}, 0, 1, 593 },
- { SUF_L, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 0, 1, {0xDC, 0, 0}, 0, 1, 594 },
- { 0, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 1, 314 },
- { GAS_ONLY, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 0, 1, {0xD8, 0, 0}, 0, 1, 38 },
- { GAS_ONLY, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0xD8, 0x01, 0}, 0, 0, 0 },
- { GAS_ILLEGAL, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 2, 313 }
+ { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0xD8, 0, 0}, 0, 1, 578 },
+ { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0xDC, 0, 0}, 0, 1, 197 },
+ { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 1, 280 },
+ { GAS_ONLY|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0xD8, 0, 0}, 0, 1, 50 },
+ { GAS_ONLY|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xD8, 0x01, 0}, 0, 0, 0 },
+ { GAS_ILLEGAL|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 2, 279 }
};
static const x86_insn_info fcom2_insn[] = {
- { 0, 0, CPU_286, CPU_FPU, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 1, 314 },
- { 0, 0, CPU_286, CPU_FPU, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 2, 313 }
+ { SUF_Z, 0, CPU_286, CPU_FPU, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 1, 280 },
+ { SUF_Z, 0, CPU_286, CPU_FPU, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 2, 279 }
};
static const x86_insn_info farith_insn[] = {
- { SUF_S, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Gap, MOD_SpAdd}, 0, 0, 0, 0, 1, {0xD8, 0, 0}, 0, 1, 593 },
- { SUF_L, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Gap, MOD_SpAdd}, 0, 0, 0, 0, 1, {0xDC, 0, 0}, 0, 1, 594 },
- { 0, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 1, 314 },
- { 0, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 2, 313 },
- { 0, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0xDC, 0x00, 0}, 0, 1, 632 },
- { GAS_ILLEGAL, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0xDC, 0x00, 0}, 0, 2, 315 },
- { GAS_ONLY, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0xDC, 0x00, 0}, 0, 2, 315 }
+ { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Gap, MOD_SpAdd}, 0, 0, 0, 1, {0xD8, 0, 0}, 0, 1, 578 },
+ { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Gap, MOD_SpAdd}, 0, 0, 0, 1, {0xDC, 0, 0}, 0, 1, 197 },
+ { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op1Add, 0}, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 1, 280 },
+ { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op1Add, 0}, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 2, 279 },
+ { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDC, 0x00, 0}, 0, 1, 618 },
+ { GAS_ILLEGAL|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDC, 0x00, 0}, 0, 2, 281 },
+ { GAS_ONLY|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op1Add, 0}, 0, 0, 0, 2, {0xDC, 0x00, 0}, 0, 2, 281 }
};
static const x86_insn_info farithp_insn[] = {
- { 0, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0xDE, 0x01, 0}, 0, 0, 0 },
- { 0, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0xDE, 0x00, 0}, 0, 1, 314 },
- { 0, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0xDE, 0x00, 0}, 0, 2, 315 }
+ { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDE, 0x01, 0}, 0, 0, 0 },
+ { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDE, 0x00, 0}, 0, 1, 280 },
+ { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDE, 0x00, 0}, 0, 2, 281 }
};
static const x86_insn_info fiarith_insn[] = {
- { SUF_S, 0, CPU_FPU, 0, 0, {MOD_SpAdd, MOD_Op0Add, 0}, 0, 0, 0, 0, 1, {0x04, 0, 0}, 0, 1, 592 },
- { SUF_L, 0, CPU_FPU, 0, 0, {MOD_SpAdd, MOD_Op0Add, 0}, 0, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 593 }
+ { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, MOD_Op0Add, 0}, 0, 0, 0, 1, {0x04, 0, 0}, 0, 1, 577 },
+ { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, MOD_Op0Add, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 578 }
};
static const x86_insn_info fldnstcw_insn[] = {
- { SUF_W, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xD9, 0, 0}, 0, 1, 22 }
+ { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xD9, 0, 0}, 0, 1, 22 }
};
static const x86_insn_info fstcw_insn[] = {
- { SUF_W, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x9B, 0xD9, 0}, 7, 1, 22 }
+ { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x9B, 0xD9, 0}, 7, 1, 22 }
};
static const x86_insn_info fnstsw_insn[] = {
- { SUF_W, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xDD, 0, 0}, 7, 1, 22 },
- { SUF_W, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0xDF, 0xE0, 0}, 0, 1, 329 }
+ { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDD, 0, 0}, 7, 1, 22 },
+ { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xDF, 0xE0, 0}, 0, 1, 295 }
};
static const x86_insn_info fstsw_insn[] = {
- { SUF_W, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x9B, 0xDD, 0}, 7, 1, 22 },
- { SUF_W, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 3, {0x9B, 0xDF, 0xE0}, 0, 1, 329 }
+ { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x9B, 0xDD, 0}, 7, 1, 22 },
+ { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 3, {0x9B, 0xDF, 0xE0}, 0, 1, 295 }
};
static const x86_insn_info ffree_insn[] = {
- { 0, 0, CPU_FPU, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 0, 2, {0x00, 0xC0, 0}, 0, 1, 314 }
+ { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 2, {0x00, 0xC0, 0}, 0, 1, 280 }
};
static const x86_insn_info bswap_insn[] = {
- { SUF_L, 0, CPU_486, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0xC8, 0}, 0, 1, 633 },
- { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0xC8, 0}, 0, 1, 634 }
+ { SUF_L|SUF_Z, 0, CPU_486, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xC8, 0}, 0, 1, 619 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC8, 0}, 0, 1, 620 }
};
static const x86_insn_info cmpxchgxadd_insn[] = {
- { SUF_B, 0, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 309 },
- { SUF_W, 0, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 246 },
- { SUF_L, 0, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 252 },
- { SUF_Q, ONLY_64, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 258 }
+ { SUF_B|SUF_Z, 0, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 275 },
+ { SUF_W|SUF_Z, 0, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 212 },
+ { SUF_L|SUF_Z, 0, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 218 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 224 }
};
static const x86_insn_info cmpxchg8b_insn[] = {
- { SUF_Q, 0, CPU_586, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xC7, 0}, 1, 1, 6 }
+ { SUF_Q|SUF_Z, 0, CPU_586, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xC7, 0}, 1, 1, 6 }
};
static const x86_insn_info cmovcc_insn[] = {
- { SUF_W, 0, CPU_686, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x40, 0}, 0, 2, 150 },
- { SUF_L, 0, CPU_686, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x40, 0}, 0, 2, 153 },
- { SUF_Q, ONLY_64, CPU_686, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x40, 0}, 0, 2, 156 }
+ { SUF_W|SUF_Z, 0, CPU_686, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x40, 0}, 0, 2, 98 },
+ { SUF_L|SUF_Z, 0, CPU_686, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x40, 0}, 0, 2, 101 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_686, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x40, 0}, 0, 2, 104 }
};
static const x86_insn_info fcmovcc_insn[] = {
- { 0, 0, CPU_686, CPU_FPU, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 2, 313 }
+ { SUF_Z, 0, CPU_686, CPU_FPU, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 2, 279 }
};
static const x86_insn_info movnti_insn[] = {
- { SUF_L, 0, CPU_P4, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xC3, 0}, 0, 2, 323 },
- { SUF_Q, ONLY_64, CPU_P4, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0xC3, 0}, 0, 2, 325 }
+ { SUF_L|SUF_Z, 0, CPU_P4, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xC3, 0}, 0, 2, 289 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_P4, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC3, 0}, 0, 2, 291 }
};
static const x86_insn_info clflush_insn[] = {
- { 0, 0, CPU_P3, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xAE, 0}, 7, 1, 30 }
+ { SUF_Z, 0, CPU_P3, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xAE, 0}, 7, 1, 42 }
};
static const x86_insn_info movd_insn[] = {
- { 0, 0, CPU_386, CPU_MMX, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 279 },
- { 0, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 281 },
- { 0, 0, CPU_386, CPU_MMX, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 280 },
- { 0, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 283 },
- { 0, 0, CPU_386, CPU_SSE2, 0, {0, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 285 },
- { 0, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 287 },
- { 0, 0, CPU_386, CPU_SSE2, 0, {0, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 222 },
- { 0, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 219 }
+ { SUF_Z, 0, CPU_386, CPU_MMX, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 245 },
+ { SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 247 },
+ { SUF_Z, 0, CPU_386, CPU_MMX, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 246 },
+ { SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 249 },
+ { SUF_Z, 0, CPU_386, CPU_SSE2, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x6E, 0}, 0, 2, 251 },
+ { SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x6E, 0}, 0, 2, 253 },
+ { SUF_Z, 0, CPU_386, CPU_SSE2, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x7E, 0}, 0, 2, 173 },
+ { SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x7E, 0}, 0, 2, 167 }
};
static const x86_insn_info movq_insn[] = {
- { GAS_ILLEGAL, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x6F, 0}, 0, 2, 234 },
- { GAS_ILLEGAL, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 281 },
- { GAS_ILLEGAL, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x7F, 0}, 0, 2, 317 },
- { GAS_ILLEGAL, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 283 },
- { GAS_ILLEGAL, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 64 },
- { GAS_ILLEGAL, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 319 },
- { GAS_ILLEGAL, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 287 },
- { GAS_ILLEGAL, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0xD6, 0}, 0, 2, 321 },
- { GAS_ILLEGAL, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 219 }
+ { GAS_ILLEGAL|SUF_Z, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x6F, 0}, 0, 2, 185 },
+ { GAS_ILLEGAL|SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 247 },
+ { GAS_ILLEGAL|SUF_Z, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x7F, 0}, 0, 2, 283 },
+ { GAS_ILLEGAL|SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 249 },
+ { GAS_ILLEGAL|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2, 88 },
+ { GAS_ILLEGAL|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2, 285 },
+ { GAS_ILLEGAL|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x6E, 0}, 0, 2, 253 },
+ { GAS_ILLEGAL|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xD6, 0}, 0, 2, 287 },
+ { GAS_ILLEGAL|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x7E, 0}, 0, 2, 167 }
};
static const x86_insn_info mmxsse2_insn[] = {
- { 0, 0, CPU_MMX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 234 },
- { 0, 0, CPU_SSE2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x00, 0}, 0, 2, 57 }
+ { SUF_Z, 0, CPU_MMX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 185 },
+ { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x00, 0}, 0, 2, 170 }
};
static const x86_insn_info pshift_insn[] = {
- { 0, 0, CPU_MMX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 234 },
- { 0, 0, CPU_MMX, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 199 },
- { 0, 0, CPU_SSE2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x00, 0}, 0, 2, 57 },
- { 0, 0, CPU_SSE2, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0x66, 0, 2, {0x0F, 0x00, 0}, 0, 2, 2 }
+ { SUF_Z, 0, CPU_MMX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 185 },
+ { SUF_Z, 0, CPU_MMX, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 147 },
+ { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x00, 0}, 0, 2, 170 },
+ { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0x66, 2, {0x0F, 0x00, 0}, 0, 2, 2 }
};
static const x86_insn_info vpshift_insn[] = {
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0xC1, 0, 2, {0x0F, 0x00, 0}, 0, 2, 195 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0xC1, 0, 2, {0x0F, 0x00, 0}, 0, 2, 469 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0xC1, 0, 2, {0x0F, 0x00, 0}, 0, 3, 40 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0xC1, 0, 2, {0x0F, 0x00, 0}, 0, 3, 1 }
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0x00, 0}, 0, 2, 143 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0xC1, 2, {0x0F, 0x00, 0}, 0, 2, 451 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0x00, 0}, 0, 3, 52 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0xC1, 2, {0x0F, 0x00, 0}, 0, 3, 1 }
};
static const x86_insn_info xmm_xmm128_256_insn[] = {
- { 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 195 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 40 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 0, 2, {0x0F, 0x00, 0}, 0, 3, 8 }
+ { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 143 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 52 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 3, 8 }
};
static const x86_insn_info xmm_xmm128_insn[] = {
- { 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 195 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 40 }
+ { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 143 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 52 }
};
static const x86_insn_info cvt_rx_xmm32_insn[] = {
- { SUF_L, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 201 },
- { SUF_L, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 345 },
- { SUF_Q, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 207 },
- { SUF_Q, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 347 }
+ { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 149 },
+ { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 311 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 155 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 313 }
};
static const x86_insn_info cvt_mm_xmm64_insn[] = {
- { 0, 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 301 },
- { 0, 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 303 }
+ { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 267 },
+ { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 269 }
};
static const x86_insn_info cvt_xmm_mm_ps_insn[] = {
- { 0, 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 319 }
+ { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 285 }
};
static const x86_insn_info cvt_xmm_rmx_insn[] = {
- { SUF_L, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 587 },
- { SUF_L, NOT_64, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 186 },
- { SUF_Q, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 589 },
- { SUF_L, ONLY_AVX|NOT_64, CPU_386, CPU_AVX, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 24 },
- { SUF_L, ONLY_AVX, CPU_386, CPU_AVX, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 267 },
- { SUF_Q, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 64, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 270 }
+ { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 573 },
+ { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 134 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 575 },
+ { SUF_L|SUF_Z, ONLY_AVX|NOT_64, CPU_386, CPU_AVX, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 24 },
+ { SUF_L|SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 233 },
+ { SUF_Q|SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 64, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 236 }
};
static const x86_insn_info xmm_xmm32_insn[] = {
- { 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 144 },
- { 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 192 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 0 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 36 }
+ { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 92 },
+ { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 140 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 0 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 48 }
};
static const x86_insn_info ssecmp_128_insn[] = {
- { 0, 0, CPU_SSE, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0, 0, 2, {0x0F, 0xC2, 0}, 0, 2, 195 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0xC2, 0}, 0, 3, 40 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC4, 0, 2, {0x0F, 0xC2, 0}, 0, 3, 8 }
+ { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0, 2, {0x0F, 0xC2, 0}, 0, 2, 143 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 2, {0x0F, 0xC2, 0}, 0, 3, 52 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC4, 2, {0x0F, 0xC2, 0}, 0, 3, 8 }
};
static const x86_insn_info ssecmp_32_insn[] = {
- { 0, 0, CPU_SSE, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0xC2, 0}, 0, 2, 144 },
- { 0, 0, CPU_SSE, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0xC2, 0}, 0, 2, 192 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0xC2, 0}, 0, 3, 0 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0xC2, 0}, 0, 3, 36 }
+ { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0xC2, 0}, 0, 2, 92 },
+ { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0xC2, 0}, 0, 2, 140 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 2, {0x0F, 0xC2, 0}, 0, 3, 0 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 2, {0x0F, 0xC2, 0}, 0, 3, 48 }
};
static const x86_insn_info xmm_xmm128_imm_insn[] = {
- { 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 77 }
+ { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 170 }
};
static const x86_insn_info xmm_xmm128_imm_256_insn[] = {
- { 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 195 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 4, 40 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 0, 2, {0x0F, 0x00, 0}, 0, 4, 8 }
+ { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 143 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 4, 52 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 4, 8 }
};
static const x86_insn_info xmm_xmm32_imm_insn[] = {
- { 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 3, 144 },
- { 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 3, 192 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 4, 0 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 4, 36 }
+ { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 3, 92 },
+ { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 3, 140 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 4, 0 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 4, 48 }
};
static const x86_insn_info ldstmxcsr_insn[] = {
- { 0, 0, CPU_SSE, 0, 0, {MOD_SpAdd, MOD_SetVEX, 0}, 0, 0, 0, 0, 2, {0x0F, 0xAE, 0}, 0, 1, 38 }
+ { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_SpAdd, MOD_SetVEX, 0}, 0, 0, 0, 2, {0x0F, 0xAE, 0}, 0, 1, 50 }
};
static const x86_insn_info maskmovq_insn[] = {
- { 0, 0, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xF7, 0}, 0, 2, 581 }
+ { SUF_Z, 0, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xF7, 0}, 0, 2, 567 }
};
static const x86_insn_info movau_insn[] = {
- { 0, NOT_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 57 },
- { 0, NOT_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op1Add}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 86 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 57 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op1Add}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 86 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 0, 2, {0x0F, 0x00, 0}, 0, 2, 225 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op1Add}, 0, 0, 0xC4, 0, 2, {0x0F, 0x00, 0}, 0, 2, 453 }
+ { SUF_Z, NOT_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 170 },
+ { SUF_Z, NOT_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op1Add}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 425 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 170 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op1Add}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 425 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 176 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op1Add}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 427 }
};
static const x86_insn_info movhllhps_insn[] = {
- { 0, 0, CPU_SSE, 0, 0, {MOD_Op1Add, MOD_SetVEX, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 144 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 0 }
+ { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Op1Add, MOD_SetVEX, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 92 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 0 }
};
static const x86_insn_info movhlp_insn[] = {
- { 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 147 },
- { 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x01, 0}, 0, 2, 106 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 4 }
+ { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 95 },
+ { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x01, 0}, 0, 2, 39 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 4 }
};
static const x86_insn_info movmsk_insn[] = {
- { SUF_L, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_SetVEX, 0}, 0, 0, 0x00, 0, 2, {0x0F, 0x50, 0}, 0, 2, 201 },
- { SUF_Q, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_SetVEX, 0}, 64, 0, 0x00, 0, 2, {0x0F, 0x50, 0}, 0, 2, 207 },
- { SUF_L, ONLY_AVX, CPU_386, CPU_AVX, 0, {MOD_PreAdd, 0, 0}, 0, 0, 0xC4, 0, 2, {0x0F, 0x50, 0}, 0, 2, 305 },
- { SUF_Q, ONLY_64|ONLY_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, 0, 0}, 64, 0, 0xC4, 0, 2, {0x0F, 0x50, 0}, 0, 2, 307 }
+ { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_SetVEX, 0}, 0, 0, 0x00, 2, {0x0F, 0x50, 0}, 0, 2, 149 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_SetVEX, 0}, 64, 0, 0x00, 2, {0x0F, 0x50, 0}, 0, 2, 155 },
+ { SUF_L|SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {MOD_PreAdd, 0, 0}, 0, 0, 0xC4, 2, {0x0F, 0x50, 0}, 0, 2, 271 },
+ { SUF_Q|SUF_Z, ONLY_64|ONLY_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, 0, 0}, 64, 0, 0xC4, 2, {0x0F, 0x50, 0}, 0, 2, 273 }
};
static const x86_insn_info movnt_insn[] = {
- { 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 541 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 0, 2, {0x0F, 0x00, 0}, 0, 2, 543 }
+ { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 531 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 533 }
};
static const x86_insn_info movntq_insn[] = {
- { 0, 0, CPU_SSE, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xE7, 0}, 0, 2, 349 }
+ { SUF_Z, 0, CPU_SSE, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xE7, 0}, 0, 2, 315 }
};
static const x86_insn_info movss_insn[] = {
- { 0, 0, CPU_SSE, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF3, 0, 2, {0x0F, 0x10, 0}, 0, 2, 144 },
- { 0, 0, CPU_SSE, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF3, 0, 2, {0x0F, 0x10, 0}, 0, 2, 125 },
- { 0, 0, CPU_SSE, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF3, 0, 2, {0x0F, 0x11, 0}, 0, 2, 134 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC2, 0, 2, {0x0F, 0x10, 0}, 0, 3, 0 }
+ { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x10, 0}, 0, 2, 92 },
+ { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x10, 0}, 0, 2, 288 },
+ { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x11, 0}, 0, 2, 529 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC2, 2, {0x0F, 0x10, 0}, 0, 3, 0 }
};
static const x86_insn_info pextrw_insn[] = {
- { SUF_L, NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xC5, 0}, 0, 3, 198 },
- { SUF_L, 0, CPU_386, CPU_SSE2, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0xC5, 0}, 0, 3, 201 },
- { SUF_Q, ONLY_64|NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0xC5, 0}, 0, 3, 204 },
- { SUF_Q, ONLY_64, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 0, 2, {0x0F, 0xC5, 0}, 0, 3, 207 },
- { 0, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x15}, 0, 3, 210 },
- { 0, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 32, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x15}, 0, 3, 213 },
- { 0, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x15}, 0, 3, 216 }
+ { SUF_L|SUF_Z, NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xC5, 0}, 0, 3, 146 },
+ { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE2, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xC5, 0}, 0, 3, 149 },
+ { SUF_Q|SUF_Z, ONLY_64|NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC5, 0}, 0, 3, 152 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0xC5, 0}, 0, 3, 155 },
+ { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x15}, 0, 3, 158 },
+ { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 32, 0, 0x66, 3, {0x0F, 0x3A, 0x15}, 0, 3, 161 },
+ { SUF_Z, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x15}, 0, 3, 164 }
};
static const x86_insn_info pinsrw_insn[] = {
- { SUF_L, NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xC4, 0}, 0, 3, 168 },
- { SUF_Q, ONLY_64|NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0xC4, 0}, 0, 3, 171 },
- { SUF_L, NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xC4, 0}, 0, 3, 174 },
- { SUF_L, 0, CPU_386, CPU_SSE2, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0xC4, 0}, 0, 3, 177 },
- { SUF_Q, ONLY_64, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 0, 2, {0x0F, 0xC4, 0}, 0, 3, 180 },
- { SUF_L, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0xC4, 0}, 0, 3, 183 },
- { SUF_L, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 0, 2, {0x0F, 0xC4, 0}, 0, 4, 12 },
- { SUF_Q, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 0, 0xC1, 0, 2, {0x0F, 0xC4, 0}, 0, 4, 16 },
- { SUF_L, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 0, 2, {0x0F, 0xC4, 0}, 0, 4, 20 }
+ { SUF_L|SUF_Z, NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xC4, 0}, 0, 3, 116 },
+ { SUF_Q|SUF_Z, ONLY_64|NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 64, 64, 0, 2, {0x0F, 0xC4, 0}, 0, 3, 119 },
+ { SUF_L|SUF_Z, NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xC4, 0}, 0, 3, 122 },
+ { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE2, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xC4, 0}, 0, 3, 125 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 64, 64, 0x66, 2, {0x0F, 0xC4, 0}, 0, 3, 128 },
+ { SUF_L|SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xC4, 0}, 0, 3, 131 },
+ { SUF_L|SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0xC4, 0}, 0, 4, 12 },
+ { SUF_Q|SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 64, 0xC1, 2, {0x0F, 0xC4, 0}, 0, 4, 16 },
+ { SUF_L|SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0xC4, 0}, 0, 4, 20 }
};
static const x86_insn_info pmovmskb_insn[] = {
- { SUF_L, NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xD7, 0}, 0, 2, 198 },
- { SUF_L, 0, CPU_386, CPU_SSE2, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0xD7, 0}, 0, 2, 201 },
- { SUF_Q, ONLY_64|NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0xD7, 0}, 0, 2, 204 },
- { SUF_Q, ONLY_64, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 0, 2, {0x0F, 0xD7, 0}, 0, 2, 207 }
+ { SUF_L|SUF_Z, NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xD7, 0}, 0, 2, 146 },
+ { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE2, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xD7, 0}, 0, 2, 149 },
+ { SUF_Q|SUF_Z, ONLY_64|NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xD7, 0}, 0, 2, 152 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0xD7, 0}, 0, 2, 155 }
};
static const x86_insn_info pshufw_insn[] = {
- { 0, 0, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x70, 0}, 0, 3, 234 }
+ { SUF_Z, 0, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x70, 0}, 0, 3, 185 }
};
static const x86_insn_info xmm_xmm64_insn[] = {
- { 0, 0, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 144 },
- { 0, 0, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 147 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 0 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 4 }
+ { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 92 },
+ { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 95 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 0 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 4 }
};
static const x86_insn_info ssecmp_64_insn[] = {
- { 0, 0, CPU_SSE2, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0xC2, 0}, 0, 2, 144 },
- { 0, 0, CPU_SSE2, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0xC2, 0}, 0, 2, 147 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0xC2, 0}, 0, 3, 0 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0xC2, 0}, 0, 3, 4 }
+ { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0xC2, 0}, 0, 2, 92 },
+ { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0xC2, 0}, 0, 2, 95 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 2, {0x0F, 0xC2, 0}, 0, 3, 0 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 2, {0x0F, 0xC2, 0}, 0, 3, 4 }
};
static const x86_insn_info cvt_rx_xmm64_insn[] = {
- { SUF_L, 0, CPU_386, CPU_SSE2, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 201 },
- { SUF_L, 0, CPU_386, CPU_SSE2, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 324 },
- { SUF_Q, ONLY_64, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 207 },
- { SUF_Q, ONLY_64, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 441 }
+ { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE2, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 149 },
+ { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE2, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 290 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 155 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 409 }
};
static const x86_insn_info cvt_mm_xmm_insn[] = {
- { 0, 0, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 565 }
+ { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 543 }
};
static const x86_insn_info cvt_xmm_mm_ss_insn[] = {
- { 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 319 }
+ { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 285 }
};
+static const x86_insn_info eptvpid_insn[] = {
+ { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_EPTVPID, 0, {MOD_Op2Add, 0, 0}, 32, 0, 0x66, 3, {0x0F, 0x38, 0x80}, 0, 2, 551 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_EPTVPID, 0, 0, {MOD_Op2Add, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x38, 0x80}, 0, 2, 553 }
+};
+
static const x86_insn_info vmxmemrd_insn[] = {
- { SUF_L, NOT_64, CPU_P4, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x78, 0}, 0, 2, 252 },
- { SUF_Q, ONLY_64, CPU_P4, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 2, {0x0F, 0x78, 0}, 0, 2, 258 }
+ { SUF_L|SUF_Z, NOT_64, CPU_P4, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0x78, 0}, 0, 2, 218 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_P4, 0, 0, {0, 0, 0}, 64, 64, 0, 2, {0x0F, 0x78, 0}, 0, 2, 224 }
};
static const x86_insn_info vmxmemwr_insn[] = {
- { SUF_L, NOT_64, CPU_P4, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x79, 0}, 0, 2, 153 },
- { SUF_Q, ONLY_64, CPU_P4, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 2, {0x0F, 0x79, 0}, 0, 2, 156 }
+ { SUF_L|SUF_Z, NOT_64, CPU_P4, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0x79, 0}, 0, 2, 101 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_P4, 0, 0, {0, 0, 0}, 64, 64, 0, 2, {0x0F, 0x79, 0}, 0, 2, 104 }
};
static const x86_insn_info vmxtwobytemem_insn[] = {
- { 0, 0, CPU_P4, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xC7, 0}, 0, 1, 6 }
+ { SUF_Z, 0, CPU_P4, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 2, {0x0F, 0xC7, 0}, 0, 1, 6 }
};
static const x86_insn_info vmxthreebytemem_insn[] = {
- { 0, 0, CPU_P4, 0, 0, {MOD_PreAdd, 0, 0}, 0, 0, 0x00, 0, 2, {0x0F, 0xC7, 0}, 6, 1, 6 }
+ { SUF_Z, 0, CPU_P4, 0, 0, {MOD_PreAdd, 0, 0}, 0, 0, 0x00, 2, {0x0F, 0xC7, 0}, 6, 1, 6 }
};
static const x86_insn_info maskmovdqu_insn[] = {
- { 0, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0xF7, 0}, 0, 2, 64 }
+ { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xF7, 0}, 0, 2, 88 }
};
static const x86_insn_info movdq2q_insn[] = {
- { 0, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0xD6, 0}, 0, 2, 301 }
+ { SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0xD6, 0}, 0, 2, 267 }
};
static const x86_insn_info movq2dq_insn[] = {
- { 0, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 0, 2, {0x0F, 0xD6, 0}, 0, 2, 431 }
+ { SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0xD6, 0}, 0, 2, 397 }
};
static const x86_insn_info pslrldq_insn[] = {
- { 0, 0, CPU_SSE2, 0, 0, {MOD_SpAdd, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x73, 0}, 0, 2, 469 },
- { 0, 0, CPU_SSE2, 0, 0, {MOD_SpAdd, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x73, 0}, 0, 3, 1 }
+ { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SpAdd, MOD_SetVEX, 0}, 0, 0, 0x66, 2, {0x0F, 0x73, 0}, 0, 2, 451 },
+ { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SpAdd, MOD_SetVEX, 0}, 0, 0, 0x66, 2, {0x0F, 0x73, 0}, 0, 3, 1 }
};
static const x86_insn_info lddqu_insn[] = {
- { 0, 0, CPU_SSE3, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0xF0, 0}, 0, 2, 539 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC7, 0, 2, {0x0F, 0xF0, 0}, 0, 2, 579 }
+ { SUF_Z, 0, CPU_SSE3, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0xF0, 0}, 0, 2, 527 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC7, 2, {0x0F, 0xF0, 0}, 0, 2, 565 }
};
static const x86_insn_info ssse3_insn[] = {
- { 0, NOT_AVX, CPU_SSSE3, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, 234 },
- { 0, 0, CPU_SSSE3, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, 195 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x38, 0x00}, 0, 3, 40 }
+ { SUF_Z, NOT_AVX, CPU_SSSE3, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, 185 },
+ { SUF_Z, 0, CPU_SSSE3, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 143 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 52 }
};
static const x86_insn_info ssse3imm_insn[] = {
- { 0, 0, CPU_SSSE3, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 234 },
- { 0, 0, CPU_SSSE3, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 77 }
+ { SUF_Z, 0, CPU_SSSE3, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 185 },
+ { SUF_Z, 0, CPU_SSSE3, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 170 }
};
static const x86_insn_info sse4_insn[] = {
- { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, 57 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, 225 }
+ { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 170 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 2, 176 }
};
static const x86_insn_info sse4imm_256_insn[] = {
- { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 195 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x3A, 0x00}, 0, 4, 40 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0x3A, 0x00}, 0, 4, 8 }
+ { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 143 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 52 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 4, 8 }
};
static const x86_insn_info sse4imm_insn[] = {
- { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 195 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x3A, 0x00}, 0, 4, 40 }
+ { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 143 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 52 }
};
static const x86_insn_info sse4m32imm_insn[] = {
- { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 144 },
- { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 192 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x3A, 0x00}, 0, 4, 0 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x3A, 0x00}, 0, 4, 36 }
+ { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 92 },
+ { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 140 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 0 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 48 }
};
static const x86_insn_info sse4m64imm_insn[] = {
- { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 144 },
- { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 147 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x3A, 0x00}, 0, 4, 0 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x3A, 0x00}, 0, 4, 4 }
+ { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 92 },
+ { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 95 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 0 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 4 }
};
static const x86_insn_info sse4xmm0_insn[] = {
- { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, 57 },
- { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x38, 0x00}, 0, 3, 231 }
+ { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 170 },
+ { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 3, 209 }
};
static const x86_insn_info avx_sse4xmm0_insn[] = {
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x3A, 0x00}, 0, 4, 48 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0x3A, 0x00}, 0, 4, 52 }
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 60 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 4, 64 }
};
static const x86_insn_info avx_sse4xmm0_128_insn[] = {
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x3A, 0x00}, 0, 4, 48 }
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 60 }
};
static const x86_insn_info crc32_insn[] = {
- { SUF_B, 0, CPU_386, CPU_SSE42, 0, {0, 0, 0}, 0, 0, 0xF2, 0, 3, {0x0F, 0x38, 0xF0}, 0, 2, 495 },
- { SUF_W, 0, CPU_386, CPU_SSE42, 0, {0, 0, 0}, 16, 0, 0xF2, 0, 3, {0x0F, 0x38, 0xF1}, 0, 2, 497 },
- { SUF_L, 0, CPU_386, CPU_SSE42, 0, {0, 0, 0}, 32, 0, 0xF2, 0, 3, {0x0F, 0x38, 0xF1}, 0, 2, 153 },
- { SUF_B, ONLY_64, CPU_SSE42, 0, 0, {0, 0, 0}, 64, 0, 0xF2, 0, 3, {0x0F, 0x38, 0xF0}, 0, 2, 499 },
- { SUF_Q, ONLY_64, CPU_SSE42, 0, 0, {0, 0, 0}, 64, 0, 0xF2, 0, 3, {0x0F, 0x38, 0xF1}, 0, 2, 156 }
+ { SUF_B|SUF_Z, 0, CPU_386, CPU_SSE42, 0, {0, 0, 0}, 0, 0, 0xF2, 3, {0x0F, 0x38, 0xF0}, 0, 2, 475 },
+ { SUF_W|SUF_Z, 0, CPU_386, CPU_SSE42, 0, {0, 0, 0}, 16, 0, 0xF2, 3, {0x0F, 0x38, 0xF1}, 0, 2, 477 },
+ { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE42, 0, {0, 0, 0}, 32, 0, 0xF2, 3, {0x0F, 0x38, 0xF1}, 0, 2, 101 },
+ { SUF_B|SUF_Z, ONLY_64, CPU_SSE42, 0, 0, {0, 0, 0}, 64, 0, 0xF2, 3, {0x0F, 0x38, 0xF0}, 0, 2, 479 },
+ { SUF_Q|SUF_Z, ONLY_64, CPU_SSE42, 0, 0, {0, 0, 0}, 64, 0, 0xF2, 3, {0x0F, 0x38, 0xF1}, 0, 2, 104 }
};
static const x86_insn_info extractps_insn[] = {
- { 0, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 32, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x17}, 0, 3, 222 },
- { 0, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x17}, 0, 3, 216 }
+ { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x17}, 0, 3, 173 },
+ { SUF_Z, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x17}, 0, 3, 164 }
};
static const x86_insn_info insertps_insn[] = {
- { 0, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x21}, 0, 3, 192 },
- { 0, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x21}, 0, 3, 144 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x3A, 0x21}, 0, 4, 36 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x3A, 0x21}, 0, 4, 0 }
+ { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x21}, 0, 3, 140 },
+ { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x21}, 0, 3, 92 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x21}, 0, 4, 48 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x21}, 0, 4, 0 }
};
static const x86_insn_info movntdqa_insn[] = {
- { 0, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x38, 0x2A}, 0, 2, 539 }
+ { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x2A}, 0, 2, 527 }
};
static const x86_insn_info sse4pcmpstr_insn[] = {
- { 0, 0, CPU_SSE42, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 77 }
+ { SUF_Z, 0, CPU_SSE42, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 170 }
};
static const x86_insn_info pextrb_insn[] = {
- { 0, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x14}, 0, 3, 228 },
- { 0, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 32, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x14}, 0, 3, 213 },
- { 0, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x14}, 0, 3, 216 }
+ { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x14}, 0, 3, 179 },
+ { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x14}, 0, 3, 161 },
+ { SUF_Z, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x14}, 0, 3, 164 }
};
static const x86_insn_info pextrd_insn[] = {
- { 0, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 32, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x16}, 0, 3, 222 }
+ { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x16}, 0, 3, 173 }
};
static const x86_insn_info pextrq_insn[] = {
- { 0, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x16}, 0, 3, 219 }
+ { SUF_Z, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x16}, 0, 3, 167 }
};
static const x86_insn_info pinsrb_insn[] = {
- { 0, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x20}, 0, 3, 189 },
- { 0, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 32, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x20}, 0, 3, 177 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x3A, 0x20}, 0, 4, 28 },
- { 0, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 32, 0, 0xC1, 0, 3, {0x0F, 0x3A, 0x20}, 0, 4, 32 }
+ { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x20}, 0, 3, 137 },
+ { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x20}, 0, 3, 125 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x20}, 0, 4, 40 },
+ { SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x20}, 0, 4, 44 }
};
static const x86_insn_info pinsrd_insn[] = {
- { 0, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 32, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x22}, 0, 3, 186 },
- { 0, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 32, 0, 0xC1, 0, 3, {0x0F, 0x3A, 0x22}, 0, 4, 24 }
+ { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x22}, 0, 3, 134 },
+ { SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x22}, 0, 4, 24 }
};
static const x86_insn_info pinsrq_insn[] = {
- { 0, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x22}, 0, 3, 243 },
- { 0, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 0, 0xC1, 0, 3, {0x0F, 0x3A, 0x22}, 0, 4, 60 }
+ { SUF_Z, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x22}, 0, 3, 206 },
+ { SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 0, 0xC1, 3, {0x0F, 0x3A, 0x22}, 0, 4, 76 }
};
static const x86_insn_info sse4m16_insn[] = {
- { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, 433 },
- { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, 64 }
+ { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 399 },
+ { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 88 }
};
static const x86_insn_info sse4m32_insn[] = {
- { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, 125 },
- { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, 64 }
+ { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 288 },
+ { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 88 }
};
static const x86_insn_info sse4m64_insn[] = {
- { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, 73 },
- { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, 64 }
+ { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 401 },
+ { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 88 }
};
static const x86_insn_info cnt_insn[] = {
- { SUF_W, 0, 0, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0xF3, 0, 2, {0x0F, 0x00, 0}, 0, 2, 150 },
- { SUF_L, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0xF3, 0, 2, {0x0F, 0x00, 0}, 0, 2, 153 },
- { SUF_Q, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0xF3, 0, 2, {0x0F, 0x00, 0}, 0, 2, 156 }
+ { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0xF3, 2, {0x0F, 0x00, 0}, 0, 2, 98 },
+ { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0xF3, 2, {0x0F, 0x00, 0}, 0, 2, 101 },
+ { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0xF3, 2, {0x0F, 0x00, 0}, 0, 2, 104 }
};
static const x86_insn_info vmovd_insn[] = {
- { 0, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 285 },
- { 0, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 222 }
+ { SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0x6E, 0}, 0, 2, 251 },
+ { SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0x7E, 0}, 0, 2, 173 }
};
static const x86_insn_info vmovq_insn[] = {
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC2, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 64 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC2, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 73 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 0, 2, {0x0F, 0xD6, 0}, 0, 2, 106 },
- { 0, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 0, 0xC1, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 287 },
- { 0, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 0, 0xC1, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 219 }
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC2, 2, {0x0F, 0x7E, 0}, 0, 2, 88 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC2, 2, {0x0F, 0x7E, 0}, 0, 2, 401 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0xD6, 0}, 0, 2, 39 },
+ { SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 0, 0xC1, 2, {0x0F, 0x6E, 0}, 0, 2, 253 },
+ { SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 0, 0xC1, 2, {0x0F, 0x7E, 0}, 0, 2, 167 }
};
static const x86_insn_info avx_xmm_xmm128_insn[] = {
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 57 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 0, 2, {0x0F, 0x00, 0}, 0, 2, 225 }
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 170 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 176 }
};
static const x86_insn_info avx_sse4imm_insn[] = {
- { 0, ONLY_AVX, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 77 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 77 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 225 }
+ { SUF_Z, ONLY_AVX, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 3, 170 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 3, 170 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 3, 176 }
};
static const x86_insn_info vmovddup_insn[] = {
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 64 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 73 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 0, 2, {0x0F, 0x00, 0}, 0, 2, 225 }
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 88 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 401 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 176 }
};
static const x86_insn_info avx_xmm_xmm64_insn[] = {
- { 0, ONLY_AVX, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 64 },
- { 0, ONLY_AVX, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 73 }
+ { SUF_Z, ONLY_AVX, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 88 },
+ { SUF_Z, ONLY_AVX, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 401 }
};
static const x86_insn_info avx_xmm_xmm32_insn[] = {
- { 0, ONLY_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 64 },
- { 0, ONLY_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 125 }
+ { SUF_Z, ONLY_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 88 },
+ { SUF_Z, ONLY_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 288 }
};
static const x86_insn_info avx_cvt_xmm64_insn[] = {
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 64 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 73 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 0, 2, {0x0F, 0x00, 0}, 0, 2, 435 }
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 88 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 401 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 403 }
};
static const x86_insn_info avx_ssse3_2op_insn[] = {
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, 57 }
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 2, 170 }
};
static const x86_insn_info avx_cvt_xmm128_x_insn[] = {
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 57 }
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 170 }
};
static const x86_insn_info avx_cvt_xmm128_y_insn[] = {
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 0, 2, {0x0F, 0x00, 0}, 0, 2, 239 }
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 190 }
};
static const x86_insn_info avx_cvt_xmm128_insn[] = {
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 549 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 0, 2, {0x0F, 0x00, 0}, 0, 2, 551 }
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 539 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 541 }
};
static const x86_insn_info vbroadcastss_insn[] = {
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x38, 0x18}, 0, 2, 125 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0x38, 0x18}, 0, 2, 455 }
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x18}, 0, 2, 288 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x18}, 0, 2, 437 }
};
static const x86_insn_info vbroadcastsd_insn[] = {
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0x38, 0x19}, 0, 2, 451 }
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x19}, 0, 2, 423 }
};
static const x86_insn_info vbroadcastf128_insn[] = {
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0x38, 0x1A}, 0, 2, 569 }
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x1A}, 0, 2, 547 }
};
static const x86_insn_info vextractf128_insn[] = {
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0x3A, 0x19}, 0, 3, 264 }
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x19}, 0, 3, 230 }
};
static const x86_insn_info vinsertf128_insn[] = {
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0x3A, 0x18}, 0, 4, 44 }
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x18}, 0, 4, 56 }
};
static const x86_insn_info vzero_insn[] = {
- { 0, 0, CPU_AVX, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x77, 0}, 0, 0, 0 }
+ { SUF_Z, 0, CPU_AVX, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0, 2, {0x0F, 0x77, 0}, 0, 0, 0 }
};
static const x86_insn_info vmaskmov_insn[] = {
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x38, 0x00}, 0, 3, 40 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0x38, 0x00}, 0, 3, 8 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x38, 0x02}, 0, 3, 237 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0x38, 0x02}, 0, 3, 240 }
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 52 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 3, 8 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x02}, 0, 3, 188 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x02}, 0, 3, 191 }
};
static const x86_insn_info vpermil_insn[] = {
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x38, 0x08}, 0, 3, 40 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0x38, 0x08}, 0, 3, 8 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 77 },
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 225 }
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x08}, 0, 3, 52 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x08}, 0, 3, 8 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 3, 170 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 3, 176 }
};
static const x86_insn_info vperm2f128_insn[] = {
- { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0x3A, 0x06}, 0, 4, 8 }
+ { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x06}, 0, 4, 8 }
};
static const x86_insn_info vfma_ps_insn[] = {
- { 0, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x38, 0x00}, 0, 3, 40 },
- { 0, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0x38, 0x00}, 0, 3, 8 }
+ { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 52 },
+ { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 3, 8 }
};
static const x86_insn_info vfma_pd_insn[] = {
- { 0, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 0, 3, {0x0F, 0x38, 0x00}, 0, 3, 40 },
- { 0, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xCD, 0, 3, {0x0F, 0x38, 0x00}, 0, 3, 8 }
+ { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x38, 0x00}, 0, 3, 52 },
+ { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xCD, 3, {0x0F, 0x38, 0x00}, 0, 3, 8 }
};
static const x86_insn_info vfma_ss_insn[] = {
- { 0, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x38, 0x00}, 0, 3, 0 },
- { 0, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x38, 0x00}, 0, 3, 36 }
+ { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 0 },
+ { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 48 }
};
static const x86_insn_info vfma_sd_insn[] = {
- { 0, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 0, 3, {0x0F, 0x38, 0x00}, 0, 3, 0 },
- { 0, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 0, 3, {0x0F, 0x38, 0x00}, 0, 3, 4 }
+ { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x38, 0x00}, 0, 3, 0 },
+ { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x38, 0x00}, 0, 3, 4 }
};
static const x86_insn_info aes_insn[] = {
- { 0, 0, CPU_AES, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 0, 3, {0x0F, 0x00, 0x00}, 0, 2, 195 },
- { 0, ONLY_AVX, CPU_AES, CPU_AVX, 0, {MOD_Op1Add, MOD_Op2Add, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x00, 0x00}, 0, 3, 40 }
+ { SUF_Z, 0, CPU_AES, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 3, {0x0F, 0x00, 0x00}, 0, 2, 143 },
+ { SUF_Z, ONLY_AVX, CPU_AES, CPU_AVX, 0, {MOD_Op1Add, MOD_Op2Add, 0}, 0, 0, 0xC1, 3, {0x0F, 0x00, 0x00}, 0, 3, 52 }
};
static const x86_insn_info aesimc_insn[] = {
- { 0, 0, CPU_AES, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 0, 3, {0x0F, 0x00, 0x00}, 0, 2, 195 }
+ { SUF_Z, 0, CPU_AES, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 3, {0x0F, 0x00, 0x00}, 0, 2, 170 }
};
static const x86_insn_info aes_imm_insn[] = {
- { 0, 0, CPU_AES, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 0, 3, {0x0F, 0x00, 0x00}, 0, 3, 77 }
+ { SUF_Z, 0, CPU_AES, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 3, {0x0F, 0x00, 0x00}, 0, 3, 170 }
};
static const x86_insn_info pclmulqdq_insn[] = {
- { 0, 0, CPU_CLMUL, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 0, 3, {0x0F, 0x00, 0x00}, 0, 3, 195 },
- { 0, ONLY_AVX, CPU_AVX, CPU_CLMUL, 0, {MOD_Op1Add, MOD_Op2Add, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x00, 0x00}, 0, 4, 40 }
+ { SUF_Z, 0, CPU_CLMUL, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 3, {0x0F, 0x00, 0x00}, 0, 3, 143 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, CPU_CLMUL, 0, {MOD_Op1Add, MOD_Op2Add, 0}, 0, 0, 0xC1, 3, {0x0F, 0x00, 0x00}, 0, 4, 52 }
};
static const x86_insn_info pclmulqdq_fixed_insn[] = {
- { 0, 0, CPU_CLMUL, 0, 0, {MOD_Imm8, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x44}, 0, 2, 195 },
- { 0, ONLY_AVX, CPU_AVX, CPU_CLMUL, 0, {MOD_Imm8, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x3A, 0x44}, 0, 3, 40 }
+ { SUF_Z, 0, CPU_CLMUL, 0, 0, {MOD_Imm8, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x44}, 0, 2, 143 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, CPU_CLMUL, 0, {MOD_Imm8, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x44}, 0, 3, 52 }
};
+static const x86_insn_info rdrand_insn[] = {
+ { SUF_Z, 0, CPU_RDRAND, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xC7, 0}, 6, 1, 347 },
+ { SUF_Z, 0, CPU_386, CPU_RDRAND, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xC7, 0}, 6, 1, 14 },
+ { SUF_Z, ONLY_64, CPU_RDRAND, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC7, 0}, 6, 1, 18 }
+};
+
+static const x86_insn_info fs_gs_base_insn[] = {
+ { SUF_Z, ONLY_64, CPU_FSGSBASE, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0xF3, 2, {0x0F, 0xAE, 0}, 0, 1, 14 },
+ { SUF_Z, ONLY_64, CPU_FSGSBASE, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0xF3, 2, {0x0F, 0xAE, 0}, 0, 1, 18 }
+};
+
+static const x86_insn_info avx_cvtps2ph_insn[] = {
+ { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 194 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 197 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC4, 3, {0x0F, 0x3A, 0x00}, 0, 3, 200 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC4, 3, {0x0F, 0x3A, 0x00}, 0, 3, 203 }
+};
+
+static const x86_insn_info avx_cvtph2ps_insn[] = {
+ { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC0, 3, {0x0F, 0x38, 0x00}, 0, 2, 88 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC0, 3, {0x0F, 0x38, 0x00}, 0, 2, 561 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC4, 3, {0x0F, 0x38, 0x00}, 0, 2, 193 },
+ { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC4, 3, {0x0F, 0x38, 0x00}, 0, 2, 563 }
+};
+
static const x86_insn_info extrq_insn[] = {
- { 0, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x78, 0}, 0, 3, 65 },
- { 0, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x79, 0}, 0, 2, 64 }
+ { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x78, 0}, 0, 3, 89 },
+ { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x79, 0}, 0, 2, 88 }
};
static const x86_insn_info insertq_insn[] = {
- { 0, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0x78, 0}, 0, 4, 64 },
- { 0, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0x79, 0}, 0, 2, 64 }
+ { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x78, 0}, 0, 4, 88 },
+ { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x79, 0}, 0, 2, 88 }
};
static const x86_insn_info movntsd_insn[] = {
- { 0, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0x2B, 0}, 0, 2, 106 }
+ { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x2B, 0}, 0, 2, 39 }
};
static const x86_insn_info movntss_insn[] = {
- { 0, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 0, 2, {0x0F, 0x2B, 0}, 0, 2, 134 }
+ { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x2B, 0}, 0, 2, 529 }
};
-static const x86_insn_info sse5com_insn[] = {
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x25, 0x00}, 0, 4, 76 }
+static const x86_insn_info vfrc_pdps_insn[] = {
+ { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x80, 0}, 0, 2, 170 },
+ { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x84, 2, {0x09, 0x80, 0}, 0, 2, 176 }
};
-static const x86_insn_info sse5com32_insn[] = {
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x25, 0x00}, 0, 4, 68 },
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x25, 0x00}, 0, 4, 124 }
+static const x86_insn_info vfrczsd_insn[] = {
+ { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x83, 0}, 0, 2, 88 },
+ { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x83, 0}, 0, 2, 401 }
};
-static const x86_insn_info sse5com64_insn[] = {
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x25, 0x00}, 0, 4, 68 },
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x25, 0x00}, 0, 4, 72 }
+static const x86_insn_info vfrczss_insn[] = {
+ { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x82, 0}, 0, 2, 88 },
+ { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x82, 0}, 0, 2, 288 }
};
-static const x86_insn_info sse5comcc_insn[] = {
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, MOD_Imm8, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x25, 0x00}, 0, 3, 56 }
+static const x86_insn_info vpcmov_insn[] = {
+ { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x08, 0xA2, 0}, 0, 4, 60 },
+ { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x88, 2, {0x08, 0xA2, 0}, 0, 4, 80 },
+ { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x84, 2, {0x08, 0xA2, 0}, 0, 4, 64 },
+ { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x8C, 2, {0x08, 0xA2, 0}, 0, 4, 84 }
};
-static const x86_insn_info sse5comcc32_insn[] = {
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, MOD_Imm8, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x25, 0x00}, 0, 3, 68 },
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, MOD_Imm8, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x25, 0x00}, 0, 3, 124 }
+static const x86_insn_info vpcom_insn[] = {
+ { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, MOD_Imm8, 0}, 0, 0, 0x80, 2, {0x08, 0x00, 0}, 0, 3, 52 }
};
-static const x86_insn_info sse5comcc64_insn[] = {
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, MOD_Imm8, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x25, 0x00}, 0, 3, 68 },
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, MOD_Imm8, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x25, 0x00}, 0, 3, 72 }
+static const x86_insn_info vpcom_imm_insn[] = {
+ { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x08, 0x00, 0}, 0, 4, 52 }
};
-static const x86_insn_info cvtph2ps_insn[] = {
- { 0, 0, CPU_SSE5, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7A, 0x30}, 0, 2, 64 },
- { 0, 0, CPU_SSE5, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7A, 0x30}, 0, 2, 73 }
+static const x86_insn_info vphaddsub_insn[] = {
+ { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x00, 0}, 0, 2, 170 }
};
-static const x86_insn_info cvtps2ph_insn[] = {
- { 0, 0, CPU_SSE5, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7A, 0x31}, 0, 2, 102 },
- { 0, 0, CPU_SSE5, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7A, 0x31}, 0, 2, 106 }
+static const x86_insn_info vpma_insn[] = {
+ { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x08, 0x00, 0}, 0, 4, 60 }
};
-static const x86_insn_info sse5arith_insn[] = {
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0x00}, 0, 4, 80 },
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0x00}, 0, 4, 84 },
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0x04}, 0, 4, 56 },
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0x04}, 0, 4, 88 }
+static const x86_insn_info vpperm_insn[] = {
+ { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x08, 0xA3, 0}, 0, 4, 60 },
+ { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x88, 2, {0x08, 0xA3, 0}, 0, 4, 80 }
};
-static const x86_insn_info sse5arith32_insn[] = {
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0x00}, 0, 4, 92 },
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0x00}, 0, 4, 128 },
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0x00}, 0, 4, 100 },
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0x00}, 0, 4, 132 },
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0x04}, 0, 4, 108 },
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0x04}, 0, 4, 136 },
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0x04}, 0, 4, 116 },
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0x04}, 0, 4, 140 }
+static const x86_insn_info vprot_insn[] = {
+ { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x90, 0}, 0, 3, 182 },
+ { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x88, 2, {0x09, 0x90, 0}, 0, 3, 52 },
+ { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x08, 0xC0, 0}, 0, 3, 170 }
};
-static const x86_insn_info sse5arith64_insn[] = {
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0x00}, 0, 4, 92 },
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0x00}, 0, 4, 96 },
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0x00}, 0, 4, 100 },
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0x00}, 0, 4, 104 },
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0x04}, 0, 4, 108 },
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0x04}, 0, 4, 112 },
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0x04}, 0, 4, 116 },
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0x04}, 0, 4, 120 }
+static const x86_insn_info amd_vpshift_insn[] = {
+ { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x00, 0}, 0, 3, 182 },
+ { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x88, 2, {0x09, 0x00, 0}, 0, 3, 52 }
};
-static const x86_insn_info sse5two_insn[] = {
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7A, 0x00}, 0, 2, 57 }
+static const x86_insn_info fma_128_256_insn[] = {
+ { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 60 },
+ { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x3A, 0x00}, 0, 4, 80 },
+ { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 4, 64 },
+ { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xCD, 3, {0x0F, 0x3A, 0x00}, 0, 4, 84 }
};
-static const x86_insn_info sse5two32_insn[] = {
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7A, 0x00}, 0, 2, 64 },
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7A, 0x00}, 0, 2, 125 }
+static const x86_insn_info fma_128_m32_insn[] = {
+ { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 28 },
+ { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 68 },
+ { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x3A, 0x00}, 0, 4, 72 }
};
-static const x86_insn_info sse5two64_insn[] = {
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7A, 0x00}, 0, 2, 64 },
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7A, 0x00}, 0, 2, 73 }
+static const x86_insn_info fma_128_m64_insn[] = {
+ { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 28 },
+ { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 32 },
+ { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x3A, 0x00}, 0, 4, 36 }
};
-static const x86_insn_info sse5pmacs_insn[] = {
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0x00}, 0, 4, 56 }
+static const x86_insn_info xsaveopt64_insn[] = {
+ { SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, MOD_Op0Add, MOD_Op1Add}, 64, 0, 0, 2, {0x00, 0x00, 0}, 0, 1, 470 }
};
-static const x86_insn_info sse5prot_insn[] = {
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0x40}, 0, 3, 56 },
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0x40}, 0, 3, 88 },
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7B, 0x40}, 0, 3, 77 }
-};
-
-static const x86_insn_info sse5psh_insn[] = {
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0x44}, 0, 3, 56 },
- { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0x44}, 0, 3, 88 }
-};
-
static const x86_insn_info movbe_insn[] = {
- { 0, 0, CPU_MOVBE, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 3, {0x0F, 0x38, 0xF0}, 0, 2, 437 },
- { 0, 0, CPU_MOVBE, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 3, {0x0F, 0x38, 0xF1}, 0, 2, 439 },
- { 0, 0, CPU_386, CPU_MOVBE, 0, {0, 0, 0}, 32, 0, 0, 0, 3, {0x0F, 0x38, 0xF0}, 0, 2, 345 },
- { 0, 0, CPU_386, CPU_MOVBE, 0, {0, 0, 0}, 32, 0, 0, 0, 3, {0x0F, 0x38, 0xF1}, 0, 2, 323 },
- { 0, ONLY_64, CPU_MOVBE, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 3, {0x0F, 0x38, 0xF0}, 0, 2, 441 },
- { 0, ONLY_64, CPU_MOVBE, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 3, {0x0F, 0x38, 0xF1}, 0, 2, 325 }
+ { SUF_Z, 0, CPU_MOVBE, 0, 0, {0, 0, 0}, 16, 0, 0, 3, {0x0F, 0x38, 0xF0}, 0, 2, 405 },
+ { SUF_Z, 0, CPU_MOVBE, 0, 0, {0, 0, 0}, 16, 0, 0, 3, {0x0F, 0x38, 0xF1}, 0, 2, 407 },
+ { SUF_Z, 0, CPU_386, CPU_MOVBE, 0, {0, 0, 0}, 32, 0, 0, 3, {0x0F, 0x38, 0xF0}, 0, 2, 311 },
+ { SUF_Z, 0, CPU_386, CPU_MOVBE, 0, {0, 0, 0}, 32, 0, 0, 3, {0x0F, 0x38, 0xF1}, 0, 2, 289 },
+ { SUF_Z, ONLY_64, CPU_MOVBE, 0, 0, {0, 0, 0}, 64, 0, 0, 3, {0x0F, 0x38, 0xF0}, 0, 2, 409 },
+ { SUF_Z, ONLY_64, CPU_MOVBE, 0, 0, {0, 0, 0}, 64, 0, 0, 3, {0x0F, 0x38, 0xF1}, 0, 2, 291 }
};
static const x86_insn_info now3d_insn[] = {
- { 0, 0, CPU_3DNow, 0, 0, {MOD_Imm8, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x0F, 0}, 0, 2, 234 }
+ { SUF_Z, 0, CPU_3DNow, 0, 0, {MOD_Imm8, 0, 0}, 0, 0, 0, 2, {0x0F, 0x0F, 0}, 0, 2, 185 }
};
static const x86_insn_info cmpxchg16b_insn[] = {
- { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0xC7, 0}, 1, 1, 540 }
+ { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC7, 0}, 1, 1, 528 }
};
static const x86_insn_info invlpga_insn[] = {
- { 0, 0, CPU_SVM, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x01, 0xDF}, 0, 0, 0 },
- { 0, 0, CPU_386, CPU_SVM, 0, {0, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x01, 0xDF}, 0, 2, 471 }
+ { SUF_Z, 0, CPU_SVM, 0, 0, {0, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0xDF}, 0, 0, 0 },
+ { SUF_Z, 0, CPU_386, CPU_SVM, 0, {0, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0xDF}, 0, 2, 453 }
};
static const x86_insn_info skinit_insn[] = {
- { 0, 0, CPU_SVM, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x01, 0xDE}, 0, 0, 0 },
- { 0, 0, CPU_SVM, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x01, 0xDE}, 0, 1, 610 }
+ { SUF_Z, 0, CPU_SVM, 0, 0, {0, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0xDE}, 0, 0, 0 },
+ { SUF_Z, 0, CPU_SVM, 0, 0, {0, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0xDE}, 0, 1, 579 }
};
static const x86_insn_info svm_rax_insn[] = {
- { 0, 0, CPU_SVM, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x01, 0x00}, 0, 0, 0 },
- { 0, 0, CPU_SVM, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x01, 0x00}, 0, 1, 471 }
+ { SUF_Z, 0, CPU_SVM, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0x00}, 0, 0, 0 },
+ { SUF_Z, 0, CPU_SVM, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0x00}, 0, 1, 453 }
};
static const x86_insn_info padlock_insn[] = {
- { 0, 0, CPU_PadLock, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_Op1Add}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 0, 0 }
+ { SUF_Z, 0, CPU_PadLock, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_Op1Add}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 0, 0 }
};
static const x86_insn_info cyrixmmx_insn[] = {
- { 0, 0, CPU_Cyrix, CPU_MMX, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 234 }
+ { SUF_Z, 0, CPU_Cyrix, CPU_MMX, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 185 }
};
static const x86_insn_info pmachriw_insn[] = {
- { 0, 0, CPU_Cyrix, CPU_MMX, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x5E, 0}, 0, 2, 303 }
+ { SUF_Z, 0, CPU_Cyrix, CPU_MMX, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x5E, 0}, 0, 2, 269 }
};
static const x86_insn_info rdwrshr_insn[] = {
- { 0, 0, CPU_686, CPU_Cyrix, CPU_SMM, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x36, 0}, 0, 1, 26 }
+ { SUF_Z, 0, CPU_686, CPU_Cyrix, CPU_SMM, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x36, 0}, 0, 1, 26 }
};
static const x86_insn_info rsdc_insn[] = {
- { 0, 0, CPU_486, CPU_Cyrix, CPU_SMM, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x79, 0}, 0, 2, 493 }
+ { SUF_Z, 0, CPU_486, CPU_Cyrix, CPU_SMM, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x79, 0}, 0, 2, 497 }
};
static const x86_insn_info cyrixsmm_insn[] = {
- { 0, 0, CPU_486, CPU_Cyrix, CPU_SMM, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 494 }
+ { SUF_Z, 0, CPU_486, CPU_Cyrix, CPU_SMM, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 498 }
};
static const x86_insn_info svdc_insn[] = {
- { 0, 0, CPU_486, CPU_Cyrix, CPU_SMM, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x78, 0}, 0, 2, 571 }
+ { SUF_Z, 0, CPU_486, CPU_Cyrix, CPU_SMM, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x78, 0}, 0, 2, 549 }
};
static const x86_insn_info ibts_insn[] = {
- { 0, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0xA7, 0}, 0, 2, 246 },
- { 0, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0xA7, 0}, 0, 2, 252 }
+ { SUF_Z, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA7, 0}, 0, 2, 212 },
+ { SUF_Z, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA7, 0}, 0, 2, 218 }
};
static const x86_insn_info umov_insn[] = {
- { 0, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x10, 0}, 0, 2, 309 },
- { 0, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x11, 0}, 0, 2, 246 },
- { 0, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x11, 0}, 0, 2, 252 },
- { 0, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x12, 0}, 0, 2, 311 },
- { 0, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x13, 0}, 0, 2, 150 },
- { 0, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x13, 0}, 0, 2, 153 }
+ { SUF_Z, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x10, 0}, 0, 2, 275 },
+ { SUF_Z, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0x11, 0}, 0, 2, 212 },
+ { SUF_Z, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0x11, 0}, 0, 2, 218 },
+ { SUF_Z, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x12, 0}, 0, 2, 277 },
+ { SUF_Z, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0x13, 0}, 0, 2, 98 },
+ { SUF_Z, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0x13, 0}, 0, 2, 101 }
};
static const x86_insn_info xbts_insn[] = {
- { 0, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0xA6, 0}, 0, 2, 437 },
- { 0, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0xA6, 0}, 0, 2, 345 }
+ { SUF_Z, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA6, 0}, 0, 2, 405 },
+ { SUF_Z, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA6, 0}, 0, 2, 311 }
};
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