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Side by Side Diff: third_party/yasm/patched-yasm/x86insns.c

Issue 6170009: Update our yasm copy to yasm 1.1.0 (Part 1: yasm side)... (Closed) Base URL: svn://svn.chromium.org/chrome/trunk/deps/
Patch Set: Created 9 years, 11 months ago
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1 /* Generated by gen_x86_insn.py r2193, do not edit */ 1 /* Generated by gen_x86_insn.py r2346, do not edit */
2 static const x86_info_operand insn_operands[] = { 2 static const x86_info_operand insn_operands[] = {
3 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 3 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
4 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 4 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
5 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 5 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
6 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 6 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
7 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 7 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
8 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 8 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
9 {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 9 {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
10 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 10 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
11 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 11 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
12 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 12 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
13 {OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 13 {OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
14 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 14 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
15 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 15 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
16 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 16 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
17 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 17 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
18 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 18 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
19 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 19 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
20 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 20 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
21 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 21 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
22 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 22 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
23 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 23 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
24 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 24 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
25 {OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 25 {OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
26 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 26 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
27 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 27 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
28 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 28 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
29 {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 29 {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
30 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 30 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
31 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 31 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
32 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 32 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
33 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
34 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
35 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
36 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
37 {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
38 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
39 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
40 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
41 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
42 {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
43 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
44 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
33 {OPT_Mem, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 45 {OPT_Mem, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
34 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 46 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
35 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None}, 47 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
36 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 48 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
37 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 49 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
38 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 50 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
39 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 51 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
40 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 52 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
41 {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 53 {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
42 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 54 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
43 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 55 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
44 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 56 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
45 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 57 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
46 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 58 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
47 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 59 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
48 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 60 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
49 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 61 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
50 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 62 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
51 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 63 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
52 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 64 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
53 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 65 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
54 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None}, 66 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
55 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 67 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
56 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 68 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
57 {OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 69 {OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
58 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None}, 70 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
59 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
60 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 71 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
61 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 72 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
62 {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None}, 73 {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
74 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
75 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
76 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
77 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
78 {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
63 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None}, 79 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
64 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 80 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
65 {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 81 {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
66 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 82 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
67 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 83 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
84 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
85 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
86 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
87 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
88 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
89 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
90 {OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
91 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
68 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 92 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
69 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 93 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
70 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 94 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
71 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
72 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
73 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
74 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
75 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
76 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
77 {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
78 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
79 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
80 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
81 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
82 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
83 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
84 {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
85 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
86 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
87 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
88 {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
89 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
90 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
91 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
92 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
93 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
94 {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
95 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
96 {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
97 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
98 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
99 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
100 {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
101 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
102 {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
103 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
104 {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
105 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
106 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
107 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
108 {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
109 {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
110 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
111 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
112 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
113 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
114 {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
115 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
116 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
117 {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
118 {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
119 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
120 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
121 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
122 {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
123 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
124 {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
125 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
126 {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
127 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
128 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
129 {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
130 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
131 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
132 {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
133 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
134 {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
135 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
136 {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
137 {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
138 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
139 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
140 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
141 {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
142 {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
143 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_DREX, OPAP_None},
144 {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
145 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
146 {OPT_SIMDRegMatch0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
147 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None}, 95 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
148 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 96 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
149 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 97 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
150 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None}, 98 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
151 {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 99 {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
152 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 100 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
153 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 101 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
154 {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 102 {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
155 {OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None}, 103 {OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
156 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 104 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
(...skipping 58 matching lines...) Expand 10 before | Expand all | Expand 10 after
215 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 163 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
216 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 164 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
217 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 165 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
218 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 166 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
219 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 167 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
220 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 168 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
221 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 169 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
222 {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 170 {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
223 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 171 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
224 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 172 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
173 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
174 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
175 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
225 {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 176 {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
226 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 177 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
227 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 178 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
228 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 179 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
229 {OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 180 {OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
230 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 181 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
231 {OPT_Mem, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 182 {OPT_Mem, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
232 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 183 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
233 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 184 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
234 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 185 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
235 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 186 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
236 {OPT_XMM0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None}, 187 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
237 {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 188 {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
238 {OPT_SIMDRM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 189 {OPT_SIMDRM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
239 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 190 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
240 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 191 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
241 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 192 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
242 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 193 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
243 {OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 194 {OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
244 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None}, 195 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
245 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 196 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
197 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
198 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
199 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
200 {OPT_Mem, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
201 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
202 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
203 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
204 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
205 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
206 {OPT_Mem, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
207 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
208 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
246 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None}, 209 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
247 {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 210 {OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
248 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 211 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
212 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
213 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
214 {OPT_XMM0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
249 {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 215 {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
250 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 216 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
251 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 217 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
252 {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 218 {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
253 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 219 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
254 {OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None}, 220 {OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
255 {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 221 {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
256 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 222 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
257 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 223 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
258 {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 224 {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
(...skipping 169 matching lines...) Expand 10 before | Expand all | Expand 10 after
428 {OPT_DRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 394 {OPT_DRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
429 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 395 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
430 {OPT_DRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 396 {OPT_DRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
431 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 397 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
432 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 398 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
433 {OPT_DRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 399 {OPT_DRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
434 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 400 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
435 {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 401 {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
436 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 402 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
437 {OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 403 {OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
404 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
405 {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
438 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 406 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
439 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 407 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
440 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 408 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
441 {OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 409 {OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
442 {OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 410 {OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
443 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 411 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
444 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 412 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
445 {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 413 {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
446 {OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None}, 414 {OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
447 {OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 415 {OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None},
448 {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 416 {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
449 {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 417 {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
450 {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}, 418 {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
451 {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 419 {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
452 {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None}, 420 {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
453 {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 421 {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
422 {OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
423 {OPT_Creg, OPS_32, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
424 {OPT_Imm, OPS_Any, 0, 0, OPTM_Short, OPA_JmpRel, OPAP_None},
425 {OPT_Creg, OPS_32, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
454 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 426 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
455 {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 427 {OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
428 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
429 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
456 {OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 430 {OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
457 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 431 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
432 {OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
433 {OPT_Creg, OPS_64, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
434 {OPT_Imm, OPS_Any, 0, 0, OPTM_Short, OPA_JmpRel, OPAP_None},
435 {OPT_Creg, OPS_64, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
436 {OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
437 {OPT_Creg, OPS_16, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
438 {OPT_Imm, OPS_Any, 0, 0, OPTM_Short, OPA_JmpRel, OPAP_None},
439 {OPT_Creg, OPS_16, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
458 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 440 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
459 {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 441 {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
460 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 442 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
461 {OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None}, 443 {OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
462 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 444 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
463 {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 445 {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
464 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 446 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
465 {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}, 447 {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
466 {OPT_Dreg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 448 {OPT_Dreg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
467 {OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None}, 449 {OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
(...skipping 18 matching lines...) Expand all
486 {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None}, 468 {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
487 {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None}, 469 {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
488 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None}, 470 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
489 {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None}, 471 {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
490 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 472 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
491 {OPT_Mem, OPS_Any, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 473 {OPT_Mem, OPS_Any, 1, 0, OPTM_None, OPA_EA, OPAP_None},
492 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 474 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
493 {OPT_Mem, OPS_Any, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 475 {OPT_Mem, OPS_Any, 1, 0, OPTM_None, OPA_EA, OPAP_None},
494 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 476 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
495 {OPT_Mem, OPS_Any, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 477 {OPT_Mem, OPS_Any, 1, 0, OPTM_None, OPA_EA, OPAP_None},
496 {OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None},
497 {OPT_Mem, OPS_80, 1, 0, OPTM_None, OPA_EA, OPAP_None},
498 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 478 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
499 {OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 479 {OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None},
500 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 480 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
501 {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 481 {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
502 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 482 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
503 {OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 483 {OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None},
504 {OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 484 {OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None},
505 {OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None}, 485 {OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
506 {OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 486 {OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None},
507 {OPT_Imm1, OPS_8, 1, 0, OPTM_None, OPA_None, OPAP_None}, 487 {OPT_Imm1, OPS_8, 1, 0, OPTM_None, OPA_None, OPAP_None},
508 {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 488 {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
509 {OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None}, 489 {OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
510 {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 490 {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
511 {OPT_Imm1, OPS_8, 1, 0, OPTM_None, OPA_None, OPAP_None}, 491 {OPT_Imm1, OPS_8, 1, 0, OPTM_None, OPA_None, OPAP_None},
512 {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 492 {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
513 {OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None}, 493 {OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
514 {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 494 {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
515 {OPT_Imm1, OPS_8, 1, 0, OPTM_None, OPA_None, OPAP_None}, 495 {OPT_Imm1, OPS_8, 1, 0, OPTM_None, OPA_None, OPAP_None},
516 {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 496 {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
517 {OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None}, 497 {OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
518 {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 498 {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
519 {OPT_Imm1, OPS_8, 1, 0, OPTM_None, OPA_None, OPAP_None}, 499 {OPT_Imm1, OPS_8, 1, 0, OPTM_None, OPA_None, OPAP_None},
500 {OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None},
501 {OPT_Mem, OPS_80, 1, 0, OPTM_None, OPA_EA, OPAP_None},
502 {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_JmpFar, OPAP_None},
503 {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_JmpFar, OPAP_None},
504 {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_JmpFar, OPAP_None},
505 {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_JmpFar, OPAP_None},
506 {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_JmpFar, OPAP_None},
507 {OPT_Imm, OPS_BITS, 1, 0, OPTM_None, OPA_JmpFar, OPAP_None},
520 {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 508 {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
521 {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8}, 509 {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
522 {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}, 510 {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
523 {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8}, 511 {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
524 {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None}, 512 {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
525 {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8}, 513 {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
526 {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 514 {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
527 {OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None}, 515 {OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
528 {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 516 {OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
529 {OPT_Imm, OPS_16, 0, 0, OPTM_None, OPA_Imm, OPAP_SImm8}, 517 {OPT_Imm, OPS_16, 0, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
530 {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 518 {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
531 {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8}, 519 {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
532 {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 520 {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
533 {OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None}, 521 {OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
534 {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 522 {OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
535 {OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_Imm, OPAP_SImm8}, 523 {OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
536 {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 524 {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
537 {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8}, 525 {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
538 {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 526 {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
539 {OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None}, 527 {OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
540 {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 528 {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
541 {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8}, 529 {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
542 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 530 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
543 {OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 531 {OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
532 {OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
533 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
544 {OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 534 {OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
545 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 535 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
546 {OPT_Mem, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 536 {OPT_Mem, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
547 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 537 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
548 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 538 {OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
549 {OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 539 {OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
550 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 540 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
551 {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 541 {OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
552 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 542 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
553 {OPT_SIMDRM, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 543 {OPT_SIMDRM, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
554 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 544 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
555 {OPT_SIMDRM, OPS_256, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 545 {OPT_SIMDRM, OPS_256, 0, 0, OPTM_None, OPA_EA, OPAP_None},
556 {OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
557 {OPT_Creg, OPS_16, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
558 {OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
559 {OPT_Creg, OPS_32, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
560 {OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
561 {OPT_Creg, OPS_64, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
562 {OPT_Imm, OPS_Any, 0, 0, OPTM_Short, OPA_JmpRel, OPAP_None},
563 {OPT_Creg, OPS_16, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
564 {OPT_Imm, OPS_Any, 0, 0, OPTM_Short, OPA_JmpRel, OPAP_None},
565 {OPT_Creg, OPS_32, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
566 {OPT_Imm, OPS_Any, 0, 0, OPTM_Short, OPA_JmpRel, OPAP_None},
567 {OPT_Creg, OPS_64, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
568 {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 546 {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
569 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 547 {OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
570 {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}, 548 {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
571 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 549 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
572 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 550 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
573 {OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 551 {OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
574 {OPT_Mem, OPS_80, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 552 {OPT_Mem, OPS_80, 1, 0, OPTM_None, OPA_EA, OPAP_None},
575 {OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None}, 553 {OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None},
554 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
555 {OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
556 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
557 {OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
576 {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 558 {OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
577 {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 559 {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
578 {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}, 560 {OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
579 {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 561 {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
580 {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None}, 562 {OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
581 {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 563 {OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
564 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
565 {OPT_Mem, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
566 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
567 {OPT_Mem, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
582 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 568 {OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
583 {OPT_Mem, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None}, 569 {OPT_Mem, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
584 {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 570 {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
585 {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 571 {OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
586 {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_A16}, 572 {OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_A16},
587 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None}, 573 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
588 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None}, 574 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
589 {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 575 {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
590 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None}, 576 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
591 {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 577 {OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
592 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None}, 578 {OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
593 {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 579 {OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
594 {OPT_Mem, OPS_80, 0, 0, OPTM_None, OPA_EA, OPAP_None},
595 {OPT_Mem, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 580 {OPT_Mem, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
596 {OPT_Mem, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 581 {OPT_Mem, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
597 {OPT_Mem, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 582 {OPT_MemEAX, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
583 {OPT_Mem, OPS_80, 0, 0, OPTM_None, OPA_EA, OPAP_None},
598 {OPT_SS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None}, 584 {OPT_SS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
599 {OPT_SS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 585 {OPT_SS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
600 {OPT_SS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}, 586 {OPT_SS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
601 {OPT_DS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None}, 587 {OPT_DS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
602 {OPT_DS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 588 {OPT_DS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
603 {OPT_DS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}, 589 {OPT_DS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
604 {OPT_ES, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None}, 590 {OPT_ES, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
605 {OPT_ES, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 591 {OPT_ES, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
606 {OPT_ES, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}, 592 {OPT_ES, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
607 {OPT_FS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None}, 593 {OPT_FS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
608 {OPT_FS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 594 {OPT_FS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
609 {OPT_FS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}, 595 {OPT_FS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
610 {OPT_GS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None}, 596 {OPT_GS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
611 {OPT_GS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 597 {OPT_GS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
612 {OPT_GS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}, 598 {OPT_GS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
613 {OPT_MemEAX, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
614 {OPT_Mem, OPS_Any, 0, 0, OPTM_None, OPA_EA, OPAP_None}, 599 {OPT_Mem, OPS_Any, 0, 0, OPTM_None, OPA_EA, OPAP_None},
615 {OPT_ImmNotSegOff, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None}, 600 {OPT_ImmNotSegOff, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
616 {OPT_ImmNotSegOff, OPS_16, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None}, 601 {OPT_ImmNotSegOff, OPS_16, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
617 {OPT_ImmNotSegOff, OPS_32, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None}, 602 {OPT_ImmNotSegOff, OPS_32, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
618 {OPT_Imm, OPS_16, 0, 0, OPTM_Near, OPA_JmpRel, OPAP_None}, 603 {OPT_Imm, OPS_16, 0, 0, OPTM_Near, OPA_JmpRel, OPAP_None},
619 {OPT_Imm, OPS_32, 0, 0, OPTM_Near, OPA_JmpRel, OPAP_None}, 604 {OPT_Imm, OPS_32, 0, 0, OPTM_Near, OPA_JmpRel, OPAP_None},
620 {OPT_Imm, OPS_Any, 0, 0, OPTM_Near, OPA_JmpRel, OPAP_None}, 605 {OPT_Imm, OPS_Any, 0, 0, OPTM_Near, OPA_JmpRel, OPAP_None},
606 {OPT_Reg, OPS_BITS, 0, 0, OPTM_None, OPA_EA, OPAP_None},
621 {OPT_RM, OPS_16, 0, 0, OPTM_Near, OPA_EA, OPAP_None}, 607 {OPT_RM, OPS_16, 0, 0, OPTM_Near, OPA_EA, OPAP_None},
622 {OPT_RM, OPS_32, 0, 0, OPTM_Near, OPA_EA, OPAP_None}, 608 {OPT_RM, OPS_32, 0, 0, OPTM_Near, OPA_EA, OPAP_None},
623 {OPT_RM, OPS_64, 0, 0, OPTM_Near, OPA_EA, OPAP_None}, 609 {OPT_RM, OPS_64, 0, 0, OPTM_Near, OPA_EA, OPAP_None},
624 {OPT_Mem, OPS_Any, 0, 0, OPTM_Near, OPA_EA, OPAP_None}, 610 {OPT_Mem, OPS_Any, 0, 0, OPTM_Near, OPA_EA, OPAP_None},
625 {OPT_Mem, OPS_16, 0, 0, OPTM_Far, OPA_EA, OPAP_None}, 611 {OPT_Mem, OPS_16, 0, 0, OPTM_Far, OPA_EA, OPAP_None},
626 {OPT_Mem, OPS_32, 0, 0, OPTM_Far, OPA_EA, OPAP_None}, 612 {OPT_Mem, OPS_32, 0, 0, OPTM_Far, OPA_EA, OPAP_None},
627 {OPT_Mem, OPS_64, 0, 0, OPTM_Far, OPA_EA, OPAP_None}, 613 {OPT_Mem, OPS_64, 0, 0, OPTM_Far, OPA_EA, OPAP_None},
628 {OPT_Mem, OPS_Any, 0, 0, OPTM_Far, OPA_EA, OPAP_None}, 614 {OPT_Mem, OPS_Any, 0, 0, OPTM_Far, OPA_EA, OPAP_None},
629 {OPT_Imm, OPS_16, 0, 0, OPTM_Far, OPA_JmpFar, OPAP_None}, 615 {OPT_Imm, OPS_16, 0, 0, OPTM_Far, OPA_JmpFar, OPAP_None},
630 {OPT_Imm, OPS_32, 0, 0, OPTM_Far, OPA_JmpFar, OPAP_None}, 616 {OPT_Imm, OPS_32, 0, 0, OPTM_Far, OPA_JmpFar, OPAP_None},
631 {OPT_Imm, OPS_Any, 0, 0, OPTM_Far, OPA_JmpFar, OPAP_None}, 617 {OPT_Imm, OPS_Any, 0, 0, OPTM_Far, OPA_JmpFar, OPAP_None},
632 {OPT_Imm, OPS_16, 0, 0, OPTM_None, OPA_JmpFar, OPAP_None}, 618 {OPT_Imm, OPS_16, 0, 0, OPTM_None, OPA_JmpFar, OPAP_None},
633 {OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_JmpFar, OPAP_None}, 619 {OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_JmpFar, OPAP_None},
634 {OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpFar, OPAP_None}, 620 {OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpFar, OPAP_None},
635 {OPT_Reg, OPS_80, 0, 0, OPTM_To, OPA_Op1Add, OPAP_None}, 621 {OPT_Reg, OPS_80, 0, 0, OPTM_To, OPA_Op1Add, OPAP_None},
636 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Op1Add, OPAP_None}, 622 {OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Op1Add, OPAP_None},
637 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Op1Add, OPAP_None}, 623 {OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Op1Add, OPAP_None},
624 {OPT_Mem, OPS_BITS, 1, 0, OPTM_None, OPA_EA, OPAP_None},
638 {OPT_Imm, OPS_16, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None}, 625 {OPT_Imm, OPS_16, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
639 {OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None}, 626 {OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
640 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_SImm, OPAP_None}, 627 {OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_SImm, OPAP_None},
641 {OPT_Imm, OPS_BITS, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8}, 628 {OPT_Imm, OPS_BITS, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
642 {OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_SImm, OPAP_None}, 629 {OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
643 {OPT_CS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None}, 630 {OPT_CS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
644 {OPT_CS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None}, 631 {OPT_CS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
645 {OPT_CS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None} 632 {OPT_CS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}
646 }; 633 };
647 634
648 static const x86_insn_info empty_insn[] = { 635 static const x86_insn_info empty_insn[] = {
649 { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0 } 636 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0 }
650 }; 637 };
651 638
652 static const x86_insn_info not64_insn[] = { 639 static const x86_insn_info not64_insn[] = {
653 { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0 } 640 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0 }
654 }; 641 };
655 642
656 static const x86_insn_info onebyte_insn[] = { 643 static const x86_insn_info onebyte_insn[] = {
657 { 0, 0, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, MOD_DOpS64R}, 0, 0, 0, 0, 1, {0x0 0, 0, 0}, 0, 0, 0 } 644 { SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, MOD_DOpS64R}, 0, 0, 0, 1, {0x0 0, 0, 0}, 0, 0, 0 }
658 }; 645 };
659 646
660 static const x86_insn_info onebyte_prefix_insn[] = { 647 static const x86_insn_info onebyte_prefix_insn[] = {
661 { 0, 0, 0, 0, 0, {MOD_PreAdd, MOD_Op0Add, 0}, 0, 0, 0x00, 0, 1, {0x00, 0, 0} , 0, 0, 0 } 648 { SUF_Z, 0, 0, 0, 0, {MOD_PreAdd, MOD_Op0Add, 0}, 0, 0, 0x00, 1, {0x00, 0, 0} , 0, 0, 0 }
662 }; 649 };
663 650
664 static const x86_insn_info twobyte_insn[] = { 651 static const x86_insn_info twobyte_insn[] = {
665 { SUF_L|SUF_Q, 0, 0, 0, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0x00 , 0x00, 0}, 0, 0, 0 } 652 { SUF_L|SUF_Q|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x 00, 0x00, 0}, 0, 0, 0 }
666 }; 653 };
667 654
668 static const x86_insn_info threebyte_insn[] = { 655 static const x86_insn_info threebyte_insn[] = {
669 { 0, 0, 0, 0, 0, {MOD_Op0Add, MOD_Op1Add, MOD_Op2Add}, 0, 0, 0, 0, 3, {0x00, 0x00, 0x00}, 0, 0, 0 } 656 { SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, MOD_Op1Add, MOD_Op2Add}, 0, 0, 0, 3, {0x00, 0x00, 0x00}, 0, 0, 0 }
670 }; 657 };
671 658
672 static const x86_insn_info onebytemem_insn[] = { 659 static const x86_insn_info onebytemem_insn[] = {
673 { SUF_L|SUF_Q|SUF_S, 0, 0, 0, 0, {MOD_SpAdd, MOD_Op0Add, 0}, 0, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 611 } 660 { SUF_L|SUF_Q|SUF_S|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, MOD_Op0Add, 0}, 0, 0, 0, 1 , {0x00, 0, 0}, 0, 1, 596 }
674 }; 661 };
675 662
676 static const x86_insn_info twobytemem_insn[] = { 663 static const x86_insn_info twobytemem_insn[] = {
677 { SUF_L|SUF_Q|SUF_S|SUF_W, 0, 0, 0, 0, {MOD_SpAdd, MOD_Op0Add, MOD_Op1Add}, 0, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 1, 488 } 664 { SUF_L|SUF_Q|SUF_S|SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, MOD_Op0Add, MOD_Op1A dd}, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 1, 470 }
678 }; 665 };
679 666
680 static const x86_insn_info mov_insn[] = { 667 static const x86_insn_info mov_insn[] = {
681 { SUF_B, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 351 }, 668 { SUF_B|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 31 7 },
682 { SUF_W, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 353 }, 669 { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 319 },
683 { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 355 }, 670 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 321 },
684 { SUF_B, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 357 }, 671 { SUF_B|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 3 23 },
685 { SUF_W, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 359 }, 672 { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 325 },
686 { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 361 }, 673 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 327 },
687 { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 327 }, 674 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 293 },
688 { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 329 }, 675 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 295 } ,
689 { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 331 }, 676 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 297 } ,
690 { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 333 }, 677 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 299 } ,
691 { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 335 }, 678 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 301 },
692 { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 337 }, 679 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 303 } ,
693 { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 339 }, 680 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 305 } ,
694 { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 341 }, 681 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 307 } ,
695 { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x88, 0xA2, 0}, 0, 2, 363 }, 682 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x88, 0xA2, 0}, 0, 2, 329 },
696 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 365 } , 683 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 33 1 },
697 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 367 }, 684 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 333 },
698 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 369 }, 685 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 335 },
699 { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x88, 0, 0}, 0, 2, 309 }, 686 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x88, 0, 0}, 0, 2, 275 },
700 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x89, 0, 0}, 0, 2, 246 }, 687 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x89, 0, 0}, 0, 2, 212 } ,
701 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x89, 0, 0}, 0, 2, 25 2 }, 688 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x89, 0, 0}, 0, 2, 218 },
702 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x89, 0, 0}, 0, 2, 25 8 }, 689 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x89, 0, 0}, 0, 2, 224 },
703 { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x8A, 0xA0, 0}, 0, 2, 371 }, 690 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8A, 0xA0, 0}, 0, 2, 337 },
704 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 373 } , 691 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 33 9 },
705 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 375 }, 692 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 341 },
706 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 377 }, 693 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 343 },
707 { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x8A, 0, 0}, 0, 2, 311 }, 694 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8A, 0, 0}, 0, 2, 277 },
708 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x8B, 0, 0}, 0, 2, 150 }, 695 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x8B, 0, 0}, 0, 2, 98 },
709 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x8B, 0, 0}, 0, 2, 15 3 }, 696 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8B, 0, 0}, 0, 2, 101 },
710 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x8B, 0, 0}, 0, 2, 15 6 }, 697 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x8B, 0, 0}, 0, 2, 104 },
711 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 379 }, 698 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 345 },
712 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 381 }, 699 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 347 } ,
713 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 38 3 }, 700 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 349 },
714 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 38 5 }, 701 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 351 },
715 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 387 }, 702 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 353 },
716 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 382 }, 703 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 348 },
717 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 384 }, 704 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 350 },
718 { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xB0, 0, 0}, 0, 2, 389 }, 705 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xB0, 0, 0}, 0, 2, 355 },
719 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 391 }, 706 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 357 } ,
720 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 39 3 }, 707 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 359 },
721 { GAS_ILLEGAL, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 395 }, 708 { GAS_ILLEGAL|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 361 },
722 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xB8, 0xC7, 0}, 0, 2, 397 }, 709 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xB8, 0xC7, 0}, 0, 2, 363 },
723 { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xC6, 0, 0}, 0, 2, 399 }, 710 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xC6, 0, 0}, 0, 2, 365 },
724 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 401 }, 711 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 367 } ,
725 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 40 3 }, 712 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 369 },
726 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 40 5 }, 713 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 371 },
727 { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xC6, 0, 0}, 0, 2, 407 }, 714 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xC6, 0, 0}, 0, 2, 373 },
728 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 409 }, 715 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 375 } ,
729 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 41 1 }, 716 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 377 },
730 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 41 3 }, 717 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 379 },
731 { SUF_L, NOT_64, CPU_586, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x22 , 0}, 0, 2, 415 }, 718 { SUF_L|SUF_Z, NOT_64, CPU_586, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0 x22, 0}, 0, 2, 381 },
732 { SUF_L, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x22 , 0}, 0, 2, 417 }, 719 { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0 x22, 0}, 0, 2, 383 },
733 { SUF_Q, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, 419 }, 720 { SUF_Q|SUF_Z, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, 385 },
734 { SUF_L, NOT_64, CPU_586, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x20 , 0}, 0, 2, 421 }, 721 { SUF_L|SUF_Z, NOT_64, CPU_586, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0 x20, 0}, 0, 2, 387 },
735 { SUF_L, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x20 , 0}, 0, 2, 416 }, 722 { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0 x20, 0}, 0, 2, 382 },
736 { SUF_Q, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, 423 }, 723 { SUF_Q|SUF_Z, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, 389 },
737 { SUF_L, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x23 , 0}, 0, 2, 425 }, 724 { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0 x23, 0}, 0, 2, 391 },
738 { SUF_Q, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x23, 0}, 0, 2, 427 }, 725 { SUF_Q|SUF_Z, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x23, 0}, 0, 2, 393 },
739 { SUF_L, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x21 , 0}, 0, 2, 426 }, 726 { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0 x21, 0}, 0, 2, 392 },
740 { SUF_Q, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x21, 0}, 0, 2, 429 }, 727 { SUF_Q|SUF_Z, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x21, 0}, 0, 2, 395 },
741 { GAS_ONLY|SUF_Q, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x6F, 0 }, 0, 2, 234 }, 728 { GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x6F , 0}, 0, 2, 185 },
742 { GAS_ONLY|SUF_Q, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 281 }, 729 { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0 F, 0x6E, 0}, 0, 2, 247 },
743 { GAS_ONLY|SUF_Q, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x7F, 0 }, 0, 2, 317 }, 730 { GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x7F , 0}, 0, 2, 283 },
744 { GAS_ONLY|SUF_Q, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 283 }, 731 { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0 F, 0x7E, 0}, 0, 2, 249 },
745 { GAS_ONLY|SUF_Q, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 0, 2, {0x0F, 0x7 E, 0}, 0, 2, 64 }, 732 { GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2, 88 },
746 { GAS_ONLY|SUF_Q, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 0, 2, {0x0F, 0x7 E, 0}, 0, 2, 319 }, 733 { GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2, 285 },
747 { GAS_ONLY|SUF_Q, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 0, 2, {0x 0F, 0x6E, 0}, 0, 2, 287 }, 734 { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x6E, 0}, 0, 2, 253 },
748 { GAS_ONLY|SUF_Q, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0xD 6, 0}, 0, 2, 321 }, 735 { GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xD6, 0}, 0, 2, 287 },
749 { GAS_ONLY|SUF_Q, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 0, 2, {0x 0F, 0x7E, 0}, 0, 2, 219 } 736 { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x7E, 0}, 0, 2, 167 }
750 }; 737 };
751 738
752 static const x86_insn_info movabs_insn[] = { 739 static const x86_insn_info movabs_insn[] = {
753 { SUF_B, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 327 }, 740 { SUF_B|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 2 93 },
754 { SUF_W, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 32 9 }, 741 { SUF_W|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 295 },
755 { SUF_L, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 33 1 }, 742 { SUF_L|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 297 },
756 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 33 3 }, 743 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 299 },
757 { SUF_B, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 335 }, 744 { SUF_B|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 301 },
758 { SUF_W, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 33 7 }, 745 { SUF_W|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 303 },
759 { SUF_L, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 33 9 }, 746 { SUF_L|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 305 },
760 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 34 1 }, 747 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 307 },
761 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 34 3 } 748 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 309 }
762 }; 749 };
763 750
764 static const x86_insn_info movszx_insn[] = { 751 static const x86_insn_info movszx_insn[] = {
765 { SUF_B, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 545 }, 752 { SUF_B|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00 , 0}, 0, 2, 535 },
766 { SUF_B, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 495 }, 753 { SUF_B|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x0 0, 0}, 0, 2, 475 },
767 { SUF_B, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 499 }, 754 { SUF_B|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x0 0, 0}, 0, 2, 479 },
768 { SUF_W, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 497 }, 755 { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x0 1, 0}, 0, 2, 477 },
769 { SUF_W, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 547 } 756 { SUF_W|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x0 1, 0}, 0, 2, 537 }
770 }; 757 };
771 758
772 static const x86_insn_info movsxd_insn[] = { 759 static const x86_insn_info movsxd_insn[] = {
773 { SUF_L, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x63, 0, 0}, 0, 2, 58 5 } 760 { SUF_L|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x63, 0, 0}, 0, 2, 571 }
774 }; 761 };
775 762
776 static const x86_insn_info push_insn[] = { 763 static const x86_insn_info push_insn[] = {
777 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0x50, 0, 0}, 0, 1, 391 }, 764 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x50, 0, 0}, 0, 1, 357 } ,
778 { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x50, 0, 0}, 0, 1, 393 }, 765 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x50, 0, 0}, 0, 1, 359 },
779 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0x50, 0, 0}, 0, 1, 34 3 }, 766 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x50, 0, 0}, 0, 1, 309 },
780 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0xFF, 0, 0}, 6, 1, 273 }, 767 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xFF, 0, 0}, 6, 1, 239 },
781 { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xFF, 0, 0}, 6, 1, 269 }, 768 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 6, 1, 235 },
782 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0xFF, 0, 0}, 6, 1, 27 2 }, 769 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 6, 1, 238 },
783 { GAS_ILLEGAL, 0, CPU_186, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0x6A, 0, 0}, 0, 1, 152 }, 770 { GAS_ILLEGAL|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x6A, 0, 0}, 0, 1, 100 },
784 { GAS_ONLY, 0, CPU_186, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0x6A, 0, 0}, 0, 1, 637 }, 771 { GAS_ONLY|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x6A, 0, 0}, 0, 1, 624 },
785 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 1, {0x6A, 0x68, 0}, 0, 1 , 164 }, 772 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0x6A, 0x68, 0}, 0 , 1, 112 },
786 { GAS_ILLEGAL, NOT_64, CPU_186, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x6A, 0x68, 0}, 0, 1, 638 }, 773 { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_186, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x6A, 0x 68, 0}, 0, 1, 625 },
787 { SUF_W, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0x6A, 0x68, 0}, 0, 1 , 518 }, 774 { SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x6A, 0x68, 0}, 0 , 1, 506 },
788 { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x6A, 0x68, 0}, 0, 1, 520 }, 775 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6A, 0x68, 0 }, 0, 1, 508 },
789 { GAS_ILLEGAL, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0x68, 0, 0}, 0 , 1, 402 }, 776 { GAS_ILLEGAL|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x68, 0, 0} , 0, 1, 368 },
790 { GAS_ILLEGAL, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x68, 0, 0 }, 0, 1, 404 }, 777 { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x68, 0 , 0}, 0, 1, 370 },
791 { GAS_ILLEGAL, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 1, {0x68, 0, 0}, 0 , 1, 639 }, 778 { GAS_ILLEGAL|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0x68, 0, 0} , 0, 1, 626 },
792 { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 640 }, 779 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 627 },
793 { SUF_W, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 641 }, 780 { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 628 },
794 { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 642 }, 781 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 629 },
795 { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x16, 0, 0}, 0, 1, 595 }, 782 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x16, 0, 0}, 0, 1, 581 },
796 { SUF_W, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x16, 0, 0}, 0, 1, 596 }, 783 { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x16, 0, 0}, 0, 1, 582 },
797 { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x16, 0, 0}, 0, 1, 597 }, 784 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x16, 0, 0}, 0, 1, 583 },
798 { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 598 }, 785 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 584 },
799 { SUF_W, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 599 }, 786 { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 585 },
800 { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 600 }, 787 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 586 },
801 { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x06, 0, 0}, 0, 1, 601 }, 788 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x06, 0, 0}, 0, 1, 587 },
802 { SUF_W, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x06, 0, 0}, 0, 1, 602 }, 789 { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x06, 0, 0}, 0, 1, 588 },
803 { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x06, 0, 0}, 0, 1, 603 }, 790 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x06, 0, 0}, 0, 1, 589 },
804 { 0, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 604 }, 791 { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 590 },
805 { SUF_W, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 605 }, 792 { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 591 },
806 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 606 }, 793 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 592 },
807 { 0, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 607 }, 794 { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 593 },
808 { SUF_W, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 608 }, 795 { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 594 },
809 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 609 } 796 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 595 }
810 }; 797 };
811 798
812 static const x86_insn_info pop_insn[] = { 799 static const x86_insn_info pop_insn[] = {
813 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0x58, 0, 0}, 0, 1, 391 }, 800 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x58, 0, 0}, 0, 1, 357 } ,
814 { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x58, 0, 0}, 0, 1, 393 }, 801 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x58, 0, 0}, 0, 1, 359 },
815 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0x58, 0, 0}, 0, 1, 34 3 }, 802 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x58, 0, 0}, 0, 1, 309 },
816 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0x8F, 0, 0}, 0, 1, 273 }, 803 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x8F, 0, 0}, 0, 1, 239 },
817 { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x8F, 0, 0}, 0, 1, 269 }, 804 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8F, 0, 0}, 0, 1, 235 },
818 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0x8F, 0, 0}, 0, 1, 27 2 }, 805 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x8F, 0, 0}, 0, 1, 238 },
819 { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x17, 0, 0}, 0, 1, 595 }, 806 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x17, 0, 0}, 0, 1, 581 },
820 { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x17, 0, 0}, 0, 1, 596 }, 807 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x17, 0, 0}, 0, 1, 582 },
821 { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x17, 0, 0}, 0, 1, 5 97 }, 808 { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x17, 0, 0}, 0, 1, 583 },
822 { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 598 }, 809 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 584 },
823 { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 599 }, 810 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 585 },
824 { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 6 00 }, 811 { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 586 },
825 { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x07, 0, 0}, 0, 1, 601 }, 812 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x07, 0, 0}, 0, 1, 587 },
826 { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x07, 0, 0}, 0, 1, 602 }, 813 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x07, 0, 0}, 0, 1, 588 },
827 { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x07, 0, 0}, 0, 1, 6 03 }, 814 { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x07, 0, 0}, 0, 1, 589 },
828 { 0, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 604 }, 815 { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 590 },
829 { 0, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 605 }, 816 { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 59 1 },
830 { 0, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 606 }, 817 { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 59 2 },
831 { 0, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 607 }, 818 { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 593 },
832 { 0, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 608 }, 819 { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 59 4 },
833 { 0, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 609 } 820 { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 59 5 }
834 }; 821 };
835 822
836 static const x86_insn_info xchg_insn[] = { 823 static const x86_insn_info xchg_insn[] = {
837 { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x86, 0, 0}, 0, 2, 309 }, 824 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x86, 0, 0}, 0, 2, 275 },
838 { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x86, 0, 0}, 0, 2, 311 }, 825 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x86, 0, 0}, 0, 2, 277 },
839 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, 473 }, 826 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x90, 0, 0}, 0, 2, 455 } ,
840 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, 475 }, 827 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x90, 0, 0}, 0, 2, 457 } ,
841 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x87, 0, 0}, 0, 2, 246 }, 828 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x87, 0, 0}, 0, 2, 212 } ,
842 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x87, 0, 0}, 0, 2, 150 }, 829 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x87, 0, 0}, 0, 2, 98 },
843 { SUF_L, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x87, 0, 0}, 0, 2, 47 7 }, 830 { SUF_L|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x87, 0, 0}, 0, 2, 459 },
844 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, 47 9 }, 831 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x90, 0, 0}, 0, 2, 461 },
845 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, 48 1 }, 832 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x90, 0, 0}, 0, 2, 463 },
846 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x87, 0, 0}, 0, 2, 25 2 }, 833 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x87, 0, 0}, 0, 2, 218 },
847 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x87, 0, 0}, 0, 2, 15 3 }, 834 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x87, 0, 0}, 0, 2, 101 },
848 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, 483 }, 835 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, 465 },
849 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, 34 2 }, 836 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x90, 0, 0}, 0, 2, 308 },
850 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, 48 5 }, 837 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x90, 0, 0}, 0, 2, 467 },
851 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x87, 0, 0}, 0, 2, 25 8 }, 838 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x87, 0, 0}, 0, 2, 224 },
852 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x87, 0, 0}, 0, 2, 15 6 } 839 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x87, 0, 0}, 0, 2, 104 }
853 }; 840 };
854 841
855 static const x86_insn_info in_insn[] = { 842 static const x86_insn_info in_insn[] = {
856 { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xE4, 0, 0}, 0, 2, 458 }, 843 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xE4, 0, 0}, 0, 2, 440 },
857 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xE5, 0, 0}, 0, 2, 460 }, 844 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xE5, 0, 0}, 0, 2, 442 } ,
858 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xE5, 0, 0}, 0, 2, 56 7 }, 845 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE5, 0, 0}, 0, 2, 545 },
859 { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xEC, 0, 0}, 0, 2, 464 }, 846 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEC, 0, 0}, 0, 2, 446 },
860 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xED, 0, 0}, 0, 2, 466 }, 847 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xED, 0, 0}, 0, 2, 448 } ,
861 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xED, 0, 0}, 0, 2, 46 2 }, 848 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xED, 0, 0}, 0, 2, 444 },
862 { GAS_ONLY|SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xE4, 0, 0}, 0, 1, 3 }, 849 { GAS_ONLY|SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xE4, 0, 0}, 0, 1, 3 },
863 { GAS_ONLY|SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xE5, 0, 0}, 0, 1, 3 }, 850 { GAS_ONLY|SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xE5, 0, 0}, 0, 1, 3 },
864 { GAS_ONLY|SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xE5, 0, 0}, 0, 1, 3 }, 851 { GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE5, 0, 0}, 0, 1, 3 },
865 { GAS_ONLY|SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xEC, 0, 0}, 0, 1, 463 }, 852 { GAS_ONLY|SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEC, 0, 0}, 0, 1, 445 },
866 { GAS_ONLY|SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xED, 0, 0}, 0, 1, 463 }, 853 { GAS_ONLY|SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xED, 0, 0}, 0, 1, 445 },
867 { GAS_ONLY|SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xED, 0, 0}, 0, 1, 463 } 854 { GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xED, 0, 0}, 0, 1, 445 }
868 }; 855 };
869 856
870 static const x86_insn_info out_insn[] = { 857 static const x86_insn_info out_insn[] = {
871 { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xE6, 0, 0}, 0, 2, 457 }, 858 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xE6, 0, 0}, 0, 2, 439 },
872 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xE7, 0, 0}, 0, 2, 459 }, 859 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xE7, 0, 0}, 0, 2, 441 } ,
873 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xE7, 0, 0}, 0, 2, 46 1 }, 860 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE7, 0, 0}, 0, 2, 443 },
874 { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xEE, 0, 0}, 0, 2, 463 }, 861 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEE, 0, 0}, 0, 2, 445 },
875 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xEF, 0, 0}, 0, 2, 465 }, 862 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEF, 0, 0}, 0, 2, 447 } ,
876 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xEF, 0, 0}, 0, 2, 46 7 }, 863 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEF, 0, 0}, 0, 2, 449 },
877 { GAS_ONLY|SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xE6, 0, 0}, 0, 1, 3 }, 864 { GAS_ONLY|SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xE6, 0, 0}, 0, 1, 3 },
878 { GAS_ONLY|SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xE7, 0, 0}, 0, 1, 3 }, 865 { GAS_ONLY|SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xE7, 0, 0}, 0, 1, 3 },
879 { GAS_ONLY|SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xE7, 0, 0}, 0, 1, 3 }, 866 { GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE7, 0, 0}, 0, 1, 3 },
880 { GAS_ONLY|SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xEE, 0, 0}, 0, 1, 463 }, 867 { GAS_ONLY|SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEE, 0, 0}, 0, 1, 445 },
881 { GAS_ONLY|SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xEF, 0, 0}, 0, 1, 463 }, 868 { GAS_ONLY|SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEF, 0, 0}, 0, 1, 445 },
882 { GAS_ONLY|SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xEF, 0, 0}, 0, 1, 463 } 869 { GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEF, 0, 0}, 0, 1, 445 }
883 }; 870 };
884 871
885 static const x86_insn_info lea_insn[] = { 872 static const x86_insn_info lea_insn[] = {
886 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 487 }, 873 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 469 },
887 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 48 9 }, 874 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 471 },
888 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 49 1 } 875 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 473 }
889 }; 876 };
890 877
891 static const x86_insn_info ldes_insn[] = { 878 static const x86_insn_info ldes_insn[] = {
892 { SUF_W, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 0, 1, {0x00, 0, 0}, 0, 2, 487 }, 879 { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 1, {0x00, 0, 0} , 0, 2, 469 },
893 { SUF_L, NOT_64, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 0, 1, {0x00, 0 , 0}, 0, 2, 489 } 880 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 1, {0x00 , 0, 0}, 0, 2, 471 }
894 }; 881 };
895 882
896 static const x86_insn_info lfgss_insn[] = { 883 static const x86_insn_info lfgss_insn[] = {
897 { SUF_W, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 487 }, 884 { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00 , 0}, 0, 2, 469 },
898 { SUF_L, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 489 } 885 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x0 0, 0}, 0, 2, 471 }
899 }; 886 };
900 887
901 static const x86_insn_info arith_insn[] = { 888 static const x86_insn_info arith_insn[] = {
902 { SUF_B, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 0, 1, {0x04, 0, 0}, 0, 2, 458 }, 889 { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x04, 0, 0}, 0, 2 , 440 },
903 { SUF_W, 0, 0, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 16, 0, 0, 0, 2, {0x83, 0 xC0, 0x05}, 0, 2, 517 }, 890 { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 16, 0, 0, 2, {0x83 , 0xC0, 0x05}, 0, 2, 505 },
904 { SUF_L, 0, CPU_386, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 32, 0, 0, 0, 2, {0 x83, 0xC0, 0x05}, 0, 2, 519 }, 891 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 32, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, 507 },
905 { SUF_Q, ONLY_64, 0, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 64, 0, 0, 0, 2, {0 x83, 0xC0, 0x05}, 0, 2, 521 }, 892 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 64, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, 509 },
906 { SUF_B, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 0, 1, {0x80, 0, 0}, 0 , 2, 407 }, 893 { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0x80, 0, 0} , 0, 2, 373 },
907 { SUF_B, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 0, 1, {0x80, 0, 0}, 0 , 2, 399 }, 894 { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0x80, 0, 0} , 0, 2, 365 },
908 { SUF_W, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 0, 1, {0x83, 0, 0}, 0, 2, 523 }, 895 { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 1, {0x83, 0, 0 }, 0, 2, 511 },
909 { GAS_ILLEGAL, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 0, 1, {0x83, 0 x81, 0}, 0, 2, 525 }, 896 { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 1, {0x83 , 0x81, 0}, 0, 2, 513 },
910 { SUF_W, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 0, 1, {0x83, 0x81, 0 }, 0, 2, 527 }, 897 { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 1, {0x83, 0x81 , 0}, 0, 2, 515 },
911 { SUF_L, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 0, 1, {0x83, 0 , 0}, 0, 2, 529 }, 898 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 1, {0x83 , 0, 0}, 0, 2, 517 },
912 { GAS_ILLEGAL, NOT_64, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 531 }, 899 { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 519 },
913 { SUF_L, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 0, 1, {0x83, 0 x81, 0}, 0, 2, 533 }, 900 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 1, {0x83 , 0x81, 0}, 0, 2, 521 },
914 { SUF_Q, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 0, 1, {0x83, 0 , 0}, 0, 2, 535 }, 901 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 1, {0x83 , 0, 0}, 0, 2, 523 },
915 { SUF_Q, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 0, 1, {0x83, 0 x81, 0}, 0, 2, 537 }, 902 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 1, {0x83 , 0x81, 0}, 0, 2, 525 },
916 { SUF_B, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 0, 1, {0x00, 0, 0}, 0, 2, 309 }, 903 { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 2, 275 },
917 { SUF_W, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 0, 1, {0x01, 0, 0}, 0, 2, 246 }, 904 { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 1, {0x01, 0, 0}, 0, 2, 212 },
918 { SUF_L, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 0, 1, {0x01, 0, 0}, 0, 2, 252 }, 905 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 1, {0x01, 0, 0}, 0, 2, 218 },
919 { SUF_Q, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 64, 0, 0, 0, 1, {0x01, 0, 0}, 0, 2, 258 }, 906 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 64, 0, 0, 1, {0x01, 0, 0}, 0, 2, 224 },
920 { SUF_B, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 0, 1, {0x02, 0, 0}, 0, 2, 311 }, 907 { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x02, 0, 0}, 0, 2, 277 },
921 { SUF_W, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 0, 1, {0x03, 0, 0}, 0, 2, 150 }, 908 { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 1, {0x03, 0, 0}, 0, 2, 98 },
922 { SUF_L, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 0, 1, {0x03, 0, 0}, 0, 2, 153 }, 909 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 1, {0x03, 0, 0}, 0, 2, 101 },
923 { SUF_Q, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 64, 0, 0, 0, 1, {0x03, 0, 0}, 0, 2, 156 } 910 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 64, 0, 0, 1, {0x03, 0, 0}, 0, 2, 104 }
924 }; 911 };
925 912
926 static const x86_insn_info incdec_insn[] = { 913 static const x86_insn_info incdec_insn[] = {
927 { SUF_B, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 0, 1, {0xFE, 0, 0}, 0 , 1, 407 }, 914 { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0xFE, 0, 0}, 0, 1, 373 },
928 { SUF_W, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 391 }, 915 { SUF_W|SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 1, {0x00, 0, 0 }, 0, 1, 357 },
929 { SUF_W, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 273 }, 916 { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 1, {0xFF, 0, 0 }, 0, 1, 239 },
930 { SUF_L, NOT_64, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 0, 1, {0x00, 0 , 0}, 0, 1, 393 }, 917 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 1, {0x00 , 0, 0}, 0, 1, 359 },
931 { SUF_L, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 0, 1, {0xFF, 0 , 0}, 0, 1, 269 }, 918 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 1, {0xFF , 0, 0}, 0, 1, 235 },
932 { SUF_Q, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 0, 1, {0xFF, 0 , 0}, 0, 1, 272 } 919 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 1, {0xFF , 0, 0}, 0, 1, 238 }
933 }; 920 };
934 921
935 static const x86_insn_info f6_insn[] = { 922 static const x86_insn_info f6_insn[] = {
936 { SUF_B, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 1, 4 07 }, 923 { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 1, 373 },
937 { SUF_W, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 273 }, 924 { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 239 },
938 { SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 269 }, 925 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0 }, 0, 1, 235 },
939 { SUF_Q, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 272 } 926 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0 }, 0, 1, 238 }
940 }; 927 };
941 928
942 static const x86_insn_info div_insn[] = { 929 static const x86_insn_info div_insn[] = {
943 { SUF_B, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 1, 4 07 }, 930 { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 1, 373 },
944 { SUF_W, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 273 }, 931 { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 239 },
945 { SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 269 }, 932 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0 }, 0, 1, 235 },
946 { SUF_Q, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 272 }, 933 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0 }, 0, 1, 238 },
947 { SUF_B, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 4 43 }, 934 { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2 , 411 },
948 { SUF_W, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 445 }, 935 { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 413 },
949 { SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 447 }, 936 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0 }, 0, 2, 415 },
950 { SUF_Q, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 449 } 937 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0 }, 0, 2, 417 }
951 }; 938 };
952 939
953 static const x86_insn_info test_insn[] = { 940 static const x86_insn_info test_insn[] = {
954 { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xA8, 0, 0}, 0, 2, 458 }, 941 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA8, 0, 0}, 0, 2, 440 },
955 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 573 }, 942 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 555 } ,
956 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 57 5 }, 943 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 557 },
957 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 57 7 }, 944 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 559 },
958 { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 407 }, 945 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 373 },
959 { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 399 }, 946 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 365 },
960 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 409 }, 947 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 375 } ,
961 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 401 }, 948 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 367 } ,
962 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 41 1 }, 949 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 377 },
963 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 40 3 }, 950 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 369 },
964 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 41 3 }, 951 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 379 },
965 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 40 5 }, 952 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 371 },
966 { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x84, 0, 0}, 0, 2, 309 }, 953 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x84, 0, 0}, 0, 2, 275 },
967 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x85, 0, 0}, 0, 2, 246 }, 954 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x85, 0, 0}, 0, 2, 212 } ,
968 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x85, 0, 0}, 0, 2, 25 2 }, 955 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x85, 0, 0}, 0, 2, 218 },
969 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x85, 0, 0}, 0, 2, 25 8 }, 956 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x85, 0, 0}, 0, 2, 224 },
970 { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x84, 0, 0}, 0, 2, 311 }, 957 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x84, 0, 0}, 0, 2, 277 },
971 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x85, 0, 0}, 0, 2, 150 }, 958 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x85, 0, 0}, 0, 2, 98 },
972 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x85, 0, 0}, 0, 2, 15 3 }, 959 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x85, 0, 0}, 0, 2, 101 },
973 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x85, 0, 0}, 0, 2, 15 6 } 960 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x85, 0, 0}, 0, 2, 104 }
974 }; 961 };
975 962
976 static const x86_insn_info aadm_insn[] = { 963 static const x86_insn_info aadm_insn[] = {
977 { 0, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 0, 2, {0xD4, 0x0A, 0}, 0, 0, 0 }, 964 { SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 2, {0xD4, 0x0A, 0}, 0, 0, 0 },
978 { 0, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 0, 1, {0xD4, 0, 0}, 0, 1, 3 } 965 { SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0xD4, 0, 0}, 0, 1, 3 }
979 }; 966 };
980 967
981 static const x86_insn_info imul_insn[] = { 968 static const x86_insn_info imul_insn[] = {
982 { SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xF6, 0, 0}, 5, 1, 407 }, 969 { SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 5, 1, 373 },
983 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 273 }, 970 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 239 } ,
984 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 26 9 }, 971 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 235 },
985 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 27 2 }, 972 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 238 },
986 { SUF_W, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, 150 }, 973 { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, 98 },
987 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, 153 }, 974 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, 101 },
988 { SUF_Q, ONLY_64, CPU_386, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, 156 }, 975 { SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, 104 },
989 { SUF_W, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x6B, 0, 0}, 0, 3, 15 0 }, 976 { SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x6B, 0, 0}, 0, 3, 98 },
990 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x6B, 0, 0}, 0, 3, 15 3 }, 977 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6B, 0, 0}, 0, 3, 101 },
991 { SUF_Q, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x6B, 0, 0}, 0, 3, 156 }, 978 { SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x6B, 0, 0}, 0, 3, 104 },
992 { SUF_W, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 28 9 }, 979 { SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 255 },
993 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 29 1 }, 980 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 257 },
994 { SUF_Q, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 293 }, 981 { SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 259 },
995 { SUF_W, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, 159 }, 982 { SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, 107 },
996 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, 162 }, 983 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, 110 },
997 { SUF_Q, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, 165 }, 984 { SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, 113 },
998 { SUF_W, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 295 }, 985 { SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 261 },
999 { SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 297 }, 986 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 263 },
1000 { SUF_Q, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 299 } 987 { SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 265 }
1001 }; 988 };
1002 989
1003 static const x86_insn_info shift_insn[] = { 990 static const x86_insn_info shift_insn[] = {
1004 { SUF_B, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xD2, 0, 0}, 0, 2, 5 01 }, 991 { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xD2, 0, 0}, 0, 2, 481 },
1005 { SUF_B, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xD0, 0, 0}, 0, 2, 5 03 }, 992 { SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xD0, 0, 0}, 0, 2 , 483 },
1006 { SUF_B, 0, CPU_186, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xC0, 0, 0}, 0 , 2, 407 }, 993 { SUF_B|SUF_Z, 0, CPU_186, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xC0, 0, 0} , 0, 2, 373 },
1007 { SUF_W, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 0, 1, {0xD3, 0, 0}, 0, 2, 505 }, 994 { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xD3, 0, 0}, 0, 2, 485 },
1008 { SUF_W, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 0, 1, {0xD1, 0, 0}, 0, 2, 507 }, 995 { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xD1, 0, 0}, 0, 2, 487 },
1009 { SUF_W, 0, CPU_186, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 0, 1, {0xC1, 0, 0}, 0, 2, 273 }, 996 { SUF_W|SUF_Z, 0, CPU_186, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xC1, 0, 0 }, 0, 2, 239 },
1010 { SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 0, 1, {0xD3, 0, 0}, 0, 2, 509 }, 997 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xD3, 0, 0 }, 0, 2, 489 },
1011 { SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 0, 1, {0xD1, 0, 0}, 0, 2, 511 }, 998 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xD1, 0, 0 }, 0, 2, 491 },
1012 { SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 0, 1, {0xC1, 0, 0}, 0, 2, 275 }, 999 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xC1, 0, 0 }, 0, 2, 241 },
1013 { SUF_Q, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 0, 1, {0xD3, 0, 0}, 0, 2, 513 }, 1000 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xD3, 0, 0 }, 0, 2, 493 },
1014 { SUF_Q, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 0, 1, {0xD1, 0, 0}, 0, 2, 515 }, 1001 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xD1, 0, 0 }, 0, 2, 495 },
1015 { SUF_Q, ONLY_64, CPU_186, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 0, 1, {0xC1, 0 , 0}, 0, 2, 277 }, 1002 { SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xC1 , 0, 0}, 0, 2, 243 },
1016 { GAS_ONLY|SUF_B, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xD0, 0, 0} , 0, 1, 407 }, 1003 { GAS_ONLY|SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xD0, 0, 0}, 0, 1, 373 },
1017 { GAS_ONLY|SUF_W, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 0, 1, {0xD1, 0, 0 }, 0, 1, 273 }, 1004 { GAS_ONLY|SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xD1, 0 , 0}, 0, 1, 239 },
1018 { GAS_ONLY|SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 0, 1, {0xD1 , 0, 0}, 0, 1, 269 }, 1005 { GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0 xD1, 0, 0}, 0, 1, 235 },
1019 { GAS_ONLY|SUF_Q, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 0, 1, {0xD1 , 0, 0}, 0, 1, 272 } 1006 { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0 xD1, 0, 0}, 0, 1, 238 }
1020 }; 1007 };
1021 1008
1022 static const x86_insn_info shlrd_insn[] = { 1009 static const x86_insn_info shlrd_insn[] = {
1023 { SUF_W, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 246 }, 1010 { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00 , 0}, 0, 3, 212 },
1024 { SUF_W, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 3, 249 }, 1011 { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x0 1, 0}, 0, 3, 215 },
1025 { SUF_L, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 252 }, 1012 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x0 0, 0}, 0, 3, 218 },
1026 { SUF_L, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 3, 255 }, 1013 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x0 1, 0}, 0, 3, 221 },
1027 { SUF_Q, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 258 }, 1014 { SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0 F, 0x00, 0}, 0, 3, 224 },
1028 { SUF_Q, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 3, 261 }, 1015 { SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0 F, 0x01, 0}, 0, 3, 227 },
1029 { GAS_ONLY|SUF_W, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 0, 2, {0x0 F, 0x01, 0}, 0, 2, 246 }, 1016 { GAS_ONLY|SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, { 0x0F, 0x01, 0}, 0, 2, 212 },
1030 { GAS_ONLY|SUF_L, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0 F, 0x01, 0}, 0, 2, 252 }, 1017 { GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, { 0x0F, 0x01, 0}, 0, 2, 218 },
1031 { GAS_ONLY|SUF_Q, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 0, 2 , {0x0F, 0x01, 0}, 0, 2, 258 } 1018 { GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0 , 2, {0x0F, 0x01, 0}, 0, 2, 224 }
1032 }; 1019 };
1033 1020
1034 static const x86_insn_info call_insn[] = { 1021 static const x86_insn_info call_insn[] = {
1035 { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 612 }, 1022 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 597 },
1036 { 0, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 613 }, 1023 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, {0, 0, 0}, 0, 1, 598 },
1037 { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 614 }, 1024 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, {0, 0, 0}, 0, 1, 599 },
1038 { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 614 }, 1025 { SUF_L|SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, {0, 0, 0}, 0, 1, 599 },
1039 { 0, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0xE8, 0, 0}, 0, 1, 615 }, 1026 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xE8, 0, 0}, 0, 1, 600 },
1040 { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xE8, 0, 0}, 0, 1, 6 16 }, 1027 { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE8, 0, 0}, 0, 1, 601 },
1041 { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 1, {0xE8, 0, 0}, 0, 1, 616 } , 1028 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xE8, 0, 0}, 0, 1, 601 },
1042 { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0xE8, 0, 0}, 0, 1, 617 }, 1029 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xE8, 0, 0}, 0, 1, 602 },
1043 { 0, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 273 }, 1030 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 239 },
1044 { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 2 69 }, 1031 { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 235 },
1045 { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 272 } , 1032 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 238 },
1046 { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 611 }, 1033 { GAS_ONLY|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 60 3 },
1047 { 0, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 618 }, 1034 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 596 },
1048 { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 6 19 }, 1035 { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xFF, 0, 0}, 2, 1 , 604 },
1049 { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 620 } , 1036 { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0 , 0}, 2, 1, 605 },
1050 { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 621 }, 1037 { GAS_ILLEGAL|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xFF, 0, 0} , 2, 1, 606 },
1051 { 0, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 622 }, 1038 { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 607 },
1052 { 0, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 623 }, 1039 { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 608 },
1053 { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 624 }, 1040 { GAS_ILLEGAL|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 609 },
1054 { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 625 }, 1041 { GAS_ILLEGAL|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 610 },
1055 { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x9A, 0, 0}, 3, 1, 626 }, 1042 { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 611 },
1056 { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x9A, 0, 0}, 3, 1, 6 27 }, 1043 { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x9A, 0, 0}, 0, 1, 612 },
1057 { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x9A, 0, 0}, 3, 1, 628 }, 1044 { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x9A, 0 , 0}, 0, 1, 613 },
1058 { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x9A, 0, 0}, 3, 1, 629 }, 1045 { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x9A, 0, 0}, 0 , 1, 614 },
1059 { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x9A, 0, 0}, 3, 1, 6 30 }, 1046 { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x9A, 0, 0}, 0, 1, 615 },
1060 { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x9A, 0, 0}, 3, 1, 631 } 1047 { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x9A, 0 , 0}, 0, 1, 616 },
1048 { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x9A, 0, 0}, 0 , 1, 617 },
1049 { GAS_ONLY|GAS_NO_REV|SUF_W, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x9A, 0, 0}, 0, 2, 499 },
1050 { GAS_ONLY|GAS_NO_REV|SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x9A, 0, 0}, 0, 2, 501 },
1051 { GAS_ONLY|GAS_NO_REV|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x9A, 0, 0}, 0, 2, 503 }
1061 }; 1052 };
1062 1053
1063 static const x86_insn_info jmp_insn[] = { 1054 static const x86_insn_info jmp_insn[] = {
1064 { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 612 }, 1055 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 597 },
1065 { 0, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 613 }, 1056 { SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, {0, 0, 0}, 0, 1, 598 },
1066 { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 6 14 }, 1057 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x00, 0, 0}, 0, 1, 599 },
1067 { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 614 }, 1058 { SUF_L|SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x00, 0, 0}, 0, 1, 599 },
1068 { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0xEB, 0, 0}, 0, 1, 559 }, 1059 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xEB, 0, 0}, 0, 1, 421 },
1069 { 0, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0xE9, 0, 0}, 0, 1, 615 }, 1060 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xE9, 0, 0}, 0, 1, 600 },
1070 { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xE9, 0, 0}, 0, 1, 6 16 }, 1061 { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE9, 0, 0}, 0, 1, 601 },
1071 { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 1, {0xE9, 0, 0}, 0, 1, 616 } , 1062 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xE9, 0, 0}, 0, 1, 601 },
1072 { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0xE9, 0, 0}, 0, 1, 617 }, 1063 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xE9, 0, 0}, 0, 1, 602 },
1073 { 0, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 273 }, 1064 { SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 239 },
1074 { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 2 69 }, 1065 { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 235 },
1075 { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 272 } , 1066 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 238 },
1076 { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 611 }, 1067 { GAS_ONLY|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 60 3 },
1077 { 0, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 618 }, 1068 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 596 },
1078 { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 6 19 }, 1069 { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xFF, 0, 0}, 4, 1 , 604 },
1079 { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 620 } , 1070 { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0 , 0}, 4, 1, 605 },
1080 { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 621 }, 1071 { GAS_ILLEGAL|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xFF, 0, 0} , 4, 1, 606 },
1081 { 0, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 622 }, 1072 { GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 607 },
1082 { 0, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 623 }, 1073 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 608 },
1083 { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 624 }, 1074 { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 609 } ,
1084 { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 625 }, 1075 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 610 } ,
1085 { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xEA, 0, 0}, 3, 1, 626 }, 1076 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 611 },
1086 { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xEA, 0, 0}, 3, 1, 6 27 }, 1077 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEA, 0, 0}, 0, 1, 612 },
1087 { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xEA, 0, 0}, 3, 1, 628 }, 1078 { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEA, 0, 0}, 0, 1, 613 },
1088 { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0xEA, 0, 0}, 3, 1, 629 }, 1079 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEA, 0, 0}, 0, 1, 614 },
1089 { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xEA, 0, 0}, 3, 1, 6 30 }, 1080 { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEA, 0, 0}, 0, 1, 615 },
1090 { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xEA, 0, 0}, 3, 1, 631 } 1081 { GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEA, 0 , 0}, 0, 1, 616 },
1082 { GAS_ILLEGAL|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEA, 0, 0}, 0 , 1, 617 },
1083 { GAS_ONLY|GAS_NO_REV|SUF_W, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEA, 0, 0}, 0, 2, 499 },
1084 { GAS_ONLY|GAS_NO_REV|SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEA, 0, 0}, 0, 2, 501 },
1085 { GAS_ONLY|GAS_NO_REV|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEA, 0, 0}, 0, 2, 503 }
1086 };
1087
1088 static const x86_insn_info ljmpcall_insn[] = {
1089 { SUF_W, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 22 } ,
1090 { SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 50 },
1091 { SUF_Q, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 6 },
1092 { SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 621 },
1093 { GAS_NO_REV|SUF_W, NOT_64, 0, 0, 0, {MOD_Gap, MOD_Op0Add, 0}, 16, 0, 0, 1, {0x00, 0, 0}, 0, 2, 499 },
1094 { GAS_NO_REV|SUF_L, NOT_64, CPU_386, 0, 0, {MOD_Gap, MOD_Op0Add, 0}, 32, 0, 0, 1, {0x00, 0, 0}, 0, 2, 501 },
1095 { GAS_NO_REV|SUF_Z, NOT_64, 0, 0, 0, {MOD_Gap, MOD_Op0Add, 0}, 0, 0, 0, 1, { 0x00, 0, 0}, 0, 2, 503 }
1091 }; 1096 };
1092 1097
1093 static const x86_insn_info retnf_insn[] = { 1098 static const x86_insn_info retnf_insn[] = {
1094 { 0, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 0, 1, {0x01, 0, 0}, 0, 0, 0 }, 1099 { SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x01, 0, 0}, 0, 0, 0 },
1095 { 0, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 392 }, 1100 { SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1 , 358 },
1096 { 0, ONLY_64, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 0, 1, {0x01, 0 , 0}, 0, 0, 0 }, 1101 { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 1, {0x01, 0, 0}, 0, 0, 0 },
1097 { 0, ONLY_64, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 0, 1, {0x00, 0 , 0}, 0, 1, 392 }, 1102 { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 358 },
1098 { SUF_L|SUF_Q|SUF_W, 0, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 0, 1 , {0x01, 0, 0}, 0, 0, 0 }, 1103 { SUF_L|SUF_Q|SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0 , 1, {0x01, 0, 0}, 0, 0, 0 },
1099 { SUF_L|SUF_Q|SUF_W, 0, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 0, 1 , {0x00, 0, 0}, 0, 1, 392 } 1104 { SUF_L|SUF_Q|SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0 , 1, {0x00, 0, 0}, 0, 1, 358 }
1100 }; 1105 };
1101 1106
1102 static const x86_insn_info enter_insn[] = { 1107 static const x86_insn_info enter_insn[] = {
1103 { GAS_NO_REV|SUF_L, NOT_64, CPU_186, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xC8, 0, 0}, 0, 2, 583 }, 1108 { GAS_NO_REV|SUF_L|SUF_Z, NOT_64, CPU_186, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xC8 , 0, 0}, 0, 2, 569 },
1104 { GAS_NO_REV|SUF_Q, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 1, {0xC 8, 0, 0}, 0, 2, 583 }, 1109 { GAS_NO_REV|SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 64, 0, 1, { 0xC8, 0, 0}, 0, 2, 569 },
1105 { GAS_ONLY|GAS_NO_REV|SUF_W, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0 xC8, 0, 0}, 0, 2, 583 } 1110 { GAS_ONLY|GAS_NO_REV|SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xC8, 0, 0}, 0, 2, 569 }
1106 }; 1111 };
1107 1112
1108 static const x86_insn_info jcc_insn[] = { 1113 static const x86_insn_info jcc_insn[] = {
1109 { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 553 }, 1114 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 419 },
1110 { 0, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 635 }, 1115 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, {0, 0, 0}, 0, 1, 622 },
1111 { 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 636 }, 1116 { SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, {0, 0, 0}, 0, 1, 623 },
1112 { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 636 }, 1117 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, {0, 0, 0}, 0, 1, 623 },
1113 { 0, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 0, 1, {0x70, 0, 0}, 0, 1, 559 }, 1118 { SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0x70, 0, 0}, 0, 1, 42 1 },
1114 { 0, 0, CPU_186, 0, 0, {MOD_Op1Add, 0, 0}, 16, 64, 0, 0, 2, {0x0F, 0x80, 0}, 0, 1, 615 }, 1119 { SUF_Z, 0, CPU_186, 0, 0, {MOD_Op1Add, 0, 0}, 16, 64, 0, 2, {0x0F, 0x80, 0} , 0, 1, 600 },
1115 { 0, NOT_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x80, 0}, 0, 1, 616 }, 1120 { SUF_Z, NOT_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x80 , 0}, 0, 1, 601 },
1116 { 0, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 64, 0, 0, 2, {0x0F, 0x80, 0}, 0, 1, 616 }, 1121 { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 64, 0, 2, {0x0F, 0x80, 0} , 0, 1, 601 },
1117 { 0, 0, CPU_186, 0, 0, {MOD_Op1Add, 0, 0}, 0, 64, 0, 0, 2, {0x0F, 0x80, 0}, 0, 1, 617 } 1122 { SUF_Z, 0, CPU_186, 0, 0, {MOD_Op1Add, 0, 0}, 0, 64, 0, 2, {0x0F, 0x80, 0}, 0, 1, 602 }
1118 }; 1123 };
1119 1124
1120 static const x86_insn_info jcxz_insn[] = { 1125 static const x86_insn_info jcxz_insn[] = {
1121 { 0, 0, 0, 0, 0, {MOD_AdSizeR, 0, 0}, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 553 }, 1126 { SUF_Z, 0, 0, 0, 0, {MOD_AdSizeR, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 419 },
1122 { 0, 0, 0, 0, 0, {MOD_AdSizeR, 0, 0}, 0, 64, 0, 0, 1, {0xE3, 0, 0}, 0, 1, 55 9 } 1127 { SUF_Z, 0, 0, 0, 0, {MOD_AdSizeR, 0, 0}, 0, 64, 0, 1, {0xE3, 0, 0}, 0, 1, 4 21 }
1123 }; 1128 };
1124 1129
1125 static const x86_insn_info loop_insn[] = { 1130 static const x86_insn_info loop_insn[] = {
1126 { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 553 }, 1131 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 419 },
1127 { 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 0, {0, 0, 0}, 0, 2, 553 }, 1132 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 2, 433 },
1128 { 0, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 0, {0, 0, 0}, 0, 2, 555 }, 1133 { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 2, 419 },
1129 { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, 0, {0, 0, 0}, 0, 2, 557 }, 1134 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 2, 429 },
1130 { 0, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 0, 1, {0xE0, 0, 0}, 0, 1, 559 }, 1135 { SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0xE0, 0, 0}, 0, 1 , 421 },
1131 { 0, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 0, 1, {0xE0, 0, 0}, 0, 2, 559 }, 1136 { SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 43 5 },
1132 { 0, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 0, 1, {0xE0, 0, 0}, 0, 2, 561 }, 1137 { SUF_Z, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 421 },
1133 { 0, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 0, 1, {0xE0, 0, 0}, 0, 2, 563 } 1138 { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 431 }
1139 };
1140
1141 static const x86_insn_info loopw_insn[] = {
1142 { SUF_Z, NOT_64, 0, 0, 0, {MOD_Gap, MOD_AdSizeR, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 1, 419 },
1143 { SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, MOD_AdSizeR, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 1, 421 },
1144 { SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 2, 433 },
1145 { SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 435 }
1146 };
1147
1148 static const x86_insn_info loopl_insn[] = {
1149 { SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_AdSizeR, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 1, 419 },
1150 { SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, MOD_AdSizeR, 0}, 0, 64, 0, 1, {0xE0, 0, 0} , 0, 1, 421 },
1151 { SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 2, 419 },
1152 { SUF_Z, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 421 }
1153 };
1154
1155 static const x86_insn_info loopq_insn[] = {
1156 { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_AdSizeR, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 1, 419 },
1157 { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, MOD_AdSizeR, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 1, 421 },
1158 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 2, 429 },
1159 { SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 431 }
1134 }; 1160 };
1135 1161
1136 static const x86_insn_info setcc_insn[] = { 1162 static const x86_insn_info setcc_insn[] = {
1137 { SUF_B, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x90, 0 }, 2, 1, 309 } 1163 { SUF_B|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x90, 0}, 2, 1, 275 }
1138 }; 1164 };
1139 1165
1140 static const x86_insn_info cmpsd_insn[] = { 1166 static const x86_insn_info cmpsd_insn[] = {
1141 { GAS_ILLEGAL, NOT_AVX, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xA7, 0, 0}, 0, 0, 0 }, 1167 { GAS_ILLEGAL|SUF_Z, NOT_AVX, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA7, 0 , 0}, 0, 0, 0 },
1142 { 0, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0xC2, 0 }, 0, 3, 144 }, 1168 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0xC2, 0}, 0, 3, 92 },
1143 { 0, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0xC2, 0 }, 0, 3, 147 }, 1169 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0xC2, 0}, 0, 3, 95 },
1144 { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC3, 0, 2, {0x0F, 0xC2, 0}, 0, 4, 0 }, 1170 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC3, 2, {0x0F, 0xC2, 0}, 0, 4, 0 },
1145 { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC3, 0, 2, {0x0F, 0xC2, 0}, 0, 4, 4 } 1171 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC3, 2, {0x0F, 0xC2, 0}, 0, 4, 4 }
1146 }; 1172 };
1147 1173
1148 static const x86_insn_info movsd_insn[] = { 1174 static const x86_insn_info movsd_insn[] = {
1149 { 0, NOT_AVX, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0xA5, 0, 0}, 0, 0, 0 }, 1175 { SUF_Z, NOT_AVX, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA5, 0, 0}, 0, 0, 0 },
1150 { 0, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0x10, 0 }, 0, 2, 144 }, 1176 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x10, 0}, 0, 2, 92 },
1151 { 0, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0x10, 0 }, 0, 2, 73 }, 1177 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x10, 0}, 0, 2, 401 },
1152 { 0, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0x11, 0 }, 0, 2, 106 }, 1178 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x11, 0}, 0, 2, 39 },
1153 { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC3, 0, 2, {0x0F, 0x10, 0}, 0, 3, 0 } 1179 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC3, 2, {0x0F, 0x10, 0}, 0, 3, 0 }
1154 }; 1180 };
1155 1181
1156 static const x86_insn_info bittest_insn[] = { 1182 static const x86_insn_info bittest_insn[] = {
1157 { SUF_W, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 246 }, 1183 { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00 , 0}, 0, 2, 212 },
1158 { SUF_L, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 252 }, 1184 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x0 0, 0}, 0, 2, 218 },
1159 { SUF_Q, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 258 }, 1185 { SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0 F, 0x00, 0}, 0, 2, 224 },
1160 { SUF_W, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 0, 2, {0x0F, 0 xBA, 0}, 0, 2, 273 }, 1186 { SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 2, {0x0F , 0xBA, 0}, 0, 2, 239 },
1161 { SUF_L, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 0, 2, {0x0F, 0 xBA, 0}, 0, 2, 275 }, 1187 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 2, {0x0F , 0xBA, 0}, 0, 2, 241 },
1162 { SUF_Q, ONLY_64, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 0, 2, {0 x0F, 0xBA, 0}, 0, 2, 277 } 1188 { SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 2, {0x0F, 0xBA, 0}, 0, 2, 243 }
1163 }; 1189 };
1164 1190
1165 static const x86_insn_info bsfr_insn[] = { 1191 static const x86_insn_info bsfr_insn[] = {
1166 { SUF_W, 0, 0, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 150 }, 1192 { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 98 },
1167 { SUF_L, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 153 }, 1193 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x0 0, 0}, 0, 2, 101 },
1168 { SUF_Q, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 156 } 1194 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x0 0, 0}, 0, 2, 104 }
1169 }; 1195 };
1170 1196
1171 static const x86_insn_info int_insn[] = { 1197 static const x86_insn_info int_insn[] = {
1172 { 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xCD, 0, 0}, 0, 1, 3 } 1198 { SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xCD, 0, 0}, 0, 1, 3 }
1173 }; 1199 };
1174 1200
1175 static const x86_insn_info bound_insn[] = { 1201 static const x86_insn_info bound_insn[] = {
1176 { SUF_W, NOT_64, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 1, {0x62, 0, 0}, 0, 2, 437 }, 1202 { SUF_W|SUF_Z, NOT_64, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x62, 0, 0}, 0 , 2, 405 },
1177 { SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 1, {0x62, 0, 0}, 0, 2, 345 } 1203 { SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x62, 0, 0}, 0, 2, 311 }
1178 }; 1204 };
1179 1205
1180 static const x86_insn_info arpl_insn[] = { 1206 static const x86_insn_info arpl_insn[] = {
1181 { SUF_W, NOT_64, CPU_286, CPU_Prot, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0x63, 0, 0 }, 0, 2, 246 } 1207 { SUF_W|SUF_Z, NOT_64, CPU_286, CPU_Prot, 0, {0, 0, 0}, 0, 0, 0, 1, {0x63, 0, 0}, 0, 2, 212 }
1182 }; 1208 };
1183 1209
1184 static const x86_insn_info str_insn[] = { 1210 static const x86_insn_info str_insn[] = {
1185 { SUF_W, 0, CPU_286, CPU_Prot, 0, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x00, 0} , 1, 1, 381 }, 1211 { SUF_W|SUF_Z, 0, CPU_286, CPU_Prot, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 347 },
1186 { SUF_L, 0, CPU_386, CPU_Prot, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x00, 0} , 1, 1, 14 }, 1212 { SUF_L|SUF_Z, 0, CPU_386, CPU_Prot, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 14 },
1187 { SUF_Q, ONLY_64, CPU_286, CPU_Prot, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x 00, 0}, 1, 1, 18 }, 1213 { SUF_Q|SUF_Z, ONLY_64, CPU_286, CPU_Prot, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 18 },
1188 { SUF_L|SUF_W, 0, CPU_286, CPU_Prot, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x0 0, 0}, 1, 1, 151 } 1214 { SUF_L|SUF_W|SUF_Z, 0, CPU_286, CPU_Prot, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 99 }
1189 }; 1215 };
1190 1216
1191 static const x86_insn_info prot286_insn[] = { 1217 static const x86_insn_info prot286_insn[] = {
1192 { SUF_W, 0, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 151 } 1218 { SUF_W|SUF_Z, 0, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x0 F, 0x00, 0}, 0, 1, 99 }
1193 }; 1219 };
1194 1220
1195 static const x86_insn_info sldtmsw_insn[] = { 1221 static const x86_insn_info sldtmsw_insn[] = {
1196 { SUF_W, 0, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 22 }, 1222 { SUF_W|SUF_Z, 0, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x0 F, 0x00, 0}, 0, 1, 22 },
1197 { SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 38 }, 1223 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x 0F, 0x00, 0}, 0, 1, 50 },
1198 { SUF_Q, ONLY_64, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 6 }, 1224 { SUF_Q|SUF_Z, ONLY_64, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 6 },
1199 { SUF_W, 0, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 16, 0, 0, 0, 2, {0x0F , 0x00, 0}, 0, 1, 381 }, 1225 { SUF_W|SUF_Z, 0, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 16, 0, 0, 2, {0 x0F, 0x00, 0}, 0, 1, 347 },
1200 { SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 32, 0, 0, 0, 2, {0x0F , 0x00, 0}, 0, 1, 14 }, 1226 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 32, 0, 0, 2, {0 x0F, 0x00, 0}, 0, 1, 14 },
1201 { SUF_Q, ONLY_64, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 64, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 18 } 1227 { SUF_Q|SUF_Z, ONLY_64, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 18 }
1202 }; 1228 };
1203 1229
1204 static const x86_insn_info fld_insn[] = { 1230 static const x86_insn_info fld_insn[] = {
1205 { SUF_S, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xD9, 0, 0}, 0, 1, 593 }, 1231 { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xD9, 0, 0}, 0, 1, 5 78 },
1206 { SUF_L, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xDD, 0, 0}, 0, 1, 594 }, 1232 { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDD, 0, 0}, 0, 1, 197 },
1207 { 0, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xDB, 0, 0}, 5, 1, 591 }, 1233 { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDB, 0, 0}, 5, 1, 580 },
1208 { 0, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0xD9, 0xC0, 0}, 0, 1, 314 } 1234 { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC0, 0}, 0, 1, 280 }
1209 }; 1235 };
1210 1236
1211 static const x86_insn_info fstp_insn[] = { 1237 static const x86_insn_info fstp_insn[] = {
1212 { SUF_S, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xD9, 0, 0}, 3, 1, 593 }, 1238 { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xD9, 0, 0}, 3, 1, 5 78 },
1213 { SUF_L, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xDD, 0, 0}, 3, 1, 594 }, 1239 { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDD, 0, 0}, 3, 1, 197 },
1214 { 0, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xDB, 0, 0}, 7, 1, 591 }, 1240 { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDB, 0, 0}, 7, 1, 580 },
1215 { 0, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0xDD, 0xD8, 0}, 0, 1, 314 } 1241 { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xDD, 0xD8, 0}, 0, 1, 280 }
1216 }; 1242 };
1217 1243
1218 static const x86_insn_info fldstpt_insn[] = { 1244 static const x86_insn_info fldstpt_insn[] = {
1219 { 0, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xDB, 0, 0}, 0, 1, 591 } 1245 { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDB, 0, 0}, 0, 1, 498 }
1220 }; 1246 };
1221 1247
1222 static const x86_insn_info fildstp_insn[] = { 1248 static const x86_insn_info fildstp_insn[] = {
1223 { SUF_S, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xDF, 0, 0}, 0 , 1, 592 }, 1249 { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDF, 0, 0}, 0, 1, 577 },
1224 { SUF_L, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xDB, 0, 0}, 0 , 1, 593 }, 1250 { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDB, 0, 0} , 0, 1, 578 },
1225 { SUF_Q, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op0Add, MOD_SpAdd}, 0, 0, 0, 0, 1, {0xDD, 0, 0}, 0, 1, 594 }, 1251 { SUF_Q|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op0Add, MOD_SpAdd}, 0, 0, 0, 1, {0xDD, 0, 0}, 0, 1, 197 },
1226 { GAS_ONLY, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xDF, 0, 0} , 0, 1, 22 } 1252 { GAS_ONLY|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDF, 0, 0}, 0, 1, 22 }
1227 }; 1253 };
1228 1254
1229 static const x86_insn_info fbldstp_insn[] = { 1255 static const x86_insn_info fbldstp_insn[] = {
1230 { 0, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xDF, 0, 0}, 0, 1, 494 } 1256 { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDF, 0, 0}, 0, 1, 498 }
1231 }; 1257 };
1232 1258
1233 static const x86_insn_info fst_insn[] = { 1259 static const x86_insn_info fst_insn[] = {
1234 { SUF_S, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xD9, 0, 0}, 2, 1, 593 }, 1260 { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xD9, 0, 0}, 2, 1, 5 78 },
1235 { SUF_L, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xDD, 0, 0}, 2, 1, 594 }, 1261 { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDD, 0, 0}, 2, 1, 197 },
1236 { 0, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0xDD, 0xD0, 0}, 0, 1, 314 } 1262 { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xDD, 0xD0, 0}, 0, 1, 280 }
1237 }; 1263 };
1238 1264
1239 static const x86_insn_info fxch_insn[] = { 1265 static const x86_insn_info fxch_insn[] = {
1240 { 0, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 1, 314 }, 1266 { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 1, 280 },
1241 { 0, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 2, 313 }, 1267 { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 2, 279 },
1242 { 0, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 2, 315 }, 1268 { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 2, 281 },
1243 { 0, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0xD9, 0xC9, 0}, 0, 0, 0 } 1269 { SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC9, 0}, 0, 0, 0 }
1244 }; 1270 };
1245 1271
1246 static const x86_insn_info fcom_insn[] = { 1272 static const x86_insn_info fcom_insn[] = {
1247 { SUF_S, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 0, 1, {0xD8, 0, 0}, 0, 1, 593 }, 1273 { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0xD8, 0, 0}, 0, 1, 578 },
1248 { SUF_L, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 0, 1, {0xDC, 0, 0}, 0, 1, 594 }, 1274 { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0xDC, 0, 0}, 0, 1, 197 },
1249 { 0, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0 , 1, 314 }, 1275 { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 1, 280 },
1250 { GAS_ONLY, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 0, 1, {0xD8, 0, 0}, 0, 1, 38 }, 1276 { GAS_ONLY|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0x D8, 0, 0}, 0, 1, 50 },
1251 { GAS_ONLY, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0xD8, 0x01 , 0}, 0, 0, 0 }, 1277 { GAS_ONLY|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xD8, 0 x01, 0}, 0, 0, 0 },
1252 { GAS_ILLEGAL, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0xD8, 0 x00, 0}, 0, 2, 313 } 1278 { GAS_ILLEGAL|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xD8 , 0x00, 0}, 0, 2, 279 }
1253 }; 1279 };
1254 1280
1255 static const x86_insn_info fcom2_insn[] = { 1281 static const x86_insn_info fcom2_insn[] = {
1256 { 0, 0, CPU_286, CPU_FPU, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0x 00, 0x00, 0}, 0, 1, 314 }, 1282 { SUF_Z, 0, CPU_286, CPU_FPU, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x 00, 0x00, 0}, 0, 1, 280 },
1257 { 0, 0, CPU_286, CPU_FPU, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0x 00, 0x00, 0}, 0, 2, 313 } 1283 { SUF_Z, 0, CPU_286, CPU_FPU, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 2, {0 x00, 0x00, 0}, 0, 2, 279 }
1258 }; 1284 };
1259 1285
1260 static const x86_insn_info farith_insn[] = { 1286 static const x86_insn_info farith_insn[] = {
1261 { SUF_S, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Gap, MOD_SpAdd}, 0, 0, 0, 0, 1, {0x D8, 0, 0}, 0, 1, 593 }, 1287 { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Gap, MOD_SpAdd}, 0, 0, 0, 1, { 0xD8, 0, 0}, 0, 1, 578 },
1262 { SUF_L, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Gap, MOD_SpAdd}, 0, 0, 0, 0, 1, {0x DC, 0, 0}, 0, 1, 594 }, 1288 { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Gap, MOD_SpAdd}, 0, 0, 0, 1, {0xDC, 0, 0}, 0, 1, 197 },
1263 { 0, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 1, 314 }, 1289 { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op1Add, 0}, 0, 0, 0, 2, {0xD8, 0x00 , 0}, 0, 1, 280 },
1264 { 0, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 2, 313 }, 1290 { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op1Add, 0}, 0, 0, 0, 2, {0xD8, 0x00 , 0}, 0, 2, 279 },
1265 { 0, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0xDC, 0x00, 0}, 0 , 1, 632 }, 1291 { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDC, 0x00, 0}, 0, 1, 618 },
1266 { GAS_ILLEGAL, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0xDC, 0 x00, 0}, 0, 2, 315 }, 1292 { GAS_ILLEGAL|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDC , 0x00, 0}, 0, 2, 281 },
1267 { GAS_ONLY, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0xDC , 0x00, 0}, 0, 2, 315 } 1293 { GAS_ONLY|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op1Add, 0}, 0, 0, 0, 2, {0 xDC, 0x00, 0}, 0, 2, 281 }
1268 }; 1294 };
1269 1295
1270 static const x86_insn_info farithp_insn[] = { 1296 static const x86_insn_info farithp_insn[] = {
1271 { 0, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0xDE, 0x01, 0}, 0 , 0, 0 }, 1297 { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDE, 0x01, 0}, 0 , 0, 0 },
1272 { 0, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0xDE, 0x00, 0}, 0 , 1, 314 }, 1298 { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDE, 0x00, 0}, 0, 1, 280 },
1273 { 0, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0xDE, 0x00, 0}, 0 , 2, 315 } 1299 { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDE, 0x00, 0}, 0, 2, 281 }
1274 }; 1300 };
1275 1301
1276 static const x86_insn_info fiarith_insn[] = { 1302 static const x86_insn_info fiarith_insn[] = {
1277 { SUF_S, 0, CPU_FPU, 0, 0, {MOD_SpAdd, MOD_Op0Add, 0}, 0, 0, 0, 0, 1, {0x04, 0, 0}, 0, 1, 592 }, 1303 { SUF_S|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, MOD_Op0Add, 0}, 0, 0, 0, 1, {0x0 4, 0, 0}, 0, 1, 577 },
1278 { SUF_L, 0, CPU_FPU, 0, 0, {MOD_SpAdd, MOD_Op0Add, 0}, 0, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 593 } 1304 { SUF_L|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, MOD_Op0Add, 0}, 0, 0, 0, 1, {0x 00, 0, 0}, 0, 1, 578 }
1279 }; 1305 };
1280 1306
1281 static const x86_insn_info fldnstcw_insn[] = { 1307 static const x86_insn_info fldnstcw_insn[] = {
1282 { SUF_W, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 1, {0xD9, 0, 0}, 0 , 1, 22 } 1308 { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xD9, 0, 0}, 0, 1, 22 }
1283 }; 1309 };
1284 1310
1285 static const x86_insn_info fstcw_insn[] = { 1311 static const x86_insn_info fstcw_insn[] = {
1286 { SUF_W, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x9B, 0xD9, 0}, 7, 1, 22 } 1312 { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x9B, 0xD9, 0}, 7, 1 , 22 }
1287 }; 1313 };
1288 1314
1289 static const x86_insn_info fnstsw_insn[] = { 1315 static const x86_insn_info fnstsw_insn[] = {
1290 { SUF_W, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 1, {0xDD, 0, 0}, 7, 1, 22 }, 1316 { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDD, 0, 0}, 7, 1, 2 2 },
1291 { SUF_W, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0xDF, 0xE0, 0}, 0, 1, 329 } 1317 { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xDF, 0xE0, 0}, 0, 1, 295 }
1292 }; 1318 };
1293 1319
1294 static const x86_insn_info fstsw_insn[] = { 1320 static const x86_insn_info fstsw_insn[] = {
1295 { SUF_W, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x9B, 0xDD, 0}, 7, 1, 22 }, 1321 { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x9B, 0xDD, 0}, 7, 1 , 22 },
1296 { SUF_W, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 3, {0x9B, 0xDF, 0xE0}, 0, 1, 329 } 1322 { SUF_W|SUF_Z, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 3, {0x9B, 0xDF, 0xE0}, 0, 1, 295 }
1297 }; 1323 };
1298 1324
1299 static const x86_insn_info ffree_insn[] = { 1325 static const x86_insn_info ffree_insn[] = {
1300 { 0, 0, CPU_FPU, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 0, 2, {0x00, 0xC0, 0}, 0 , 1, 314 } 1326 { SUF_Z, 0, CPU_FPU, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 2, {0x00, 0xC0, 0}, 0 , 1, 280 }
1301 }; 1327 };
1302 1328
1303 static const x86_insn_info bswap_insn[] = { 1329 static const x86_insn_info bswap_insn[] = {
1304 { SUF_L, 0, CPU_486, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0xC8, 0}, 0, 1, 633 }, 1330 { SUF_L|SUF_Z, 0, CPU_486, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xC8, 0}, 0, 1, 619 },
1305 { SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0xC8, 0}, 0, 1, 634 } 1331 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC8, 0}, 0, 1, 620 }
1306 }; 1332 };
1307 1333
1308 static const x86_insn_info cmpxchgxadd_insn[] = { 1334 static const x86_insn_info cmpxchgxadd_insn[] = {
1309 { SUF_B, 0, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0 }, 0, 2, 309 }, 1335 { SUF_B|SUF_Z, 0, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 275 },
1310 { SUF_W, 0, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 246 }, 1336 { SUF_W|SUF_Z, 0, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x0 1, 0}, 0, 2, 212 },
1311 { SUF_L, 0, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 252 }, 1337 { SUF_L|SUF_Z, 0, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x0 1, 0}, 0, 2, 218 },
1312 { SUF_Q, ONLY_64, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 258 } 1338 { SUF_Q|SUF_Z, ONLY_64, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0 F, 0x01, 0}, 0, 2, 224 }
1313 }; 1339 };
1314 1340
1315 static const x86_insn_info cmpxchg8b_insn[] = { 1341 static const x86_insn_info cmpxchg8b_insn[] = {
1316 { SUF_Q, 0, CPU_586, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xC7, 0}, 1, 1, 6 } 1342 { SUF_Q|SUF_Z, 0, CPU_586, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xC7, 0}, 1, 1 , 6 }
1317 }; 1343 };
1318 1344
1319 static const x86_insn_info cmovcc_insn[] = { 1345 static const x86_insn_info cmovcc_insn[] = {
1320 { SUF_W, 0, CPU_686, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x40, 0}, 0, 2, 150 }, 1346 { SUF_W|SUF_Z, 0, CPU_686, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x40 , 0}, 0, 2, 98 },
1321 { SUF_L, 0, CPU_686, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x40, 0}, 0, 2, 153 }, 1347 { SUF_L|SUF_Z, 0, CPU_686, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x4 0, 0}, 0, 2, 101 },
1322 { SUF_Q, ONLY_64, CPU_686, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x40, 0}, 0, 2, 156 } 1348 { SUF_Q|SUF_Z, ONLY_64, CPU_686, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0 F, 0x40, 0}, 0, 2, 104 }
1323 }; 1349 };
1324 1350
1325 static const x86_insn_info fcmovcc_insn[] = { 1351 static const x86_insn_info fcmovcc_insn[] = {
1326 { 0, 0, CPU_686, CPU_FPU, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 0, 2, {0x 00, 0x00, 0}, 0, 2, 313 } 1352 { SUF_Z, 0, CPU_686, CPU_FPU, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x 00, 0x00, 0}, 0, 2, 279 }
1327 }; 1353 };
1328 1354
1329 static const x86_insn_info movnti_insn[] = { 1355 static const x86_insn_info movnti_insn[] = {
1330 { SUF_L, 0, CPU_P4, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xC3, 0}, 0, 2, 3 23 }, 1356 { SUF_L|SUF_Z, 0, CPU_P4, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xC3, 0}, 0, 2, 289 },
1331 { SUF_Q, ONLY_64, CPU_P4, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0xC3, 0}, 0, 2, 325 } 1357 { SUF_Q|SUF_Z, ONLY_64, CPU_P4, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC3, 0 }, 0, 2, 291 }
1332 }; 1358 };
1333 1359
1334 static const x86_insn_info clflush_insn[] = { 1360 static const x86_insn_info clflush_insn[] = {
1335 { 0, 0, CPU_P3, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xAE, 0}, 7, 1, 30 } 1361 { SUF_Z, 0, CPU_P3, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xAE, 0}, 7, 1, 42 }
1336 }; 1362 };
1337 1363
1338 static const x86_insn_info movd_insn[] = { 1364 static const x86_insn_info movd_insn[] = {
1339 { 0, 0, CPU_386, CPU_MMX, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2 , 279 }, 1365 { SUF_Z, 0, CPU_386, CPU_MMX, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2 , 245 },
1340 { 0, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 281 }, 1366 { SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 247 },
1341 { 0, 0, CPU_386, CPU_MMX, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2 , 280 }, 1367 { SUF_Z, 0, CPU_386, CPU_MMX, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 246 },
1342 { 0, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 283 }, 1368 { SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 249 },
1343 { 0, 0, CPU_386, CPU_SSE2, 0, {0, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 285 }, 1369 { SUF_Z, 0, CPU_386, CPU_SSE2, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x6E, 0}, 0, 2, 251 },
1344 { 0, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 287 }, 1370 { SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x6E, 0} , 0, 2, 253 },
1345 { 0, 0, CPU_386, CPU_SSE2, 0, {0, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 222 }, 1371 { SUF_Z, 0, CPU_386, CPU_SSE2, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x7E, 0}, 0, 2, 173 },
1346 { 0, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 219 } 1372 { SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x7E, 0} , 0, 2, 167 }
1347 }; 1373 };
1348 1374
1349 static const x86_insn_info movq_insn[] = { 1375 static const x86_insn_info movq_insn[] = {
1350 { GAS_ILLEGAL, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x6F, 0}, 0, 2, 234 }, 1376 { GAS_ILLEGAL|SUF_Z, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x6F, 0} , 0, 2, 185 },
1351 { GAS_ILLEGAL, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x6 E, 0}, 0, 2, 281 }, 1377 { GAS_ILLEGAL|SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 247 },
1352 { GAS_ILLEGAL, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x7F, 0}, 0, 2, 317 }, 1378 { GAS_ILLEGAL|SUF_Z, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x7F, 0 }, 0, 2, 283 },
1353 { GAS_ILLEGAL, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0x7 E, 0}, 0, 2, 283 }, 1379 { GAS_ILLEGAL|SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 249 },
1354 { GAS_ILLEGAL, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 64 }, 1380 { GAS_ILLEGAL|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x7 E, 0}, 0, 2, 88 },
1355 { GAS_ILLEGAL, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 319 }, 1381 { GAS_ILLEGAL|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x7 E, 0}, 0, 2, 285 },
1356 { GAS_ILLEGAL, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 287 }, 1382 { GAS_ILLEGAL|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x 0F, 0x6E, 0}, 0, 2, 253 },
1357 { GAS_ILLEGAL, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0xD6, 0}, 0, 2, 321 }, 1383 { GAS_ILLEGAL|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xD 6, 0}, 0, 2, 287 },
1358 { GAS_ILLEGAL, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 219 } 1384 { GAS_ILLEGAL|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x 0F, 0x7E, 0}, 0, 2, 167 }
1359 }; 1385 };
1360 1386
1361 static const x86_insn_info mmxsse2_insn[] = { 1387 static const x86_insn_info mmxsse2_insn[] = {
1362 { 0, 0, CPU_MMX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0 , 2, 234 }, 1388 { SUF_Z, 0, CPU_MMX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0 , 2, 185 },
1363 { 0, 0, CPU_SSE2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x00, 0 }, 0, 2, 57 } 1389 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x00, 0}, 0, 2, 170 }
1364 }; 1390 };
1365 1391
1366 static const x86_insn_info pshift_insn[] = { 1392 static const x86_insn_info pshift_insn[] = {
1367 { 0, 0, CPU_MMX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0 , 2, 234 }, 1393 { SUF_Z, 0, CPU_MMX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0 , 2, 185 },
1368 { 0, 0, CPU_MMX, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0, 0, 2, {0x0 F, 0x00, 0}, 0, 2, 199 }, 1394 { SUF_Z, 0, CPU_MMX, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0, 2, {0x 0F, 0x00, 0}, 0, 2, 147 },
1369 { 0, 0, CPU_SSE2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x00, 0 }, 0, 2, 57 }, 1395 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x00, 0}, 0, 2, 170 },
1370 { 0, 0, CPU_SSE2, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0x66, 0, 2, {0x0F, 0x00, 0}, 0, 2, 2 } 1396 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0x66, 2, {0x0F, 0x00, 0}, 0, 2, 2 }
1371 }; 1397 };
1372 1398
1373 static const x86_insn_info vpshift_insn[] = { 1399 static const x86_insn_info vpshift_insn[] = {
1374 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0xC1, 0, 2, {0x0F, 0 x00, 0}, 0, 2, 195 }, 1400 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0 x00, 0}, 0, 2, 143 },
1375 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0xC1, 0, 2, {0x0F, 0x00, 0}, 0, 2, 469 }, 1401 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0x C1, 2, {0x0F, 0x00, 0}, 0, 2, 451 },
1376 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0xC1, 0, 2, {0x0F, 0 x00, 0}, 0, 3, 40 }, 1402 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0x00, 0}, 0, 3, 52 },
1377 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0xC1, 0, 2, {0x0F, 0x00, 0}, 0, 3, 1 } 1403 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0x C1, 2, {0x0F, 0x00, 0}, 0, 3, 1 }
1378 }; 1404 };
1379 1405
1380 static const x86_insn_info xmm_xmm128_256_insn[] = { 1406 static const x86_insn_info xmm_xmm128_256_insn[] = {
1381 { 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 195 }, 1407 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 143 },
1382 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 40 }, 1408 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2 , {0x0F, 0x00, 0}, 0, 3, 52 },
1383 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 0, 2, {0x0F, 0x00, 0}, 0, 3, 8 } 1409 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2 , {0x0F, 0x00, 0}, 0, 3, 8 }
1384 }; 1410 };
1385 1411
1386 static const x86_insn_info xmm_xmm128_insn[] = { 1412 static const x86_insn_info xmm_xmm128_insn[] = {
1387 { 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 195 }, 1413 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 143 },
1388 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 40 } 1414 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2 , {0x0F, 0x00, 0}, 0, 3, 52 }
1389 }; 1415 };
1390 1416
1391 static const x86_insn_info cvt_rx_xmm32_insn[] = { 1417 static const x86_insn_info cvt_rx_xmm32_insn[] = {
1392 { SUF_L, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 201 }, 1418 { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 149 },
1393 { SUF_L, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 345 }, 1419 { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 311 },
1394 { SUF_Q, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0 , 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 207 }, 1420 { SUF_Q|SUF_Z, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 155 },
1395 { SUF_Q, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0 , 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 347 } 1421 { SUF_Q|SUF_Z, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 313 }
1396 }; 1422 };
1397 1423
1398 static const x86_insn_info cvt_mm_xmm64_insn[] = { 1424 static const x86_insn_info cvt_mm_xmm64_insn[] = {
1399 { 0, 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0 , 2, 301 }, 1425 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0 , 2, 267 },
1400 { 0, 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0 , 2, 303 } 1426 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 269 }
1401 }; 1427 };
1402 1428
1403 static const x86_insn_info cvt_xmm_mm_ps_insn[] = { 1429 static const x86_insn_info cvt_xmm_mm_ps_insn[] = {
1404 { 0, 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0 , 2, 319 } 1430 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0 , 2, 285 }
1405 }; 1431 };
1406 1432
1407 static const x86_insn_info cvt_xmm_rmx_insn[] = { 1433 static const x86_insn_info cvt_xmm_rmx_insn[] = {
1408 { SUF_L, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 587 }, 1434 { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 573 },
1409 { SUF_L, NOT_64, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 186 }, 1435 { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Set VEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 134 },
1410 { SUF_Q, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0 , 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 589 }, 1436 { SUF_Q|SUF_Z, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 575 },
1411 { SUF_L, ONLY_AVX|NOT_64, CPU_386, CPU_AVX, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 24 }, 1437 { SUF_L|SUF_Z, ONLY_AVX|NOT_64, CPU_386, CPU_AVX, 0, {MOD_PreAdd, MOD_Op1Add , 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 24 },
1412 { SUF_L, ONLY_AVX, CPU_386, CPU_AVX, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0 xC0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 267 }, 1438 { SUF_L|SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0 , 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 233 },
1413 { SUF_Q, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 64, 0 , 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 270 } 1439 { SUF_Q|SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 64, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 236 }
1414 }; 1440 };
1415 1441
1416 static const x86_insn_info xmm_xmm32_insn[] = { 1442 static const x86_insn_info xmm_xmm32_insn[] = {
1417 { 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 144 }, 1443 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 92 },
1418 { 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 192 }, 1444 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 140 },
1419 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 0 }, 1445 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2 , {0x0F, 0x00, 0}, 0, 3, 0 },
1420 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 36 } 1446 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2 , {0x0F, 0x00, 0}, 0, 3, 48 }
1421 }; 1447 };
1422 1448
1423 static const x86_insn_info ssecmp_128_insn[] = { 1449 static const x86_insn_info ssecmp_128_insn[] = {
1424 { 0, 0, CPU_SSE, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0, 0, 2, {0 x0F, 0xC2, 0}, 0, 2, 195 }, 1450 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0, 2, {0 x0F, 0xC2, 0}, 0, 2, 143 },
1425 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 0, 2, { 0x0F, 0xC2, 0}, 0, 3, 40 }, 1451 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 2, {0x0F, 0xC2, 0}, 0, 3, 52 },
1426 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC4, 0, 2, { 0x0F, 0xC2, 0}, 0, 3, 8 } 1452 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC4, 2, {0x0F, 0xC2, 0}, 0, 3, 8 }
1427 }; 1453 };
1428 1454
1429 static const x86_insn_info ssecmp_32_insn[] = { 1455 static const x86_insn_info ssecmp_32_insn[] = {
1430 { 0, 0, CPU_SSE, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0xC2, 0}, 0, 2, 144 }, 1456 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0xC2, 0}, 0, 2, 92 },
1431 { 0, 0, CPU_SSE, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0xC2, 0}, 0, 2, 192 }, 1457 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0x00, 2 , {0x0F, 0xC2, 0}, 0, 2, 140 },
1432 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 0, 2, { 0x0F, 0xC2, 0}, 0, 3, 0 }, 1458 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 2, {0x0F, 0xC2, 0}, 0, 3, 0 },
1433 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 0, 2, { 0x0F, 0xC2, 0}, 0, 3, 36 } 1459 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 2, {0x0F, 0xC2, 0}, 0, 3, 48 }
1434 }; 1460 };
1435 1461
1436 static const x86_insn_info xmm_xmm128_imm_insn[] = { 1462 static const x86_insn_info xmm_xmm128_imm_insn[] = {
1437 { 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 77 } 1463 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 170 }
1438 }; 1464 };
1439 1465
1440 static const x86_insn_info xmm_xmm128_imm_256_insn[] = { 1466 static const x86_insn_info xmm_xmm128_imm_256_insn[] = {
1441 { 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 195 }, 1467 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 143 },
1442 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 4, 40 }, 1468 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2 , {0x0F, 0x00, 0}, 0, 4, 52 },
1443 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 0, 2, {0x0F, 0x00, 0}, 0, 4, 8 } 1469 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2 , {0x0F, 0x00, 0}, 0, 4, 8 }
1444 }; 1470 };
1445 1471
1446 static const x86_insn_info xmm_xmm32_imm_insn[] = { 1472 static const x86_insn_info xmm_xmm32_imm_insn[] = {
1447 { 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 3, 144 }, 1473 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 3, 92 },
1448 { 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 3, 192 }, 1474 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 3, 140 },
1449 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 4, 0 }, 1475 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2 , {0x0F, 0x00, 0}, 0, 4, 0 },
1450 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 4, 36 } 1476 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2 , {0x0F, 0x00, 0}, 0, 4, 48 }
1451 }; 1477 };
1452 1478
1453 static const x86_insn_info ldstmxcsr_insn[] = { 1479 static const x86_insn_info ldstmxcsr_insn[] = {
1454 { 0, 0, CPU_SSE, 0, 0, {MOD_SpAdd, MOD_SetVEX, 0}, 0, 0, 0, 0, 2, {0x0F, 0xA E, 0}, 0, 1, 38 } 1480 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_SpAdd, MOD_SetVEX, 0}, 0, 0, 0, 2, {0x0F, 0xA E, 0}, 0, 1, 50 }
1455 }; 1481 };
1456 1482
1457 static const x86_insn_info maskmovq_insn[] = { 1483 static const x86_insn_info maskmovq_insn[] = {
1458 { 0, 0, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xF7, 0}, 0, 2, 581 } 1484 { SUF_Z, 0, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xF7, 0}, 0, 2, 567 }
1459 }; 1485 };
1460 1486
1461 static const x86_insn_info movau_insn[] = { 1487 static const x86_insn_info movau_insn[] = {
1462 { 0, NOT_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 57 }, 1488 { SUF_Z, NOT_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 170 },
1463 { 0, NOT_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op1Add}, 0, 0, 0x0 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 86 }, 1489 { SUF_Z, NOT_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op1Add}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 425 },
1464 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 57 }, 1490 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2 , {0x0F, 0x00, 0}, 0, 2, 170 },
1465 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op1Add}, 0, 0, 0x C0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 86 }, 1491 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op1Add}, 0, 0 , 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 425 },
1466 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 0, 2, {0x0F, 0x00, 0}, 0, 2, 225 }, 1492 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2 , {0x0F, 0x00, 0}, 0, 2, 176 },
1467 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op1Add}, 0, 0, 0x C4, 0, 2, {0x0F, 0x00, 0}, 0, 2, 453 } 1493 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op1Add}, 0, 0 , 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 427 }
1468 }; 1494 };
1469 1495
1470 static const x86_insn_info movhllhps_insn[] = { 1496 static const x86_insn_info movhllhps_insn[] = {
1471 { 0, 0, CPU_SSE, 0, 0, {MOD_Op1Add, MOD_SetVEX, 0}, 0, 0, 0, 0, 2, {0x0F, 0x 00, 0}, 0, 2, 144 }, 1497 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_Op1Add, MOD_SetVEX, 0}, 0, 0, 0, 2, {0x0F, 0x 00, 0}, 0, 2, 92 },
1472 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0 x00, 0}, 0, 3, 0 } 1498 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 0 }
1473 }; 1499 };
1474 1500
1475 static const x86_insn_info movhlp_insn[] = { 1501 static const x86_insn_info movhlp_insn[] = {
1476 { 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 147 }, 1502 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 95 },
1477 { 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x01, 0}, 0, 2, 106 }, 1503 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x01, 0}, 0, 2, 39 },
1478 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 4 } 1504 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2 , {0x0F, 0x00, 0}, 0, 3, 4 }
1479 }; 1505 };
1480 1506
1481 static const x86_insn_info movmsk_insn[] = { 1507 static const x86_insn_info movmsk_insn[] = {
1482 { SUF_L, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_SetVEX, 0}, 0, 0, 0x00, 0, 2, {0x0F, 0x50, 0}, 0, 2, 201 }, 1508 { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_SetVEX, 0}, 0, 0, 0x0 0, 2, {0x0F, 0x50, 0}, 0, 2, 149 },
1483 { SUF_Q, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_SetVEX, 0}, 64, 0, 0x00, 0 , 2, {0x0F, 0x50, 0}, 0, 2, 207 }, 1509 { SUF_Q|SUF_Z, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_SetVEX, 0}, 64, 0, 0 x00, 2, {0x0F, 0x50, 0}, 0, 2, 155 },
1484 { SUF_L, ONLY_AVX, CPU_386, CPU_AVX, 0, {MOD_PreAdd, 0, 0}, 0, 0, 0xC4, 0, 2 , {0x0F, 0x50, 0}, 0, 2, 305 }, 1510 { SUF_L|SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {MOD_PreAdd, 0, 0}, 0, 0, 0xC4 , 2, {0x0F, 0x50, 0}, 0, 2, 271 },
1485 { SUF_Q, ONLY_64|ONLY_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, 0, 0}, 64, 0, 0xC4, 0 , 2, {0x0F, 0x50, 0}, 0, 2, 307 } 1511 { SUF_Q|SUF_Z, ONLY_64|ONLY_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, 0, 0}, 64, 0, 0 xC4, 2, {0x0F, 0x50, 0}, 0, 2, 273 }
1486 }; 1512 };
1487 1513
1488 static const x86_insn_info movnt_insn[] = { 1514 static const x86_insn_info movnt_insn[] = {
1489 { 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 541 }, 1515 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 531 },
1490 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 0, 2, {0x0F, 0x00, 0}, 0, 2, 543 } 1516 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2 , {0x0F, 0x00, 0}, 0, 2, 533 }
1491 }; 1517 };
1492 1518
1493 static const x86_insn_info movntq_insn[] = { 1519 static const x86_insn_info movntq_insn[] = {
1494 { 0, 0, CPU_SSE, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xE7, 0}, 0, 2, 349 } 1520 { SUF_Z, 0, CPU_SSE, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xE7, 0}, 0, 2, 315 }
1495 }; 1521 };
1496 1522
1497 static const x86_insn_info movss_insn[] = { 1523 static const x86_insn_info movss_insn[] = {
1498 { 0, 0, CPU_SSE, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF3, 0, 2, {0x0F, 0x10, 0} , 0, 2, 144 }, 1524 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x10, 0} , 0, 2, 92 },
1499 { 0, 0, CPU_SSE, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF3, 0, 2, {0x0F, 0x10, 0} , 0, 2, 125 }, 1525 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x10, 0 }, 0, 2, 288 },
1500 { 0, 0, CPU_SSE, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF3, 0, 2, {0x0F, 0x11, 0} , 0, 2, 134 }, 1526 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x11, 0 }, 0, 2, 529 },
1501 { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC2, 0, 2, {0x0F, 0x10, 0}, 0, 3, 0 } 1527 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC2, 2, {0x0F, 0x10, 0}, 0, 3, 0 }
1502 }; 1528 };
1503 1529
1504 static const x86_insn_info pextrw_insn[] = { 1530 static const x86_insn_info pextrw_insn[] = {
1505 { SUF_L, NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xC5, 0}, 0, 3, 198 }, 1531 { SUF_L|SUF_Z, NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xC 5, 0}, 0, 3, 146 },
1506 { SUF_L, 0, CPU_386, CPU_SSE2, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 0, 2, {0x0 F, 0xC5, 0}, 0, 3, 201 }, 1532 { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE2, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 2, { 0x0F, 0xC5, 0}, 0, 3, 149 },
1507 { SUF_Q, ONLY_64|NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x 0F, 0xC5, 0}, 0, 3, 204 }, 1533 { SUF_Q|SUF_Z, ONLY_64|NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC5, 0}, 0, 3, 152 },
1508 { SUF_Q, ONLY_64, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 0, 2, {0x 0F, 0xC5, 0}, 0, 3, 207 }, 1534 { SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0xC5, 0}, 0, 3, 155 },
1509 { 0, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x15}, 0, 3, 210 }, 1535 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x15}, 0, 3, 158 },
1510 { 0, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 32, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x15}, 0, 3, 213 }, 1536 { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 32, 0, 0x66, 3, {0x0F , 0x3A, 0x15}, 0, 3, 161 },
1511 { 0, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x15}, 0, 3, 216 } 1537 { SUF_Z, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F , 0x3A, 0x15}, 0, 3, 164 }
1512 }; 1538 };
1513 1539
1514 static const x86_insn_info pinsrw_insn[] = { 1540 static const x86_insn_info pinsrw_insn[] = {
1515 { SUF_L, NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xC4, 0}, 0, 3, 168 }, 1541 { SUF_L|SUF_Z, NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xC 4, 0}, 0, 3, 116 },
1516 { SUF_Q, ONLY_64|NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x 0F, 0xC4, 0}, 0, 3, 171 }, 1542 { SUF_Q|SUF_Z, ONLY_64|NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 64, 64, 0, 2, {0x0F, 0xC4, 0}, 0, 3, 119 },
1517 { SUF_L, NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xC4, 0}, 0, 3, 174 }, 1543 { SUF_L|SUF_Z, NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x C4, 0}, 0, 3, 122 },
1518 { SUF_L, 0, CPU_386, CPU_SSE2, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 0, 2, {0x0 F, 0xC4, 0}, 0, 3, 177 }, 1544 { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE2, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 2, { 0x0F, 0xC4, 0}, 0, 3, 125 },
1519 { SUF_Q, ONLY_64, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 0, 2, {0x 0F, 0xC4, 0}, 0, 3, 180 }, 1545 { SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 64, 64, 0x66, 2, {0x0F, 0xC4, 0}, 0, 3, 128 },
1520 { SUF_L, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0xC 4, 0}, 0, 3, 183 }, 1546 { SUF_L|SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xC4, 0}, 0, 3, 131 },
1521 { SUF_L, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 0, 2, {0x0F, 0xC4, 0}, 0, 4, 12 }, 1547 { SUF_L|SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0 F, 0xC4, 0}, 0, 4, 12 },
1522 { SUF_Q, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 0, 0xC1, 0, 2, {0x0 F, 0xC4, 0}, 0, 4, 16 }, 1548 { SUF_Q|SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 64, 0xC1, 2, {0x0F, 0xC4, 0}, 0, 4, 16 },
1523 { SUF_L, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 0, 2, {0x0F, 0xC4, 0}, 0, 4, 20 } 1549 { SUF_L|SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0xC 4, 0}, 0, 4, 20 }
1524 }; 1550 };
1525 1551
1526 static const x86_insn_info pmovmskb_insn[] = { 1552 static const x86_insn_info pmovmskb_insn[] = {
1527 { SUF_L, NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xD7, 0}, 0, 2, 198 }, 1553 { SUF_L|SUF_Z, NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xD 7, 0}, 0, 2, 146 },
1528 { SUF_L, 0, CPU_386, CPU_SSE2, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 0, 2, {0x0 F, 0xD7, 0}, 0, 2, 201 }, 1554 { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE2, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 2, { 0x0F, 0xD7, 0}, 0, 2, 149 },
1529 { SUF_Q, ONLY_64|NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x 0F, 0xD7, 0}, 0, 2, 204 }, 1555 { SUF_Q|SUF_Z, ONLY_64|NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xD7, 0}, 0, 2, 152 },
1530 { SUF_Q, ONLY_64, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 0, 2, {0x 0F, 0xD7, 0}, 0, 2, 207 } 1556 { SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0xD7, 0}, 0, 2, 155 }
1531 }; 1557 };
1532 1558
1533 static const x86_insn_info pshufw_insn[] = { 1559 static const x86_insn_info pshufw_insn[] = {
1534 { 0, 0, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x70, 0}, 0, 3, 234 } 1560 { SUF_Z, 0, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x70, 0}, 0, 3, 185 }
1535 }; 1561 };
1536 1562
1537 static const x86_insn_info xmm_xmm64_insn[] = { 1563 static const x86_insn_info xmm_xmm64_insn[] = {
1538 { 0, 0, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 144 }, 1564 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 92 },
1539 { 0, 0, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 147 }, 1565 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00 , 2, {0x0F, 0x00, 0}, 0, 2, 95 },
1540 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 0 }, 1566 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2 , {0x0F, 0x00, 0}, 0, 3, 0 },
1541 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 4 } 1567 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2 , {0x0F, 0x00, 0}, 0, 3, 4 }
1542 }; 1568 };
1543 1569
1544 static const x86_insn_info ssecmp_64_insn[] = { 1570 static const x86_insn_info ssecmp_64_insn[] = {
1545 { 0, 0, CPU_SSE2, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0x00, 0, 2 , {0x0F, 0xC2, 0}, 0, 2, 144 }, 1571 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0x00, 2 , {0x0F, 0xC2, 0}, 0, 2, 92 },
1546 { 0, 0, CPU_SSE2, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0x00, 0, 2 , {0x0F, 0xC2, 0}, 0, 2, 147 }, 1572 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0xC2, 0}, 0, 2, 95 },
1547 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 0, 2, { 0x0F, 0xC2, 0}, 0, 3, 0 }, 1573 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 2, {0x0F, 0xC2, 0}, 0, 3, 0 },
1548 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 0, 2, { 0x0F, 0xC2, 0}, 0, 3, 4 } 1574 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 2, {0x0F, 0xC2, 0}, 0, 3, 4 }
1549 }; 1575 };
1550 1576
1551 static const x86_insn_info cvt_rx_xmm64_insn[] = { 1577 static const x86_insn_info cvt_rx_xmm64_insn[] = {
1552 { SUF_L, 0, CPU_386, CPU_SSE2, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0 , 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 201 }, 1578 { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE2, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 149 },
1553 { SUF_L, 0, CPU_386, CPU_SSE2, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0 , 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 324 }, 1579 { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE2, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX} , 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 290 },
1554 { SUF_Q, ONLY_64, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 207 }, 1580 { SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX} , 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 155 },
1555 { SUF_Q, ONLY_64, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 441 } 1581 { SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX} , 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 409 }
1556 }; 1582 };
1557 1583
1558 static const x86_insn_info cvt_mm_xmm_insn[] = { 1584 static const x86_insn_info cvt_mm_xmm_insn[] = {
1559 { 0, 0, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 0, 2, {0x0F , 0x00, 0}, 0, 2, 565 } 1585 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 2, {0x0F , 0x00, 0}, 0, 2, 543 }
1560 }; 1586 };
1561 1587
1562 static const x86_insn_info cvt_xmm_mm_ss_insn[] = { 1588 static const x86_insn_info cvt_xmm_mm_ss_insn[] = {
1563 { 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 0, 2, {0x0F, 0x00, 0}, 0, 2, 319 } 1589 { SUF_Z, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 285 }
1590 };
1591
1592 static const x86_insn_info eptvpid_insn[] = {
1593 { SUF_L|SUF_Z, NOT_64, CPU_386, CPU_EPTVPID, 0, {MOD_Op2Add, 0, 0}, 32, 0, 0x 66, 3, {0x0F, 0x38, 0x80}, 0, 2, 551 },
1594 { SUF_Q|SUF_Z, ONLY_64, CPU_EPTVPID, 0, 0, {MOD_Op2Add, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x38, 0x80}, 0, 2, 553 }
1564 }; 1595 };
1565 1596
1566 static const x86_insn_info vmxmemrd_insn[] = { 1597 static const x86_insn_info vmxmemrd_insn[] = {
1567 { SUF_L, NOT_64, CPU_P4, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x78, 0}, 0 , 2, 252 }, 1598 { SUF_L|SUF_Z, NOT_64, CPU_P4, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0x78, 0}, 0, 2, 218 },
1568 { SUF_Q, ONLY_64, CPU_P4, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 2, {0x0F, 0x78, 0}, 0, 2, 258 } 1599 { SUF_Q|SUF_Z, ONLY_64, CPU_P4, 0, 0, {0, 0, 0}, 64, 64, 0, 2, {0x0F, 0x78, 0}, 0, 2, 224 }
1569 }; 1600 };
1570 1601
1571 static const x86_insn_info vmxmemwr_insn[] = { 1602 static const x86_insn_info vmxmemwr_insn[] = {
1572 { SUF_L, NOT_64, CPU_P4, 0, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x79, 0}, 0 , 2, 153 }, 1603 { SUF_L|SUF_Z, NOT_64, CPU_P4, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0x79, 0}, 0, 2, 101 },
1573 { SUF_Q, ONLY_64, CPU_P4, 0, 0, {0, 0, 0}, 64, 64, 0, 0, 2, {0x0F, 0x79, 0}, 0, 2, 156 } 1604 { SUF_Q|SUF_Z, ONLY_64, CPU_P4, 0, 0, {0, 0, 0}, 64, 64, 0, 2, {0x0F, 0x79, 0}, 0, 2, 104 }
1574 }; 1605 };
1575 1606
1576 static const x86_insn_info vmxtwobytemem_insn[] = { 1607 static const x86_insn_info vmxtwobytemem_insn[] = {
1577 { 0, 0, CPU_P4, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0xC7, 0}, 0, 1, 6 } 1608 { SUF_Z, 0, CPU_P4, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 2, {0x0F, 0xC7, 0}, 0, 1, 6 }
1578 }; 1609 };
1579 1610
1580 static const x86_insn_info vmxthreebytemem_insn[] = { 1611 static const x86_insn_info vmxthreebytemem_insn[] = {
1581 { 0, 0, CPU_P4, 0, 0, {MOD_PreAdd, 0, 0}, 0, 0, 0x00, 0, 2, {0x0F, 0xC7, 0}, 6, 1, 6 } 1612 { SUF_Z, 0, CPU_P4, 0, 0, {MOD_PreAdd, 0, 0}, 0, 0, 0x00, 2, {0x0F, 0xC7, 0}, 6, 1, 6 }
1582 }; 1613 };
1583 1614
1584 static const x86_insn_info maskmovdqu_insn[] = { 1615 static const x86_insn_info maskmovdqu_insn[] = {
1585 { 0, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0xF7, 0 }, 0, 2, 64 } 1616 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xF7, 0 }, 0, 2, 88 }
1586 }; 1617 };
1587 1618
1588 static const x86_insn_info movdq2q_insn[] = { 1619 static const x86_insn_info movdq2q_insn[] = {
1589 { 0, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0xD6, 0}, 0, 2, 301 } 1620 { SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0xD6, 0}, 0, 2, 267 }
1590 }; 1621 };
1591 1622
1592 static const x86_insn_info movq2dq_insn[] = { 1623 static const x86_insn_info movq2dq_insn[] = {
1593 { 0, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 0, 2, {0x0F, 0xD6, 0}, 0, 2, 431 } 1624 { SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0xD6, 0}, 0, 2, 397 }
1594 }; 1625 };
1595 1626
1596 static const x86_insn_info pslrldq_insn[] = { 1627 static const x86_insn_info pslrldq_insn[] = {
1597 { 0, 0, CPU_SSE2, 0, 0, {MOD_SpAdd, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x73, 0}, 0, 2, 469 }, 1628 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SpAdd, MOD_SetVEX, 0}, 0, 0, 0x66, 2, {0x0F, 0x73, 0}, 0, 2, 451 },
1598 { 0, 0, CPU_SSE2, 0, 0, {MOD_SpAdd, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x73, 0}, 0, 3, 1 } 1629 { SUF_Z, 0, CPU_SSE2, 0, 0, {MOD_SpAdd, MOD_SetVEX, 0}, 0, 0, 0x66, 2, {0x0F , 0x73, 0}, 0, 3, 1 }
1599 }; 1630 };
1600 1631
1601 static const x86_insn_info lddqu_insn[] = { 1632 static const x86_insn_info lddqu_insn[] = {
1602 { 0, 0, CPU_SSE3, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0xF0, 0 }, 0, 2, 539 }, 1633 { SUF_Z, 0, CPU_SSE3, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0xF0, 0 }, 0, 2, 527 },
1603 { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC7, 0, 2, {0x0F, 0xF0, 0}, 0, 2, 579 } 1634 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC7, 2, {0x0F, 0xF0, 0}, 0, 2, 565 }
1604 }; 1635 };
1605 1636
1606 static const x86_insn_info ssse3_insn[] = { 1637 static const x86_insn_info ssse3_insn[] = {
1607 { 0, NOT_AVX, CPU_SSSE3, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x3 8, 0x00}, 0, 2, 234 }, 1638 { SUF_Z, NOT_AVX, CPU_SSSE3, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 3, {0x0F, 0x3 8, 0x00}, 0, 2, 185 },
1608 { 0, 0, CPU_SSSE3, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0 F, 0x38, 0x00}, 0, 2, 195 }, 1639 { SUF_Z, 0, CPU_SSSE3, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x 0F, 0x38, 0x00}, 0, 2, 143 },
1609 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0 x38, 0x00}, 0, 3, 40 } 1640 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 52 }
1610 }; 1641 };
1611 1642
1612 static const x86_insn_info ssse3imm_insn[] = { 1643 static const x86_insn_info ssse3imm_insn[] = {
1613 { 0, 0, CPU_SSSE3, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x3A, 0x0 0}, 0, 3, 234 }, 1644 { SUF_Z, 0, CPU_SSSE3, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 3, {0x0F, 0x3A, 0x0 0}, 0, 3, 185 },
1614 { 0, 0, CPU_SSSE3, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 77 } 1645 { SUF_Z, 0, CPU_SSSE3, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 170 }
1615 }; 1646 };
1616 1647
1617 static const x86_insn_info sse4_insn[] = { 1648 static const x86_insn_info sse4_insn[] = {
1618 { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0 F, 0x38, 0x00}, 0, 2, 57 }, 1649 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0 F, 0x38, 0x00}, 0, 2, 170 },
1619 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0 x38, 0x00}, 0, 2, 225 } 1650 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 2, 176 }
1620 }; 1651 };
1621 1652
1622 static const x86_insn_info sse4imm_256_insn[] = { 1653 static const x86_insn_info sse4imm_256_insn[] = {
1623 { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0 F, 0x3A, 0x00}, 0, 3, 195 }, 1654 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0 F, 0x3A, 0x00}, 0, 3, 143 },
1624 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0 x3A, 0x00}, 0, 4, 40 }, 1655 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 52 },
1625 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0 x3A, 0x00}, 0, 4, 8 } 1656 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 4, 8 }
1626 }; 1657 };
1627 1658
1628 static const x86_insn_info sse4imm_insn[] = { 1659 static const x86_insn_info sse4imm_insn[] = {
1629 { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0 F, 0x3A, 0x00}, 0, 3, 195 }, 1660 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0 F, 0x3A, 0x00}, 0, 3, 143 },
1630 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0 x3A, 0x00}, 0, 4, 40 } 1661 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 52 }
1631 }; 1662 };
1632 1663
1633 static const x86_insn_info sse4m32imm_insn[] = { 1664 static const x86_insn_info sse4m32imm_insn[] = {
1634 { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0 F, 0x3A, 0x00}, 0, 3, 144 }, 1665 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0 F, 0x3A, 0x00}, 0, 3, 92 },
1635 { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0 F, 0x3A, 0x00}, 0, 3, 192 }, 1666 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x 0F, 0x3A, 0x00}, 0, 3, 140 },
1636 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0 x3A, 0x00}, 0, 4, 0 }, 1667 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 0 },
1637 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0 x3A, 0x00}, 0, 4, 36 } 1668 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 48 }
1638 }; 1669 };
1639 1670
1640 static const x86_insn_info sse4m64imm_insn[] = { 1671 static const x86_insn_info sse4m64imm_insn[] = {
1641 { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0 F, 0x3A, 0x00}, 0, 3, 144 }, 1672 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0 F, 0x3A, 0x00}, 0, 3, 92 },
1642 { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0 F, 0x3A, 0x00}, 0, 3, 147 }, 1673 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x 0F, 0x3A, 0x00}, 0, 3, 95 },
1643 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0 x3A, 0x00}, 0, 4, 0 }, 1674 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 0 },
1644 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0 x3A, 0x00}, 0, 4, 4 } 1675 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 4 }
1645 }; 1676 };
1646 1677
1647 static const x86_insn_info sse4xmm0_insn[] = { 1678 static const x86_insn_info sse4xmm0_insn[] = {
1648 { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, 57 }, 1679 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 170 },
1649 { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x38, 0x00}, 0, 3, 231 } 1680 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 3, 209 }
1650 }; 1681 };
1651 1682
1652 static const x86_insn_info avx_sse4xmm0_insn[] = { 1683 static const x86_insn_info avx_sse4xmm0_insn[] = {
1653 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0 x3A, 0x00}, 0, 4, 48 }, 1684 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0 x3A, 0x00}, 0, 4, 60 },
1654 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0 x3A, 0x00}, 0, 4, 52 } 1685 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 4, 64 }
1655 }; 1686 };
1656 1687
1657 static const x86_insn_info avx_sse4xmm0_128_insn[] = { 1688 static const x86_insn_info avx_sse4xmm0_128_insn[] = {
1658 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0 x3A, 0x00}, 0, 4, 48 } 1689 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0 x3A, 0x00}, 0, 4, 60 }
1659 }; 1690 };
1660 1691
1661 static const x86_insn_info crc32_insn[] = { 1692 static const x86_insn_info crc32_insn[] = {
1662 { SUF_B, 0, CPU_386, CPU_SSE42, 0, {0, 0, 0}, 0, 0, 0xF2, 0, 3, {0x0F, 0x38, 0xF0}, 0, 2, 495 }, 1693 { SUF_B|SUF_Z, 0, CPU_386, CPU_SSE42, 0, {0, 0, 0}, 0, 0, 0xF2, 3, {0x0F, 0x3 8, 0xF0}, 0, 2, 475 },
1663 { SUF_W, 0, CPU_386, CPU_SSE42, 0, {0, 0, 0}, 16, 0, 0xF2, 0, 3, {0x0F, 0x38 , 0xF1}, 0, 2, 497 }, 1694 { SUF_W|SUF_Z, 0, CPU_386, CPU_SSE42, 0, {0, 0, 0}, 16, 0, 0xF2, 3, {0x0F, 0 x38, 0xF1}, 0, 2, 477 },
1664 { SUF_L, 0, CPU_386, CPU_SSE42, 0, {0, 0, 0}, 32, 0, 0xF2, 0, 3, {0x0F, 0x38 , 0xF1}, 0, 2, 153 }, 1695 { SUF_L|SUF_Z, 0, CPU_386, CPU_SSE42, 0, {0, 0, 0}, 32, 0, 0xF2, 3, {0x0F, 0 x38, 0xF1}, 0, 2, 101 },
1665 { SUF_B, ONLY_64, CPU_SSE42, 0, 0, {0, 0, 0}, 64, 0, 0xF2, 0, 3, {0x0F, 0x38 , 0xF0}, 0, 2, 499 }, 1696 { SUF_B|SUF_Z, ONLY_64, CPU_SSE42, 0, 0, {0, 0, 0}, 64, 0, 0xF2, 3, {0x0F, 0 x38, 0xF0}, 0, 2, 479 },
1666 { SUF_Q, ONLY_64, CPU_SSE42, 0, 0, {0, 0, 0}, 64, 0, 0xF2, 0, 3, {0x0F, 0x38 , 0xF1}, 0, 2, 156 } 1697 { SUF_Q|SUF_Z, ONLY_64, CPU_SSE42, 0, 0, {0, 0, 0}, 64, 0, 0xF2, 3, {0x0F, 0 x38, 0xF1}, 0, 2, 104 }
1667 }; 1698 };
1668 1699
1669 static const x86_insn_info extractps_insn[] = { 1700 static const x86_insn_info extractps_insn[] = {
1670 { 0, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 32, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x17}, 0, 3, 222 }, 1701 { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x17}, 0, 3, 173 },
1671 { 0, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x17}, 0, 3, 216 } 1702 { SUF_Z, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F , 0x3A, 0x17}, 0, 3, 164 }
1672 }; 1703 };
1673 1704
1674 static const x86_insn_info insertps_insn[] = { 1705 static const x86_insn_info insertps_insn[] = {
1675 { 0, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x21}, 0, 3, 192 }, 1706 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x21}, 0, 3, 140 },
1676 { 0, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x21}, 0, 3, 144 }, 1707 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x21}, 0, 3, 92 },
1677 { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x3A, 0x21 }, 0, 4, 36 }, 1708 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x2 1}, 0, 4, 48 },
1678 { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x3A, 0x21 }, 0, 4, 0 } 1709 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x2 1}, 0, 4, 0 }
1679 }; 1710 };
1680 1711
1681 static const x86_insn_info movntdqa_insn[] = { 1712 static const x86_insn_info movntdqa_insn[] = {
1682 { 0, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x38, 0x2A}, 0, 2, 539 } 1713 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x2A}, 0, 2, 527 }
1683 }; 1714 };
1684 1715
1685 static const x86_insn_info sse4pcmpstr_insn[] = { 1716 static const x86_insn_info sse4pcmpstr_insn[] = {
1686 { 0, 0, CPU_SSE42, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0 F, 0x3A, 0x00}, 0, 3, 77 } 1717 { SUF_Z, 0, CPU_SSE42, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0 F, 0x3A, 0x00}, 0, 3, 170 }
1687 }; 1718 };
1688 1719
1689 static const x86_insn_info pextrb_insn[] = { 1720 static const x86_insn_info pextrb_insn[] = {
1690 { 0, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x14}, 0, 3, 228 }, 1721 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x14}, 0, 3, 179 },
1691 { 0, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 32, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x14}, 0, 3, 213 }, 1722 { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x14}, 0, 3, 161 },
1692 { 0, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x14}, 0, 3, 216 } 1723 { SUF_Z, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F , 0x3A, 0x14}, 0, 3, 164 }
1693 }; 1724 };
1694 1725
1695 static const x86_insn_info pextrd_insn[] = { 1726 static const x86_insn_info pextrd_insn[] = {
1696 { 0, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 32, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x16}, 0, 3, 222 } 1727 { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x16}, 0, 3, 173 }
1697 }; 1728 };
1698 1729
1699 static const x86_insn_info pextrq_insn[] = { 1730 static const x86_insn_info pextrq_insn[] = {
1700 { 0, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x16}, 0, 3, 219 } 1731 { SUF_Z, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x16}, 0, 3, 167 }
1701 }; 1732 };
1702 1733
1703 static const x86_insn_info pinsrb_insn[] = { 1734 static const x86_insn_info pinsrb_insn[] = {
1704 { 0, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x20}, 0, 3, 189 }, 1735 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x20}, 0, 3, 137 },
1705 { 0, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 32, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x20}, 0, 3, 177 }, 1736 { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x20}, 0, 3, 125 },
1706 { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x3A, 0x20 }, 0, 4, 28 }, 1737 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x2 0}, 0, 4, 40 },
1707 { 0, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 32, 0, 0xC1, 0, 3, {0x0F, 0x3 A, 0x20}, 0, 4, 32 } 1738 { SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3 A, 0x20}, 0, 4, 44 }
1708 }; 1739 };
1709 1740
1710 static const x86_insn_info pinsrd_insn[] = { 1741 static const x86_insn_info pinsrd_insn[] = {
1711 { 0, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 32, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x22}, 0, 3, 186 }, 1742 { SUF_Z, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x22}, 0, 3, 134 },
1712 { 0, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 32, 0, 0xC1, 0, 3, {0x0F, 0x3 A, 0x22}, 0, 4, 24 } 1743 { SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3 A, 0x22}, 0, 4, 24 }
1713 }; 1744 };
1714 1745
1715 static const x86_insn_info pinsrq_insn[] = { 1746 static const x86_insn_info pinsrq_insn[] = {
1716 { 0, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x22}, 0, 3, 243 }, 1747 { SUF_Z, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x22}, 0, 3, 206 },
1717 { 0, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 0, 0xC1, 0, 3, {0x0F, 0 x3A, 0x22}, 0, 4, 60 } 1748 { SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 0, 0xC1, 3, {0x0F, 0x3A, 0x22}, 0, 4, 76 }
1718 }; 1749 };
1719 1750
1720 static const x86_insn_info sse4m16_insn[] = { 1751 static const x86_insn_info sse4m16_insn[] = {
1721 { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0 F, 0x38, 0x00}, 0, 2, 433 }, 1752 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0 F, 0x38, 0x00}, 0, 2, 399 },
1722 { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0 F, 0x38, 0x00}, 0, 2, 64 } 1753 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x 0F, 0x38, 0x00}, 0, 2, 88 }
1723 }; 1754 };
1724 1755
1725 static const x86_insn_info sse4m32_insn[] = { 1756 static const x86_insn_info sse4m32_insn[] = {
1726 { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0 F, 0x38, 0x00}, 0, 2, 125 }, 1757 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0 F, 0x38, 0x00}, 0, 2, 288 },
1727 { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0 F, 0x38, 0x00}, 0, 2, 64 } 1758 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x 0F, 0x38, 0x00}, 0, 2, 88 }
1728 }; 1759 };
1729 1760
1730 static const x86_insn_info sse4m64_insn[] = { 1761 static const x86_insn_info sse4m64_insn[] = {
1731 { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0 F, 0x38, 0x00}, 0, 2, 73 }, 1762 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0 F, 0x38, 0x00}, 0, 2, 401 },
1732 { 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0 F, 0x38, 0x00}, 0, 2, 64 } 1763 { SUF_Z, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x 0F, 0x38, 0x00}, 0, 2, 88 }
1733 }; 1764 };
1734 1765
1735 static const x86_insn_info cnt_insn[] = { 1766 static const x86_insn_info cnt_insn[] = {
1736 { SUF_W, 0, 0, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0xF3, 0, 2, {0x0F, 0x00, 0}, 0, 2, 150 }, 1767 { SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0xF3, 2, {0x0F, 0x00, 0 }, 0, 2, 98 },
1737 { SUF_L, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0xF3, 0, 2, {0x0F, 0x0 0, 0}, 0, 2, 153 }, 1768 { SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0xF3, 2, {0x0F, 0x00, 0}, 0, 2, 101 },
1738 { SUF_Q, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0xF3, 0, 2, {0x0F, 0x0 0, 0}, 0, 2, 156 } 1769 { SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0xF3, 2, {0x0F, 0x00, 0}, 0, 2, 104 }
1739 }; 1770 };
1740 1771
1741 static const x86_insn_info vmovd_insn[] = { 1772 static const x86_insn_info vmovd_insn[] = {
1742 { 0, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 0, 2, {0x0F, 0x6E , 0}, 0, 2, 285 }, 1773 { SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0x6E , 0}, 0, 2, 251 },
1743 { 0, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 0, 2, {0x0F, 0x7E , 0}, 0, 2, 222 } 1774 { SUF_Z, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0x7 E, 0}, 0, 2, 173 }
1744 }; 1775 };
1745 1776
1746 static const x86_insn_info vmovq_insn[] = { 1777 static const x86_insn_info vmovq_insn[] = {
1747 { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC2, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 64 }, 1778 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC2, 2, {0x0F, 0x7E, 0}, 0, 2, 88 },
1748 { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC2, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 73 }, 1779 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC2, 2, {0x0F, 0x7E, 0}, 0, 2, 401 },
1749 { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 0, 2, {0x0F, 0xD6, 0}, 0, 2, 106 }, 1780 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0xD6, 0}, 0, 2, 39 },
1750 { 0, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 0, 0xC1, 0, 2, {0x0F, 0 x6E, 0}, 0, 2, 287 }, 1781 { SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 0, 0xC1, 2, {0x0F, 0x6E, 0}, 0, 2, 253 },
1751 { 0, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 0, 0xC1, 0, 2, {0x0F, 0 x7E, 0}, 0, 2, 219 } 1782 { SUF_Z, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 0, 0xC1, 2, {0x0F, 0x7E, 0}, 0, 2, 167 }
1752 }; 1783 };
1753 1784
1754 static const x86_insn_info avx_xmm_xmm128_insn[] = { 1785 static const x86_insn_info avx_xmm_xmm128_insn[] = {
1755 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 57 }, 1786 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 170 },
1756 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 0, 2, {0x0F, 0x00, 0}, 0, 2, 225 } 1787 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2 , {0x0F, 0x00, 0}, 0, 2, 176 }
1757 }; 1788 };
1758 1789
1759 static const x86_insn_info avx_sse4imm_insn[] = { 1790 static const x86_insn_info avx_sse4imm_insn[] = {
1760 { 0, ONLY_AVX, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 77 }, 1791 { SUF_Z, ONLY_AVX, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 3, 170 },
1761 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0 x3A, 0x00}, 0, 3, 77 }, 1792 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 3, 170 },
1762 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0 x3A, 0x00}, 0, 3, 225 } 1793 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 3, 176 }
1763 }; 1794 };
1764 1795
1765 static const x86_insn_info vmovddup_insn[] = { 1796 static const x86_insn_info vmovddup_insn[] = {
1766 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 64 }, 1797 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 88 },
1767 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 73 }, 1798 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2 , {0x0F, 0x00, 0}, 0, 2, 401 },
1768 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 0, 2, {0x0F, 0x00, 0}, 0, 2, 225 } 1799 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2 , {0x0F, 0x00, 0}, 0, 2, 176 }
1769 }; 1800 };
1770 1801
1771 static const x86_insn_info avx_xmm_xmm64_insn[] = { 1802 static const x86_insn_info avx_xmm_xmm64_insn[] = {
1772 { 0, ONLY_AVX, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2 , {0x0F, 0x00, 0}, 0, 2, 64 }, 1803 { SUF_Z, ONLY_AVX, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2 , {0x0F, 0x00, 0}, 0, 2, 88 },
1773 { 0, ONLY_AVX, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2 , {0x0F, 0x00, 0}, 0, 2, 73 } 1804 { SUF_Z, ONLY_AVX, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 401 }
1774 }; 1805 };
1775 1806
1776 static const x86_insn_info avx_xmm_xmm32_insn[] = { 1807 static const x86_insn_info avx_xmm_xmm32_insn[] = {
1777 { 0, ONLY_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 64 }, 1808 { SUF_Z, ONLY_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 88 },
1778 { 0, ONLY_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 125 } 1809 { SUF_Z, ONLY_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2 , {0x0F, 0x00, 0}, 0, 2, 288 }
1779 }; 1810 };
1780 1811
1781 static const x86_insn_info avx_cvt_xmm64_insn[] = { 1812 static const x86_insn_info avx_cvt_xmm64_insn[] = {
1782 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 64 }, 1813 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 88 },
1783 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 73 }, 1814 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2 , {0x0F, 0x00, 0}, 0, 2, 401 },
1784 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 0, 2, {0x0F, 0x00, 0}, 0, 2, 435 } 1815 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2 , {0x0F, 0x00, 0}, 0, 2, 403 }
1785 }; 1816 };
1786 1817
1787 static const x86_insn_info avx_ssse3_2op_insn[] = { 1818 static const x86_insn_info avx_ssse3_2op_insn[] = {
1788 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0 x38, 0x00}, 0, 2, 57 } 1819 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0 x38, 0x00}, 0, 2, 170 }
1789 }; 1820 };
1790 1821
1791 static const x86_insn_info avx_cvt_xmm128_x_insn[] = { 1822 static const x86_insn_info avx_cvt_xmm128_x_insn[] = {
1792 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 57 } 1823 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 170 }
1793 }; 1824 };
1794 1825
1795 static const x86_insn_info avx_cvt_xmm128_y_insn[] = { 1826 static const x86_insn_info avx_cvt_xmm128_y_insn[] = {
1796 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 0, 2, {0x0F, 0x00, 0}, 0, 2, 239 } 1827 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 190 }
1797 }; 1828 };
1798 1829
1799 static const x86_insn_info avx_cvt_xmm128_insn[] = { 1830 static const x86_insn_info avx_cvt_xmm128_insn[] = {
1800 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 549 }, 1831 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 539 },
1801 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 0, 2, {0x0F, 0x00, 0}, 0, 2, 551 } 1832 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2 , {0x0F, 0x00, 0}, 0, 2, 541 }
1802 }; 1833 };
1803 1834
1804 static const x86_insn_info vbroadcastss_insn[] = { 1835 static const x86_insn_info vbroadcastss_insn[] = {
1805 { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x38, 0x18 }, 0, 2, 125 }, 1836 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x18 }, 0, 2, 288 },
1806 { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0x38, 0x18 }, 0, 2, 455 } 1837 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x1 8}, 0, 2, 437 }
1807 }; 1838 };
1808 1839
1809 static const x86_insn_info vbroadcastsd_insn[] = { 1840 static const x86_insn_info vbroadcastsd_insn[] = {
1810 { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0x38, 0x19 }, 0, 2, 451 } 1841 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x19 }, 0, 2, 423 }
1811 }; 1842 };
1812 1843
1813 static const x86_insn_info vbroadcastf128_insn[] = { 1844 static const x86_insn_info vbroadcastf128_insn[] = {
1814 { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0x38, 0x1A }, 0, 2, 569 } 1845 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x1A }, 0, 2, 547 }
1815 }; 1846 };
1816 1847
1817 static const x86_insn_info vextractf128_insn[] = { 1848 static const x86_insn_info vextractf128_insn[] = {
1818 { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0x3A, 0x19 }, 0, 3, 264 } 1849 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x19 }, 0, 3, 230 }
1819 }; 1850 };
1820 1851
1821 static const x86_insn_info vinsertf128_insn[] = { 1852 static const x86_insn_info vinsertf128_insn[] = {
1822 { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0x3A, 0x18 }, 0, 4, 44 } 1853 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x18 }, 0, 4, 56 }
1823 }; 1854 };
1824 1855
1825 static const x86_insn_info vzero_insn[] = { 1856 static const x86_insn_info vzero_insn[] = {
1826 { 0, 0, CPU_AVX, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x77, 0}, 0 , 0, 0 } 1857 { SUF_Z, 0, CPU_AVX, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0, 2, {0x0F, 0x77, 0}, 0 , 0, 0 }
1827 }; 1858 };
1828 1859
1829 static const x86_insn_info vmaskmov_insn[] = { 1860 static const x86_insn_info vmaskmov_insn[] = {
1830 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0 x38, 0x00}, 0, 3, 40 }, 1861 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0 x38, 0x00}, 0, 3, 52 },
1831 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0 x38, 0x00}, 0, 3, 8 }, 1862 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 3, 8 },
1832 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0 x38, 0x02}, 0, 3, 237 }, 1863 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x02}, 0, 3, 188 },
1833 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0 x38, 0x02}, 0, 3, 240 } 1864 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x02}, 0, 3, 191 }
1834 }; 1865 };
1835 1866
1836 static const x86_insn_info vpermil_insn[] = { 1867 static const x86_insn_info vpermil_insn[] = {
1837 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0 x38, 0x08}, 0, 3, 40 }, 1868 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0 x38, 0x08}, 0, 3, 52 },
1838 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0 x38, 0x08}, 0, 3, 8 }, 1869 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x08}, 0, 3, 8 },
1839 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0 x3A, 0x00}, 0, 3, 77 }, 1870 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 3, 170 },
1840 { 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0 x3A, 0x00}, 0, 3, 225 } 1871 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 3, 176 }
1841 }; 1872 };
1842 1873
1843 static const x86_insn_info vperm2f128_insn[] = { 1874 static const x86_insn_info vperm2f128_insn[] = {
1844 { 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0x3A, 0x06 }, 0, 4, 8 } 1875 { SUF_Z, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x06 }, 0, 4, 8 }
1845 }; 1876 };
1846 1877
1847 static const x86_insn_info vfma_ps_insn[] = { 1878 static const x86_insn_info vfma_ps_insn[] = {
1848 { 0, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0 x38, 0x00}, 0, 3, 40 }, 1879 { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0 x38, 0x00}, 0, 3, 52 },
1849 { 0, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 0, 3, {0x0F, 0 x38, 0x00}, 0, 3, 8 } 1880 { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 3, 8 }
1850 }; 1881 };
1851 1882
1852 static const x86_insn_info vfma_pd_insn[] = { 1883 static const x86_insn_info vfma_pd_insn[] = {
1853 { 0, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 0, 3, {0x0F, 0 x38, 0x00}, 0, 3, 40 }, 1884 { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0 x38, 0x00}, 0, 3, 52 },
1854 { 0, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xCD, 0, 3, {0x0F, 0 x38, 0x00}, 0, 3, 8 } 1885 { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xCD, 3, {0x0F, 0x38, 0x00}, 0, 3, 8 }
1855 }; 1886 };
1856 1887
1857 static const x86_insn_info vfma_ss_insn[] = { 1888 static const x86_insn_info vfma_ss_insn[] = {
1858 { 0, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0 x38, 0x00}, 0, 3, 0 }, 1889 { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0 x38, 0x00}, 0, 3, 0 },
1859 { 0, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0 x38, 0x00}, 0, 3, 36 } 1890 { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 48 }
1860 }; 1891 };
1861 1892
1862 static const x86_insn_info vfma_sd_insn[] = { 1893 static const x86_insn_info vfma_sd_insn[] = {
1863 { 0, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 0, 3, {0x0F, 0 x38, 0x00}, 0, 3, 0 }, 1894 { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0 x38, 0x00}, 0, 3, 0 },
1864 { 0, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 0, 3, {0x0F, 0 x38, 0x00}, 0, 3, 4 } 1895 { SUF_Z, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x38, 0x00}, 0, 3, 4 }
1865 }; 1896 };
1866 1897
1867 static const x86_insn_info aes_insn[] = { 1898 static const x86_insn_info aes_insn[] = {
1868 { 0, 0, CPU_AES, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 0, 3, {0x0F, 0x00, 0x00}, 0, 2, 195 }, 1899 { SUF_Z, 0, CPU_AES, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 3, {0x0F, 0x00, 0x00}, 0, 2, 143 },
1869 { 0, ONLY_AVX, CPU_AES, CPU_AVX, 0, {MOD_Op1Add, MOD_Op2Add, 0}, 0, 0, 0xC1, 0, 3, {0x0F, 0x00, 0x00}, 0, 3, 40 } 1900 { SUF_Z, ONLY_AVX, CPU_AES, CPU_AVX, 0, {MOD_Op1Add, MOD_Op2Add, 0}, 0, 0, 0 xC1, 3, {0x0F, 0x00, 0x00}, 0, 3, 52 }
1870 }; 1901 };
1871 1902
1872 static const x86_insn_info aesimc_insn[] = { 1903 static const x86_insn_info aesimc_insn[] = {
1873 { 0, 0, CPU_AES, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 0, 3, {0x0F, 0x00, 0x00}, 0, 2, 195 } 1904 { SUF_Z, 0, CPU_AES, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 3, {0x0F, 0x00, 0x00}, 0, 2, 170 }
1874 }; 1905 };
1875 1906
1876 static const x86_insn_info aes_imm_insn[] = { 1907 static const x86_insn_info aes_imm_insn[] = {
1877 { 0, 0, CPU_AES, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 0, 3, {0x0F, 0x00, 0x00}, 0, 3, 77 } 1908 { SUF_Z, 0, CPU_AES, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 3, {0x0F, 0x00, 0x00}, 0, 3, 170 }
1878 }; 1909 };
1879 1910
1880 static const x86_insn_info pclmulqdq_insn[] = { 1911 static const x86_insn_info pclmulqdq_insn[] = {
1881 { 0, 0, CPU_CLMUL, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 0 , 3, {0x0F, 0x00, 0x00}, 0, 3, 195 }, 1912 { SUF_Z, 0, CPU_CLMUL, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66 , 3, {0x0F, 0x00, 0x00}, 0, 3, 143 },
1882 { 0, ONLY_AVX, CPU_AVX, CPU_CLMUL, 0, {MOD_Op1Add, MOD_Op2Add, 0}, 0, 0, 0xC 1, 0, 3, {0x0F, 0x00, 0x00}, 0, 4, 40 } 1913 { SUF_Z, ONLY_AVX, CPU_AVX, CPU_CLMUL, 0, {MOD_Op1Add, MOD_Op2Add, 0}, 0, 0, 0xC1, 3, {0x0F, 0x00, 0x00}, 0, 4, 52 }
1883 }; 1914 };
1884 1915
1885 static const x86_insn_info pclmulqdq_fixed_insn[] = { 1916 static const x86_insn_info pclmulqdq_fixed_insn[] = {
1886 { 0, 0, CPU_CLMUL, 0, 0, {MOD_Imm8, MOD_SetVEX, 0}, 0, 0, 0x66, 0, 3, {0x0F, 0x3A, 0x44}, 0, 2, 195 }, 1917 { SUF_Z, 0, CPU_CLMUL, 0, 0, {MOD_Imm8, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x44}, 0, 2, 143 },
1887 { 0, ONLY_AVX, CPU_AVX, CPU_CLMUL, 0, {MOD_Imm8, 0, 0}, 0, 0, 0xC1, 0, 3, {0 x0F, 0x3A, 0x44}, 0, 3, 40 } 1918 { SUF_Z, ONLY_AVX, CPU_AVX, CPU_CLMUL, 0, {MOD_Imm8, 0, 0}, 0, 0, 0xC1, 3, { 0x0F, 0x3A, 0x44}, 0, 3, 52 }
1919 };
1920
1921 static const x86_insn_info rdrand_insn[] = {
1922 { SUF_Z, 0, CPU_RDRAND, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xC7, 0}, 6, 1, 347 },
1923 { SUF_Z, 0, CPU_386, CPU_RDRAND, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xC7, 0}, 6, 1, 14 },
1924 { SUF_Z, ONLY_64, CPU_RDRAND, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC7, 0}, 6, 1, 18 }
1925 };
1926
1927 static const x86_insn_info fs_gs_base_insn[] = {
1928 { SUF_Z, ONLY_64, CPU_FSGSBASE, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0xF3, 2, {0x0 F, 0xAE, 0}, 0, 1, 14 },
1929 { SUF_Z, ONLY_64, CPU_FSGSBASE, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0xF3, 2, {0x 0F, 0xAE, 0}, 0, 1, 18 }
1930 };
1931
1932 static const x86_insn_info avx_cvtps2ph_insn[] = {
1933 { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0 xC0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 194 },
1934 { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 197 },
1935 { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC4, 3, {0x0F, 0x3A, 0x00}, 0, 3, 200 },
1936 { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC4, 3, {0x0F, 0x3A, 0x00}, 0, 3, 203 }
1937 };
1938
1939 static const x86_insn_info avx_cvtph2ps_insn[] = {
1940 { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0 xC0, 3, {0x0F, 0x38, 0x00}, 0, 2, 88 },
1941 { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC0, 3, {0x0F, 0x38, 0x00}, 0, 2, 561 },
1942 { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC4, 3, {0x0F, 0x38, 0x00}, 0, 2, 193 },
1943 { SUF_Z, ONLY_AVX, CPU_AVX, CPU_F16C, 0, {MOD_PreAdd, MOD_Op2Add, 0}, 0, 0, 0xC4, 3, {0x0F, 0x38, 0x00}, 0, 2, 563 }
1888 }; 1944 };
1889 1945
1890 static const x86_insn_info extrq_insn[] = { 1946 static const x86_insn_info extrq_insn[] = {
1891 { 0, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x78, 0}, 0, 3, 65 }, 1947 { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x78, 0}, 0, 3, 89 },
1892 { 0, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0x66, 0, 2, {0x0F, 0x79, 0}, 0, 2, 64 } 1948 { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x79, 0}, 0, 2 , 88 }
1893 }; 1949 };
1894 1950
1895 static const x86_insn_info insertq_insn[] = { 1951 static const x86_insn_info insertq_insn[] = {
1896 { 0, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0x78, 0}, 0, 4, 64 }, 1952 { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x78, 0}, 0, 4, 88 },
1897 { 0, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0x79, 0}, 0, 2, 64 } 1953 { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x79, 0}, 0, 2 , 88 }
1898 }; 1954 };
1899 1955
1900 static const x86_insn_info movntsd_insn[] = { 1956 static const x86_insn_info movntsd_insn[] = {
1901 { 0, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 0, 2, {0x0F, 0x2B, 0}, 0, 2, 106 } 1957 { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x2B, 0}, 0, 2, 39 }
1902 }; 1958 };
1903 1959
1904 static const x86_insn_info movntss_insn[] = { 1960 static const x86_insn_info movntss_insn[] = {
1905 { 0, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 0, 2, {0x0F, 0x2B, 0}, 0, 2, 134 } 1961 { SUF_Z, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x2B, 0}, 0, 2, 529 }
1906 }; 1962 };
1907 1963
1908 static const x86_insn_info sse5com_insn[] = { 1964 static const x86_insn_info vfrc_pdps_insn[] = {
1909 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x25, 0 x00}, 0, 4, 76 } 1965 { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x80, 0} , 0, 2, 170 },
1910 }; 1966 { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x84, 2, {0x09, 0x80, 0 }, 0, 2, 176 }
1911 1967 };
1912 static const x86_insn_info sse5com32_insn[] = { 1968
1913 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x25, 0 x00}, 0, 4, 68 }, 1969 static const x86_insn_info vfrczsd_insn[] = {
1914 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x25, 0 x00}, 0, 4, 124 } 1970 { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x83, 0}, 0, 2, 8 8 },
1915 }; 1971 { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x83, 0}, 0, 2, 401 }
1916 1972 };
1917 static const x86_insn_info sse5com64_insn[] = { 1973
1918 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x25, 0 x00}, 0, 4, 68 }, 1974 static const x86_insn_info vfrczss_insn[] = {
1919 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x25, 0 x00}, 0, 4, 72 } 1975 { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x82, 0}, 0, 2, 8 8 },
1920 }; 1976 { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x82, 0}, 0, 2, 288 }
1921 1977 };
1922 static const x86_insn_info sse5comcc_insn[] = { 1978
1923 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, MOD_Imm8, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x25, 0x00}, 0, 3, 56 } 1979 static const x86_insn_info vpcmov_insn[] = {
1924 }; 1980 { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x08, 0xA2, 0}, 0, 4, 6 0 },
1925 1981 { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x88, 2, {0x08, 0xA2, 0}, 0, 4, 80 },
1926 static const x86_insn_info sse5comcc32_insn[] = { 1982 { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x84, 2, {0x08, 0xA2, 0}, 0, 4, 64 },
1927 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, MOD_Imm8, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x25, 0x00}, 0, 3, 68 }, 1983 { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x8C, 2, {0x08, 0xA2, 0}, 0, 4, 84 }
1928 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, MOD_Imm8, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x25, 0x00}, 0, 3, 124 } 1984 };
1929 }; 1985
1930 1986 static const x86_insn_info vpcom_insn[] = {
1931 static const x86_insn_info sse5comcc64_insn[] = { 1987 { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, MOD_Imm8, 0}, 0, 0, 0x80, 2, {0x08, 0 x00, 0}, 0, 3, 52 }
1932 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, MOD_Imm8, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x25, 0x00}, 0, 3, 68 }, 1988 };
1933 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, MOD_Imm8, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x25, 0x00}, 0, 3, 72 } 1989
1934 }; 1990 static const x86_insn_info vpcom_imm_insn[] = {
1935 1991 { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x08, 0x00, 0} , 0, 4, 52 }
1936 static const x86_insn_info cvtph2ps_insn[] = { 1992 };
1937 { 0, 0, CPU_SSE5, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7A, 0x30}, 0, 2, 64 }, 1993
1938 { 0, 0, CPU_SSE5, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7A, 0x30}, 0, 2, 73 } 1994 static const x86_insn_info vphaddsub_insn[] = {
1939 }; 1995 { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x00, 0} , 0, 2, 170 }
1940 1996 };
1941 static const x86_insn_info cvtps2ph_insn[] = { 1997
1942 { 0, 0, CPU_SSE5, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7A, 0x31}, 0, 2, 102 }, 1998 static const x86_insn_info vpma_insn[] = {
1943 { 0, 0, CPU_SSE5, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7A, 0x31}, 0, 2, 106 } 1999 { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x08, 0x00, 0} , 0, 4, 60 }
1944 }; 2000 };
1945 2001
1946 static const x86_insn_info sse5arith_insn[] = { 2002 static const x86_insn_info vpperm_insn[] = {
1947 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0 x00}, 0, 4, 80 }, 2003 { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x08, 0xA3, 0}, 0, 4, 6 0 },
1948 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0 x00}, 0, 4, 84 }, 2004 { SUF_Z, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x88, 2, {0x08, 0xA3, 0}, 0, 4, 80 }
1949 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0 x04}, 0, 4, 56 }, 2005 };
1950 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0 x04}, 0, 4, 88 } 2006
1951 }; 2007 static const x86_insn_info vprot_insn[] = {
1952 2008 { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x90, 0} , 0, 3, 182 },
1953 static const x86_insn_info sse5arith32_insn[] = { 2009 { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x88, 2, {0x09, 0x90, 0 }, 0, 3, 52 },
1954 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0 x00}, 0, 4, 92 }, 2010 { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x08, 0xC0, 0 }, 0, 3, 170 }
1955 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0 x00}, 0, 4, 128 }, 2011 };
1956 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0 x00}, 0, 4, 100 }, 2012
1957 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0 x00}, 0, 4, 132 }, 2013 static const x86_insn_info amd_vpshift_insn[] = {
1958 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0 x04}, 0, 4, 108 }, 2014 { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x00, 0} , 0, 3, 182 },
1959 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0 x04}, 0, 4, 136 }, 2015 { SUF_Z, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x88, 2, {0x09, 0x00, 0 }, 0, 3, 52 }
1960 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0 x04}, 0, 4, 116 }, 2016 };
1961 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0 x04}, 0, 4, 140 } 2017
1962 }; 2018 static const x86_insn_info fma_128_256_insn[] = {
1963 2019 { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 60 },
1964 static const x86_insn_info sse5arith64_insn[] = { 2020 { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x3A, 0x00}, 0, 4, 80 },
1965 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0 x00}, 0, 4, 92 }, 2021 { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 4, 64 },
1966 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0 x00}, 0, 4, 96 }, 2022 { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xCD, 3, {0x0F, 0x3A, 0x00}, 0, 4, 84 }
1967 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0 x00}, 0, 4, 100 }, 2023 };
1968 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0 x00}, 0, 4, 104 }, 2024
1969 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0 x04}, 0, 4, 108 }, 2025 static const x86_insn_info fma_128_m32_insn[] = {
1970 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0 x04}, 0, 4, 112 }, 2026 { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 28 },
1971 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0 x04}, 0, 4, 116 }, 2027 { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 68 },
1972 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0 x04}, 0, 4, 120 } 2028 { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x3A, 0x00}, 0, 4, 72 }
1973 }; 2029 };
1974 2030
1975 static const x86_insn_info sse5two_insn[] = { 2031 static const x86_insn_info fma_128_m64_insn[] = {
1976 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7A, 0x00 }, 0, 2, 57 } 2032 { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 28 },
1977 }; 2033 { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 32 },
1978 2034 { SUF_Z, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x3A, 0x00}, 0, 4, 36 }
1979 static const x86_insn_info sse5two32_insn[] = { 2035 };
1980 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7A, 0x00 }, 0, 2, 64 }, 2036
1981 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7A, 0x00 }, 0, 2, 125 } 2037 static const x86_insn_info xsaveopt64_insn[] = {
1982 }; 2038 { SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, MOD_Op0Add, MOD_Op1Add}, 64, 0, 0, 2, {0x00, 0x00, 0}, 0, 1, 470 }
1983
1984 static const x86_insn_info sse5two64_insn[] = {
1985 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7A, 0x00 }, 0, 2, 64 },
1986 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7A, 0x00 }, 0, 2, 73 }
1987 };
1988
1989 static const x86_insn_info sse5pmacs_insn[] = {
1990 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0 x00}, 0, 4, 56 }
1991 };
1992
1993 static const x86_insn_info sse5prot_insn[] = {
1994 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0 x40}, 0, 3, 56 },
1995 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0 x40}, 0, 3, 88 },
1996 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x7B, 0x40 }, 0, 3, 77 }
1997 };
1998
1999 static const x86_insn_info sse5psh_insn[] = {
2000 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x80, 3, {0x0F, 0x24, 0 x44}, 0, 3, 56 },
2001 { 0, 0, CPU_SSE5, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0x88, 3, {0x0F, 0x24, 0 x44}, 0, 3, 88 }
2002 }; 2039 };
2003 2040
2004 static const x86_insn_info movbe_insn[] = { 2041 static const x86_insn_info movbe_insn[] = {
2005 { 0, 0, CPU_MOVBE, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 3, {0x0F, 0x38, 0xF0}, 0, 2 , 437 }, 2042 { SUF_Z, 0, CPU_MOVBE, 0, 0, {0, 0, 0}, 16, 0, 0, 3, {0x0F, 0x38, 0xF0}, 0, 2 , 405 },
2006 { 0, 0, CPU_MOVBE, 0, 0, {0, 0, 0}, 16, 0, 0, 0, 3, {0x0F, 0x38, 0xF1}, 0, 2 , 439 }, 2043 { SUF_Z, 0, CPU_MOVBE, 0, 0, {0, 0, 0}, 16, 0, 0, 3, {0x0F, 0x38, 0xF1}, 0, 2, 407 },
2007 { 0, 0, CPU_386, CPU_MOVBE, 0, {0, 0, 0}, 32, 0, 0, 0, 3, {0x0F, 0x38, 0xF0} , 0, 2, 345 }, 2044 { SUF_Z, 0, CPU_386, CPU_MOVBE, 0, {0, 0, 0}, 32, 0, 0, 3, {0x0F, 0x38, 0xF0 }, 0, 2, 311 },
2008 { 0, 0, CPU_386, CPU_MOVBE, 0, {0, 0, 0}, 32, 0, 0, 0, 3, {0x0F, 0x38, 0xF1} , 0, 2, 323 }, 2045 { SUF_Z, 0, CPU_386, CPU_MOVBE, 0, {0, 0, 0}, 32, 0, 0, 3, {0x0F, 0x38, 0xF1 }, 0, 2, 289 },
2009 { 0, ONLY_64, CPU_MOVBE, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 3, {0x0F, 0x38, 0xF0} , 0, 2, 441 }, 2046 { SUF_Z, ONLY_64, CPU_MOVBE, 0, 0, {0, 0, 0}, 64, 0, 0, 3, {0x0F, 0x38, 0xF0 }, 0, 2, 409 },
2010 { 0, ONLY_64, CPU_MOVBE, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 3, {0x0F, 0x38, 0xF1} , 0, 2, 325 } 2047 { SUF_Z, ONLY_64, CPU_MOVBE, 0, 0, {0, 0, 0}, 64, 0, 0, 3, {0x0F, 0x38, 0xF1 }, 0, 2, 291 }
2011 }; 2048 };
2012 2049
2013 static const x86_insn_info now3d_insn[] = { 2050 static const x86_insn_info now3d_insn[] = {
2014 { 0, 0, CPU_3DNow, 0, 0, {MOD_Imm8, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x0F, 0}, 0 , 2, 234 } 2051 { SUF_Z, 0, CPU_3DNow, 0, 0, {MOD_Imm8, 0, 0}, 0, 0, 0, 2, {0x0F, 0x0F, 0}, 0 , 2, 185 }
2015 }; 2052 };
2016 2053
2017 static const x86_insn_info cmpxchg16b_insn[] = { 2054 static const x86_insn_info cmpxchg16b_insn[] = {
2018 { 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, 2, {0x0F, 0xC7, 0}, 1, 1, 540 } 2055 { SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC7, 0}, 1, 1, 528 }
2019 }; 2056 };
2020 2057
2021 static const x86_insn_info invlpga_insn[] = { 2058 static const x86_insn_info invlpga_insn[] = {
2022 { 0, 0, CPU_SVM, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x01, 0xDF}, 0, 0, 0 }, 2059 { SUF_Z, 0, CPU_SVM, 0, 0, {0, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0xDF}, 0, 0, 0 },
2023 { 0, 0, CPU_386, CPU_SVM, 0, {0, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x01, 0xDF}, 0 , 2, 471 } 2060 { SUF_Z, 0, CPU_386, CPU_SVM, 0, {0, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0xDF}, 0, 2, 453 }
2024 }; 2061 };
2025 2062
2026 static const x86_insn_info skinit_insn[] = { 2063 static const x86_insn_info skinit_insn[] = {
2027 { 0, 0, CPU_SVM, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x01, 0xDE}, 0, 0, 0 }, 2064 { SUF_Z, 0, CPU_SVM, 0, 0, {0, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0xDE}, 0, 0, 0 },
2028 { 0, 0, CPU_SVM, 0, 0, {0, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x01, 0xDE}, 0, 1, 6 10 } 2065 { SUF_Z, 0, CPU_SVM, 0, 0, {0, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0xDE}, 0, 1, 579 }
2029 }; 2066 };
2030 2067
2031 static const x86_insn_info svm_rax_insn[] = { 2068 static const x86_insn_info svm_rax_insn[] = {
2032 { 0, 0, CPU_SVM, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x01, 0x00} , 0, 0, 0 }, 2069 { SUF_Z, 0, CPU_SVM, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0x00} , 0, 0, 0 },
2033 { 0, 0, CPU_SVM, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 0, 3, {0x0F, 0x01, 0x00} , 0, 1, 471 } 2070 { SUF_Z, 0, CPU_SVM, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0x00 }, 0, 1, 453 }
2034 }; 2071 };
2035 2072
2036 static const x86_insn_info padlock_insn[] = { 2073 static const x86_insn_info padlock_insn[] = {
2037 { 0, 0, CPU_PadLock, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_Op1Add}, 0, 0, 0x00, 0 , 2, {0x0F, 0x00, 0}, 0, 0, 0 } 2074 { SUF_Z, 0, CPU_PadLock, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_Op1Add}, 0, 0, 0x00 , 2, {0x0F, 0x00, 0}, 0, 0, 0 }
2038 }; 2075 };
2039 2076
2040 static const x86_insn_info cyrixmmx_insn[] = { 2077 static const x86_insn_info cyrixmmx_insn[] = {
2041 { 0, 0, CPU_Cyrix, CPU_MMX, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x0 0, 0}, 0, 2, 234 } 2078 { SUF_Z, 0, CPU_Cyrix, CPU_MMX, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x0 0, 0}, 0, 2, 185 }
2042 }; 2079 };
2043 2080
2044 static const x86_insn_info pmachriw_insn[] = { 2081 static const x86_insn_info pmachriw_insn[] = {
2045 { 0, 0, CPU_Cyrix, CPU_MMX, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x5E, 0}, 0, 2, 303 } 2082 { SUF_Z, 0, CPU_Cyrix, CPU_MMX, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x5E, 0}, 0, 2, 269 }
2046 }; 2083 };
2047 2084
2048 static const x86_insn_info rdwrshr_insn[] = { 2085 static const x86_insn_info rdwrshr_insn[] = {
2049 { 0, 0, CPU_686, CPU_Cyrix, CPU_SMM, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0 F, 0x36, 0}, 0, 1, 26 } 2086 { SUF_Z, 0, CPU_686, CPU_Cyrix, CPU_SMM, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0 F, 0x36, 0}, 0, 1, 26 }
2050 }; 2087 };
2051 2088
2052 static const x86_insn_info rsdc_insn[] = { 2089 static const x86_insn_info rsdc_insn[] = {
2053 { 0, 0, CPU_486, CPU_Cyrix, CPU_SMM, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x79, 0}, 0, 2, 493 } 2090 { SUF_Z, 0, CPU_486, CPU_Cyrix, CPU_SMM, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x79, 0}, 0, 2, 497 }
2054 }; 2091 };
2055 2092
2056 static const x86_insn_info cyrixsmm_insn[] = { 2093 static const x86_insn_info cyrixsmm_insn[] = {
2057 { 0, 0, CPU_486, CPU_Cyrix, CPU_SMM, {MOD_Op1Add, 0, 0}, 0, 0, 0, 0, 2, {0x0 F, 0x00, 0}, 0, 1, 494 } 2094 { SUF_Z, 0, CPU_486, CPU_Cyrix, CPU_SMM, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0 F, 0x00, 0}, 0, 1, 498 }
2058 }; 2095 };
2059 2096
2060 static const x86_insn_info svdc_insn[] = { 2097 static const x86_insn_info svdc_insn[] = {
2061 { 0, 0, CPU_486, CPU_Cyrix, CPU_SMM, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x78, 0}, 0, 2, 571 } 2098 { SUF_Z, 0, CPU_486, CPU_Cyrix, CPU_SMM, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x78, 0}, 0, 2, 549 }
2062 }; 2099 };
2063 2100
2064 static const x86_insn_info ibts_insn[] = { 2101 static const x86_insn_info ibts_insn[] = {
2065 { 0, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0xA7, 0}, 0, 2, 246 }, 2102 { SUF_Z, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA7, 0}, 0, 2, 212 },
2066 { 0, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0xA7, 0}, 0, 2, 252 } 2103 { SUF_Z, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA7 , 0}, 0, 2, 218 }
2067 }; 2104 };
2068 2105
2069 static const x86_insn_info umov_insn[] = { 2106 static const x86_insn_info umov_insn[] = {
2070 { 0, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x10, 0}, 0, 2, 309 }, 2107 { SUF_Z, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x10, 0}, 0, 2, 275 },
2071 { 0, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x11, 0}, 0 , 2, 246 }, 2108 { SUF_Z, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0x11, 0}, 0, 2, 212 },
2072 { 0, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x11, 0}, 0 , 2, 252 }, 2109 { SUF_Z, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0x11, 0}, 0, 2, 218 },
2073 { 0, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 0, 0, 0, 0, 2, {0x0F, 0x12, 0}, 0, 2, 311 }, 2110 { SUF_Z, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x12, 0}, 0 , 2, 277 },
2074 { 0, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0x13, 0}, 0 , 2, 150 }, 2111 { SUF_Z, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0x13, 0}, 0, 2, 98 },
2075 { 0, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0x13, 0}, 0 , 2, 153 } 2112 { SUF_Z, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0x13, 0}, 0, 2, 101 }
2076 }; 2113 };
2077 2114
2078 static const x86_insn_info xbts_insn[] = { 2115 static const x86_insn_info xbts_insn[] = {
2079 { 0, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 16, 0, 0, 0, 2, {0x0F, 0xA6, 0}, 0, 2, 437 }, 2116 { SUF_Z, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA6, 0}, 0, 2, 405 },
2080 { 0, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 32, 0, 0, 0, 2, {0x0F, 0xA6, 0}, 0, 2, 345 } 2117 { SUF_Z, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA6 , 0}, 0, 2, 311 }
2081 }; 2118 };
2082 2119
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