Add 1.2GHz cpu clock support for T25

arch/arm/mach-tegra/tegra2_clocks.c

Index: arch/arm/mach-tegra/tegra2_clocks.c
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 1622de8bd06510aa37a750234f287f1f4a71bdda..6708a36ede9961219938bf4305fb0379dd326a17 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -694,10 +694,17 @@ static struct clk_ops tegra_pll_ops = {
 
 static void tegra2_pllx_clk_init(struct clk *c)
 {
+	int sku_id = tegra_sku_id();
+
 	tegra2_pll_clk_init(c);
 
-	if (tegra_sku_id() == 7)
+	if (sku_id == 7) {
 		c->max_rate = 750000000;
+	} else if (sku_id == SKU_ID_T20) {
+		/* make adjustment for T20 */
+		/* the default max_rate is set at 1.2GHz for T25 */
+		c->max_rate = 1000000000;
+	}
 }
 
 static struct clk_ops tegra_pllx_ops = {
@@ -1513,6 +1520,12 @@ static struct clk tegra_pll_u = {
 };
 
 static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
+	/* 1.2 GHz */
+	{ 12000000, 1200000000,  600,  6, 1, 12},
+	{ 13000000, 1200000000,  923, 10, 1, 12},
+	{ 19200000, 1200000000,  750, 12, 1,  8},
+	{ 26000000, 1200000000,  600, 13, 1, 12},
+
 	/* 1 GHz */
 	{ 12000000, 1000000000, 1000, 12, 1, 12},
 	{ 13000000, 1000000000, 1000, 13, 1, 12},
@@ -1564,7 +1577,7 @@ static struct clk tegra_pll_x = {
 	.ops       = &tegra_pllx_ops,
 	.reg       = 0xe0,
 	.parent    = &tegra_clk_m,
-	.max_rate  = 1000000000,
+	.max_rate  = 1200000000,
 	.u.pll = {
 		.input_min = 2000000,
 		.input_max = 31000000,
@@ -1713,7 +1726,7 @@ static struct clk tegra_clk_cclk = {
 	.inputs	= mux_cclk,
 	.reg	= 0x20,
 	.ops	= &tegra_super_ops,
-	.max_rate = 1000000000,
+	.max_rate = 1200000000,
 };
 
 static struct clk tegra_clk_sclk = {
@@ -1731,7 +1744,7 @@ static struct clk tegra_clk_virtual_cpu = {
 	.name      = "cpu",
 	.parent    = &tegra_clk_cclk,
 	.ops       = &tegra_cpu_ops,
-	.max_rate  = 1000000000,
+	.max_rate  = 1200000000,
 	.u.cpu = {
 		.main      = &tegra_pll_x,
 		.backup    = &tegra_pll_p,