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Side by Side Diff: arch/arm/mach-tegra/tegra2_clocks.c

Issue 6116004: Add 1.2GHz cpu clock support for T25 (Closed) Base URL: http://git.chromium.org/git/kernel-next.git@chromeos-2.6.36
Patch Set: Fix places as indicated by Olof's comments. Created 9 years, 11 months ago
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1 /* 1 /*
2 * arch/arm/mach-tegra/tegra2_clocks.c 2 * arch/arm/mach-tegra/tegra2_clocks.c
3 * 3 *
4 * Copyright (C) 2010 Google, Inc. 4 * Copyright (C) 2010 Google, Inc.
5 * 5 *
6 * Author: 6 * Author:
7 * Colin Cross <ccross@google.com> 7 * Colin Cross <ccross@google.com>
8 * 8 *
9 * This software is licensed under the terms of the GNU General Public 9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and 10 * License version 2, as published by the Free Software Foundation, and
(...skipping 676 matching lines...) Expand 10 before | Expand all | Expand 10 after
687 687
688 static struct clk_ops tegra_pll_ops = { 688 static struct clk_ops tegra_pll_ops = {
689 .init = tegra2_pll_clk_init, 689 .init = tegra2_pll_clk_init,
690 .enable = tegra2_pll_clk_enable, 690 .enable = tegra2_pll_clk_enable,
691 .disable = tegra2_pll_clk_disable, 691 .disable = tegra2_pll_clk_disable,
692 .set_rate = tegra2_pll_clk_set_rate, 692 .set_rate = tegra2_pll_clk_set_rate,
693 }; 693 };
694 694
695 static void tegra2_pllx_clk_init(struct clk *c) 695 static void tegra2_pllx_clk_init(struct clk *c)
696 { 696 {
697 int sku_id = tegra_sku_id();
698
697 tegra2_pll_clk_init(c); 699 tegra2_pll_clk_init(c);
698 700
699 » if (tegra_sku_id() == 7) 701 » if (sku_id == 7) {
700 c->max_rate = 750000000; 702 c->max_rate = 750000000;
703 } else if (sku_id == SKU_ID_T20) {
704 /* make adjustment for T20 */
705 /* the default max_rate is set at 1.2GHz for T25 */
706 c->max_rate = 1000000000;
707 }
701 } 708 }
702 709
703 static struct clk_ops tegra_pllx_ops = { 710 static struct clk_ops tegra_pllx_ops = {
704 .init = tegra2_pllx_clk_init, 711 .init = tegra2_pllx_clk_init,
705 .enable = tegra2_pll_clk_enable, 712 .enable = tegra2_pll_clk_enable,
706 .disable = tegra2_pll_clk_disable, 713 .disable = tegra2_pll_clk_disable,
707 .set_rate = tegra2_pll_clk_set_rate, 714 .set_rate = tegra2_pll_clk_set_rate,
708 }; 715 };
709 716
710 /* Clock divider ops */ 717 /* Clock divider ops */
(...skipping 795 matching lines...) Expand 10 before | Expand all | Expand 10 after
1506 .cf_min = 1000000, 1513 .cf_min = 1000000,
1507 .cf_max = 6000000, 1514 .cf_max = 6000000,
1508 .vco_min = 480000000, 1515 .vco_min = 480000000,
1509 .vco_max = 960000000, 1516 .vco_max = 960000000,
1510 .freq_table = tegra_pll_u_freq_table, 1517 .freq_table = tegra_pll_u_freq_table,
1511 .lock_delay = 1000, 1518 .lock_delay = 1000,
1512 }, 1519 },
1513 }; 1520 };
1514 1521
1515 static struct clk_pll_freq_table tegra_pll_x_freq_table[] = { 1522 static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
1523 /* 1.2 GHz */
1524 { 12000000, 1200000000, 600, 6, 1, 12},
1525 { 13000000, 1200000000, 923, 10, 1, 12},
1526 { 19200000, 1200000000, 750, 12, 1, 8},
1527 { 26000000, 1200000000, 600, 13, 1, 12},
1528
1516 /* 1 GHz */ 1529 /* 1 GHz */
1517 { 12000000, 1000000000, 1000, 12, 1, 12}, 1530 { 12000000, 1000000000, 1000, 12, 1, 12},
1518 { 13000000, 1000000000, 1000, 13, 1, 12}, 1531 { 13000000, 1000000000, 1000, 13, 1, 12},
1519 { 19200000, 1000000000, 625, 12, 1, 8}, 1532 { 19200000, 1000000000, 625, 12, 1, 8},
1520 { 26000000, 1000000000, 1000, 26, 1, 12}, 1533 { 26000000, 1000000000, 1000, 26, 1, 12},
1521 1534
1522 /* 912 MHz */ 1535 /* 912 MHz */
1523 { 12000000, 912000000, 912, 12, 1, 12}, 1536 { 12000000, 912000000, 912, 12, 1, 12},
1524 { 13000000, 912000000, 912, 13, 1, 12}, 1537 { 13000000, 912000000, 912, 13, 1, 12},
1525 { 19200000, 912000000, 760, 16, 1, 8}, 1538 { 19200000, 912000000, 760, 16, 1, 8},
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1557 1570
1558 { 0, 0, 0, 0, 0, 0 }, 1571 { 0, 0, 0, 0, 0, 0 },
1559 }; 1572 };
1560 1573
1561 static struct clk tegra_pll_x = { 1574 static struct clk tegra_pll_x = {
1562 .name = "pll_x", 1575 .name = "pll_x",
1563 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG, 1576 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
1564 .ops = &tegra_pllx_ops, 1577 .ops = &tegra_pllx_ops,
1565 .reg = 0xe0, 1578 .reg = 0xe0,
1566 .parent = &tegra_clk_m, 1579 .parent = &tegra_clk_m,
1567 » .max_rate = 1000000000, 1580 » .max_rate = 1200000000,
1568 .u.pll = { 1581 .u.pll = {
1569 .input_min = 2000000, 1582 .input_min = 2000000,
1570 .input_max = 31000000, 1583 .input_max = 31000000,
1571 .cf_min = 1000000, 1584 .cf_min = 1000000,
1572 .cf_max = 6000000, 1585 .cf_max = 6000000,
1573 .vco_min = 20000000, 1586 .vco_min = 20000000,
1574 .vco_max = 1200000000, 1587 .vco_max = 1200000000,
1575 .freq_table = tegra_pll_x_freq_table, 1588 .freq_table = tegra_pll_x_freq_table,
1576 .lock_delay = 300, 1589 .lock_delay = 300,
1577 }, 1590 },
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1706 { .input = &tegra_clk_32k, .value = 6}, 1719 { .input = &tegra_clk_32k, .value = 6},
1707 { .input = &tegra_pll_m_out1, .value = 7}, 1720 { .input = &tegra_pll_m_out1, .value = 7},
1708 { 0, 0}, 1721 { 0, 0},
1709 }; 1722 };
1710 1723
1711 static struct clk tegra_clk_cclk = { 1724 static struct clk tegra_clk_cclk = {
1712 .name = "cclk", 1725 .name = "cclk",
1713 .inputs = mux_cclk, 1726 .inputs = mux_cclk,
1714 .reg = 0x20, 1727 .reg = 0x20,
1715 .ops = &tegra_super_ops, 1728 .ops = &tegra_super_ops,
1716 » .max_rate = 1000000000, 1729 » .max_rate = 1200000000,
1717 }; 1730 };
1718 1731
1719 static struct clk tegra_clk_sclk = { 1732 static struct clk tegra_clk_sclk = {
1720 .name = "sclk", 1733 .name = "sclk",
1721 .inputs = mux_sclk, 1734 .inputs = mux_sclk,
1722 .reg = 0x28, 1735 .reg = 0x28,
1723 .ops = &tegra_super_ops, 1736 .ops = &tegra_super_ops,
1724 .max_rate = 240000000, 1737 .max_rate = 240000000,
1725 .u.shared_bus = { 1738 .u.shared_bus = {
1726 .min_rate = 120000000, 1739 .min_rate = 120000000,
1727 }, 1740 },
1728 }; 1741 };
1729 1742
1730 static struct clk tegra_clk_virtual_cpu = { 1743 static struct clk tegra_clk_virtual_cpu = {
1731 .name = "cpu", 1744 .name = "cpu",
1732 .parent = &tegra_clk_cclk, 1745 .parent = &tegra_clk_cclk,
1733 .ops = &tegra_cpu_ops, 1746 .ops = &tegra_cpu_ops,
1734 » .max_rate = 1000000000, 1747 » .max_rate = 1200000000,
1735 .u.cpu = { 1748 .u.cpu = {
1736 .main = &tegra_pll_x, 1749 .main = &tegra_pll_x,
1737 .backup = &tegra_pll_p, 1750 .backup = &tegra_pll_p,
1738 }, 1751 },
1739 }; 1752 };
1740 1753
1741 static struct clk tegra_clk_cop = { 1754 static struct clk tegra_clk_cop = {
1742 .name = "cop", 1755 .name = "cop",
1743 .parent = &tegra_clk_sclk, 1756 .parent = &tegra_clk_sclk,
1744 .ops = &tegra_cop_ops, 1757 .ops = &tegra_cop_ops,
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2155 2168
2156 off = CLK_OUT_ENB; 2169 off = CLK_OUT_ENB;
2157 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4) 2170 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
2158 clk_writel(*ctx++, off); 2171 clk_writel(*ctx++, off);
2159 wmb(); 2172 wmb();
2160 2173
2161 clk_writel(*ctx++, MISC_CLK_ENB); 2174 clk_writel(*ctx++, MISC_CLK_ENB);
2162 clk_writel(*ctx++, CLK_MASK_ARM); 2175 clk_writel(*ctx++, CLK_MASK_ARM);
2163 } 2176 }
2164 #endif 2177 #endif
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