Add 1.2GHz cpu clock support for T25

arch/arm/mach-tegra/tegra2_clocks.c

 /*
  * arch/arm/mach-tegra/tegra2_clocks.c
  *
  * Copyright (C) 2010 Google, Inc.
  *
  * Author:
  *      Colin Cross <ccross@google.com>
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ skipping 771 matching lines @@
 }
 
 static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
 {
         u32 val;
         u32 new_val;
         int divider_u71;
         unsigned long parent_rate = clk_get_rate(c->parent);
 
         pr_debug("%s: %s %lu\n", __func__, c->name, rate);
+

[Olof Johansson, 2011/01/12 01:05:28]

Unrelated change, please discard

[jimmzhang, 2011/01/12 01:22:56]

will be removed.

         if (c->flags & DIV_U71) {
                 divider_u71 = clk_div71_get_divider(parent_rate, rate);
                 if (divider_u71 >= 0) {
                         val = clk_readl(c->reg);
                         new_val = val >> c->reg_shift;
                         new_val &= 0xFFFF;
                         if (c->flags & DIV_U71_FIXED)
                                 new_val |= PLL_OUT_OVERRIDE;
                         new_val &= ~PLL_OUT_RATIO_MASK;
                         new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
@@ skipping 704 matching lines @@
                 .cf_min    = 1000000,
                 .cf_max    = 6000000,
                 .vco_min   = 480000000,
                 .vco_max   = 960000000,
                 .freq_table = tegra_pll_u_freq_table,
                 .lock_delay = 1000,
         },
 };
 
 static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
+        /* 1.2 GHz */
+        { 12000000, 1200000000,  600,  6, 1, 12},
+        { 13000000, 1200000000,  923, 10, 1, 12},
+        { 19200000, 1200000000,  750, 12, 1,  8},
+        { 26000000, 1200000000,  600, 13, 1, 12},
+
         /* 1 GHz */
         { 12000000, 1000000000, 1000, 12, 1, 12},
         { 13000000, 1000000000, 1000, 13, 1, 12},
         { 19200000, 1000000000, 625,  12, 1, 8},
         { 26000000, 1000000000, 1000, 26, 1, 12},
 
         /* 912 MHz */
         { 12000000, 912000000,  912,  12, 1, 12},
         { 13000000, 912000000,  912,  13, 1, 12},
         { 19200000, 912000000,  760,  16, 1, 8},
@@ skipping 31 matching lines @@
 
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct clk tegra_pll_x = {
         .name      = "pll_x",
         .flags     = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
         .ops       = &tegra_pllx_ops,
         .reg       = 0xe0,
         .parent    = &tegra_clk_m,
-        .max_rate  = 1000000000,
+        .max_rate  = 1200000000,

[Olof Johansson, 2011/01/12 01:05:28]

Is it safe to set max_rate here? Shouldn't you update it dynamically when you
detect T25 instead? (same for the other changes below).

[jimmzhang, 2011/01/12 01:22:56]

The max value is still limited by the cpu frequency table. In case of T20, the
max rate will only be set to 1.0GHz.

[Olof Johansson, 2011/01/12 18:53:07]

Ok, sounds good.

         .u.pll = {
                 .input_min = 2000000,
                 .input_max = 31000000,
                 .cf_min    = 1000000,
                 .cf_max    = 6000000,
                 .vco_min   = 20000000,
                 .vco_max   = 1200000000,
                 .freq_table = tegra_pll_x_freq_table,
                 .lock_delay = 300,
         },
@@ skipping 128 matching lines @@
         { .input = &tegra_clk_32k,      .value = 6},
         { .input = &tegra_pll_m_out1,   .value = 7},
         { 0, 0},
 };
 
 static struct clk tegra_clk_cclk = {
         .name   = "cclk",
         .inputs = mux_cclk,
         .reg    = 0x20,
         .ops    = &tegra_super_ops,
-        .max_rate = 1000000000,
+        .max_rate = 1200000000,
 };
 
 static struct clk tegra_clk_sclk = {
         .name   = "sclk",
         .inputs = mux_sclk,
         .reg    = 0x28,
         .ops    = &tegra_super_ops,
         .max_rate = 240000000,
         .u.shared_bus = {
                 .min_rate = 120000000,
         },
 };
 
 static struct clk tegra_clk_virtual_cpu = {
         .name      = "cpu",
         .parent    = &tegra_clk_cclk,
         .ops       = &tegra_cpu_ops,
-        .max_rate  = 1000000000,
+        .max_rate  = 1200000000,
         .u.cpu = {
                 .main      = &tegra_pll_x,
                 .backup    = &tegra_pll_p,
         },
 };
 
 static struct clk tegra_clk_cop = {
         .name      = "cop",
         .parent    = &tegra_clk_sclk,
         .ops       = &tegra_cop_ops,
@@ skipping 410 matching lines @@
 
         off = CLK_OUT_ENB;
         for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
                 clk_writel(*ctx++, off);
         wmb();
 
         clk_writel(*ctx++, MISC_CLK_ENB);
         clk_writel(*ctx++, CLK_MASK_ARM);
 }
 #endif