Generate some intrinsics using our IR.

runtime/vm/flow_graph_compiler_mips.cc

Index: runtime/vm/flow_graph_compiler_mips.cc
===================================================================
--- runtime/vm/flow_graph_compiler_mips.cc	(revision 39726)
+++ runtime/vm/flow_graph_compiler_mips.cc	(working copy)
@@ -54,6 +54,20 @@
 }
 
 
+void FlowGraphCompiler::EnterIntrinsicMode() {
+  ASSERT(!intrinsic_mode());
+  intrinsic_mode_ = true;
+  assembler()->set_allow_constant_pool(false);
+}
+
+
+void FlowGraphCompiler::ExitIntrinsicMode() {
+  ASSERT(intrinsic_mode());
+  intrinsic_mode_ = false;
+  assembler()->set_allow_constant_pool(true);
+}
+
+
 RawDeoptInfo* CompilerDeoptInfo::CreateDeoptInfo(FlowGraphCompiler* compiler,
                                                  DeoptInfoBuilder* builder,
                                                  const Array& deopt_table) {
@@ -1593,18 +1607,19 @@
     } else {
       ASSERT(destination.IsStackSlot());
       const intptr_t dest_offset = destination.ToStackSlotOffset();
-      __ StoreToOffset(source.reg(), FP, dest_offset);
+      __ StoreToOffset(source.reg(), destination.base_reg(), dest_offset);
     }
   } else if (source.IsStackSlot()) {
     if (destination.IsRegister()) {
       const intptr_t source_offset = source.ToStackSlotOffset();
-      __ LoadFromOffset(destination.reg(), FP, source_offset);
+      __ LoadFromOffset(destination.reg(), source.base_reg(), source_offset);
     } else {
       ASSERT(destination.IsStackSlot());
       const intptr_t source_offset = source.ToStackSlotOffset();
       const intptr_t dest_offset = destination.ToStackSlotOffset();
-      __ LoadFromOffset(TMP, FP, source_offset);
-      __ StoreToOffset(TMP, FP, dest_offset);
+      ScratchRegisterScope tmp(this, kNoRegister);
+      __ LoadFromOffset(tmp.reg(), source.base_reg(), source_offset);
+      __ StoreToOffset(tmp.reg(), destination.base_reg(), dest_offset);
     }
   } else if (source.IsFpuRegister()) {
     if (destination.IsFpuRegister()) {
@@ -1615,7 +1630,7 @@
       if (destination.IsDoubleStackSlot()) {
         const intptr_t dest_offset = destination.ToStackSlotOffset();
         DRegister src = source.fpu_reg();
-        __ StoreDToOffset(src, FP, dest_offset);
+        __ StoreDToOffset(src, destination.base_reg(), dest_offset);
       } else {
         ASSERT(destination.IsQuadStackSlot());
         UNIMPLEMENTED();
@@ -1623,15 +1638,15 @@
     }
   } else if (source.IsDoubleStackSlot()) {
     if (destination.IsFpuRegister()) {
-      const intptr_t dest_offset = source.ToStackSlotOffset();
+      const intptr_t source_offset = source.ToStackSlotOffset();
       DRegister dst = destination.fpu_reg();
-      __ LoadDFromOffset(dst, FP, dest_offset);
+      __ LoadDFromOffset(dst, source.base_reg(), source_offset);
     } else {
       ASSERT(destination.IsDoubleStackSlot());
       const intptr_t source_offset = source.ToStackSlotOffset();
       const intptr_t dest_offset = destination.ToStackSlotOffset();
-      __ LoadDFromOffset(DTMP, FP, source_offset);
-      __ StoreDToOffset(DTMP, FP, dest_offset);
+      __ LoadDFromOffset(DTMP, source.base_reg(), source_offset);
+      __ StoreDToOffset(DTMP, destination.base_reg(), dest_offset);
     }
   } else if (source.IsQuadStackSlot()) {
     UNIMPLEMENTED();
@@ -1648,12 +1663,13 @@
       const intptr_t dest_offset = destination.ToStackSlotOffset();
       __ LoadObject(TMP, constant);
       __ LoadDFromOffset(DTMP, TMP, Double::value_offset() - kHeapObjectTag);
-      __ StoreDToOffset(DTMP, FP, dest_offset);
+      __ StoreDToOffset(DTMP, destination.base_reg(), dest_offset);
     } else {
       ASSERT(destination.IsStackSlot());
       const intptr_t dest_offset = destination.ToStackSlotOffset();
-      __ LoadObject(TMP, constant);
-      __ StoreToOffset(TMP, FP, dest_offset);
+      ScratchRegisterScope tmp(this, kNoRegister);
+      __ LoadObject(tmp.reg(), constant);
+      __ StoreToOffset(tmp.reg(), destination.base_reg(), dest_offset);
     }
   }
 
@@ -1673,11 +1689,14 @@
     __ mov(source.reg(), destination.reg());
     __ mov(destination.reg(), TMP);
   } else if (source.IsRegister() && destination.IsStackSlot()) {
-    Exchange(source.reg(), destination.ToStackSlotOffset());
+    Exchange(source.reg(),
+             destination.base_reg(), destination.ToStackSlotOffset());
   } else if (source.IsStackSlot() && destination.IsRegister()) {
-    Exchange(destination.reg(), source.ToStackSlotOffset());
+    Exchange(destination.reg(),
+             source.base_reg(), source.ToStackSlotOffset());
   } else if (source.IsStackSlot() && destination.IsStackSlot()) {
-    Exchange(source.ToStackSlotOffset(), destination.ToStackSlotOffset());
+    Exchange(source.base_reg(), source.ToStackSlotOffset(),
+             destination.base_reg(), destination.ToStackSlotOffset());
   } else if (source.IsFpuRegister() && destination.IsFpuRegister()) {
     DRegister dst = destination.fpu_reg();
     DRegister src = source.fpu_reg();
@@ -1767,20 +1786,26 @@
 }
 
 
-void ParallelMoveResolver::Exchange(Register reg, intptr_t stack_offset) {
-  __ mov(TMP, reg);
-  __ LoadFromOffset(reg, FP, stack_offset);
-  __ StoreToOffset(TMP, FP, stack_offset);
+void ParallelMoveResolver::Exchange(Register reg,
+                                    Register base_reg,
+                                    intptr_t stack_offset) {
+  ScratchRegisterScope tmp(this, kNoRegister);
+  __ mov(tmp.reg(), reg);
+  __ LoadFromOffset(reg, base_reg, stack_offset);
+  __ StoreToOffset(tmp.reg(), base_reg, stack_offset);
 }
 
 
-void ParallelMoveResolver::Exchange(intptr_t stack_offset1,
+void ParallelMoveResolver::Exchange(Register base_reg1,
+                                    intptr_t stack_offset1,
+                                    Register base_reg2,
                                     intptr_t stack_offset2) {
-  ScratchRegisterScope ensure_scratch(this, TMP);
-  __ LoadFromOffset(ensure_scratch.reg(), FP, stack_offset1);
-  __ LoadFromOffset(TMP, FP, stack_offset2);
-  __ StoreToOffset(ensure_scratch.reg(), FP, stack_offset2);
-  __ StoreToOffset(TMP, FP, stack_offset1);
+  ScratchRegisterScope tmp1(this, kNoRegister);
+  ScratchRegisterScope tmp2(this, tmp1.reg());
+  __ LoadFromOffset(tmp1.reg(), base_reg1, stack_offset1);
+  __ LoadFromOffset(tmp2.reg(), base_reg2, stack_offset2);
+  __ StoreToOffset(tmp1.reg(), base_reg1, stack_offset2);
+  __ StoreToOffset(tmp2.reg(), base_reg2, stack_offset1);
 }