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Unified Diff: runtime/vm/flow_graph_compiler_arm.cc

Issue 513213002: Generate some intrinsics using our IR. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 6 years, 3 months ago
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« runtime/vm/flow_graph_compiler.cc ('K') | « runtime/vm/flow_graph_compiler.cc ('k') | runtime/vm/flow_graph_compiler_arm64.cc » ('j') | runtime/vm/intermediate_language_ia32.cc » ('J')
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Index: runtime/vm/flow_graph_compiler_arm.cc
===================================================================
--- runtime/vm/flow_graph_compiler_arm.cc (revision 39726)
+++ runtime/vm/flow_graph_compiler_arm.cc (working copy)
@@ -58,6 +58,20 @@
}
+void FlowGraphCompiler::EnterIntrinsicMode() {
+ ASSERT(!intrinsic_mode());
+ intrinsic_mode_ = true;
+ assembler()->set_allow_constant_pool(false);
srdjan 2014/09/02 18:48:21 Could you please remind me why we cannot have cons
Florian Schneider 2014/09/02 21:03:20 There is no normal function prologue and therefore
+}
+
+
+void FlowGraphCompiler::ExitIntrinsicMode() {
+ ASSERT(intrinsic_mode());
+ intrinsic_mode_ = false;
+ assembler()->set_allow_constant_pool(true);
+}
+
+
RawDeoptInfo* CompilerDeoptInfo::CreateDeoptInfo(FlowGraphCompiler* compiler,
DeoptInfoBuilder* builder,
const Array& deopt_table) {
@@ -1535,18 +1549,20 @@
} else {
ASSERT(destination.IsStackSlot());
const intptr_t dest_offset = destination.ToStackSlotOffset();
- __ StoreToOffset(kWord, source.reg(), FP, dest_offset);
+ __ StoreToOffset(
+ kWord, source.reg(), destination.base_reg(), dest_offset);
}
} else if (source.IsStackSlot()) {
if (destination.IsRegister()) {
const intptr_t source_offset = source.ToStackSlotOffset();
- __ LoadFromOffset(kWord, destination.reg(), FP, source_offset);
+ __ LoadFromOffset(
+ kWord, destination.reg(), source.base_reg(), source_offset);
} else {
ASSERT(destination.IsStackSlot());
const intptr_t source_offset = source.ToStackSlotOffset();
const intptr_t dest_offset = destination.ToStackSlotOffset();
- __ LoadFromOffset(kWord, TMP, FP, source_offset);
- __ StoreToOffset(kWord, TMP, FP, dest_offset);
+ __ LoadFromOffset(kWord, TMP, source.base_reg(), source_offset);
+ __ StoreToOffset(kWord, TMP, destination.base_reg(), dest_offset);
}
} else if (source.IsFpuRegister()) {
if (destination.IsFpuRegister()) {
@@ -1562,38 +1578,39 @@
if (destination.IsDoubleStackSlot()) {
const intptr_t dest_offset = destination.ToStackSlotOffset();
DRegister src = EvenDRegisterOf(source.fpu_reg());
- __ StoreDToOffset(src, FP, dest_offset);
+ __ StoreDToOffset(src, destination.base_reg(), dest_offset);
} else {
ASSERT(destination.IsQuadStackSlot());
const intptr_t dest_offset = destination.ToStackSlotOffset();
const DRegister dsrc0 = EvenDRegisterOf(source.fpu_reg());
- __ StoreMultipleDToOffset(dsrc0, 2, FP, dest_offset);
+ __ StoreMultipleDToOffset(
+ dsrc0, 2, destination.base_reg(), dest_offset);
}
}
} else if (source.IsDoubleStackSlot()) {
if (destination.IsFpuRegister()) {
- const intptr_t dest_offset = source.ToStackSlotOffset();
+ const intptr_t source_offset = source.ToStackSlotOffset();
const DRegister dst = EvenDRegisterOf(destination.fpu_reg());
- __ LoadDFromOffset(dst, FP, dest_offset);
+ __ LoadDFromOffset(dst, source.base_reg(), source_offset);
} else {
ASSERT(destination.IsDoubleStackSlot());
const intptr_t source_offset = source.ToStackSlotOffset();
const intptr_t dest_offset = destination.ToStackSlotOffset();
- __ LoadDFromOffset(DTMP, FP, source_offset);
- __ StoreDToOffset(DTMP, FP, dest_offset);
+ __ LoadDFromOffset(DTMP, source.base_reg(), source_offset);
+ __ StoreDToOffset(DTMP, destination.base_reg(), dest_offset);
}
} else if (source.IsQuadStackSlot()) {
if (destination.IsFpuRegister()) {
- const intptr_t dest_offset = source.ToStackSlotOffset();
+ const intptr_t source_offset = source.ToStackSlotOffset();
const DRegister dst0 = EvenDRegisterOf(destination.fpu_reg());
- __ LoadMultipleDFromOffset(dst0, 2, FP, dest_offset);
+ __ LoadMultipleDFromOffset(dst0, 2, source.base_reg(), source_offset);
} else {
ASSERT(destination.IsQuadStackSlot());
const intptr_t source_offset = source.ToStackSlotOffset();
const intptr_t dest_offset = destination.ToStackSlotOffset();
const DRegister dtmp0 = DTMP;
- __ LoadMultipleDFromOffset(dtmp0, 2, FP, source_offset);
- __ StoreMultipleDToOffset(dtmp0, 2, FP, dest_offset);
+ __ LoadMultipleDFromOffset(dtmp0, 2, source.base_reg(), source_offset);
+ __ StoreMultipleDToOffset(dtmp0, 2, destination.base_reg(), dest_offset);
}
} else {
ASSERT(source.IsConstant());
@@ -1625,7 +1642,7 @@
__ vldrd(DTMP, Address(TMP, 0));
}
const intptr_t dest_offset = destination.ToStackSlotOffset();
- __ StoreDToOffset(DTMP, FP, dest_offset);
+ __ StoreDToOffset(DTMP, destination.base_reg(), dest_offset);
} else {
ASSERT(destination.IsStackSlot());
const intptr_t dest_offset = destination.ToStackSlotOffset();
@@ -1634,7 +1651,7 @@
} else {
__ LoadObject(TMP, constant);
}
- __ StoreToOffset(kWord, TMP, FP, dest_offset);
+ __ StoreToOffset(kWord, TMP, destination.base_reg(), dest_offset);
}
}
@@ -1654,11 +1671,14 @@
__ mov(source.reg(), Operand(destination.reg()));
__ mov(destination.reg(), Operand(IP));
} else if (source.IsRegister() && destination.IsStackSlot()) {
- Exchange(source.reg(), destination.ToStackSlotOffset());
+ Exchange(source.reg(),
+ destination.base_reg(), destination.ToStackSlotOffset());
} else if (source.IsStackSlot() && destination.IsRegister()) {
- Exchange(destination.reg(), source.ToStackSlotOffset());
+ Exchange(destination.reg(),
+ source.base_reg(), source.ToStackSlotOffset());
} else if (source.IsStackSlot() && destination.IsStackSlot()) {
- Exchange(source.ToStackSlotOffset(), destination.ToStackSlotOffset());
+ Exchange(source.base_reg(), source.ToStackSlotOffset(),
+ destination.base_reg(), destination.ToStackSlotOffset());
} else if (source.IsFpuRegister() && destination.IsFpuRegister()) {
const DRegister dst = EvenDRegisterOf(destination.fpu_reg());
DRegister src = EvenDRegisterOf(source.fpu_reg());
@@ -1678,10 +1698,13 @@
const intptr_t slot_offset = source.IsFpuRegister()
? destination.ToStackSlotOffset()
: source.ToStackSlotOffset();
+ Register base_reg = source.IsFpuRegister()
+ ? destination.base_reg()
+ : source.base_reg();
if (double_width) {
- __ LoadDFromOffset(DTMP, FP, slot_offset);
- __ StoreDToOffset(reg, FP, slot_offset);
+ __ LoadDFromOffset(DTMP, base_reg, slot_offset);
+ __ StoreDToOffset(reg, base_reg, slot_offset);
__ vmovd(reg, DTMP);
} else {
UNIMPLEMENTED();
@@ -1692,10 +1715,10 @@
ScratchFpuRegisterScope ensure_scratch(this, QTMP);
DRegister scratch = EvenDRegisterOf(ensure_scratch.reg());
- __ LoadDFromOffset(DTMP, FP, source_offset);
- __ LoadDFromOffset(scratch, FP, dest_offset);
- __ StoreDToOffset(DTMP, FP, dest_offset);
- __ StoreDToOffset(scratch, FP, source_offset);
+ __ LoadDFromOffset(DTMP, source.base_reg(), source_offset);
+ __ LoadDFromOffset(scratch, destination.base_reg(), dest_offset);
+ __ StoreDToOffset(DTMP, destination.base_reg(), dest_offset);
+ __ StoreDToOffset(scratch, destination.base_reg(), source_offset);
} else if (source.IsQuadStackSlot() && destination.IsQuadStackSlot()) {
UNIMPLEMENTED();
} else {
@@ -1722,14 +1745,12 @@
void ParallelMoveResolver::MoveMemoryToMemory(const Address& dst,
const Address& src) {
- __ ldr(IP, src);
- __ str(IP, dst);
+ UNREACHABLE();
}
void ParallelMoveResolver::StoreObject(const Address& dst, const Object& obj) {
- __ LoadObject(IP, obj);
- __ str(IP, dst);
+ UNREACHABLE();
}
@@ -1747,20 +1768,26 @@
}
-void ParallelMoveResolver::Exchange(Register reg, intptr_t stack_offset) {
- __ mov(TMP, Operand(reg));
- __ LoadFromOffset(kWord, reg, FP, stack_offset);
- __ StoreToOffset(kWord, TMP, FP, stack_offset);
+void ParallelMoveResolver::Exchange(Register reg,
+ Register base_reg,
+ intptr_t stack_offset) {
+ ScratchRegisterScope tmp(this, kNoRegister);
+ __ mov(tmp.reg(), Operand(reg));
+ __ LoadFromOffset(kWord, reg, base_reg, stack_offset);
+ __ StoreToOffset(kWord, tmp.reg(), base_reg, stack_offset);
}
-void ParallelMoveResolver::Exchange(intptr_t stack_offset1,
+void ParallelMoveResolver::Exchange(Register base_reg1,
+ intptr_t stack_offset1,
+ Register base_reg2,
intptr_t stack_offset2) {
- ScratchRegisterScope ensure_scratch(this, IP);
- __ LoadFromOffset(kWord, ensure_scratch.reg(), FP, stack_offset1);
- __ LoadFromOffset(kWord, TMP, FP, stack_offset2);
- __ StoreToOffset(kWord, ensure_scratch.reg(), FP, stack_offset2);
- __ StoreToOffset(kWord, TMP, FP, stack_offset1);
+ ScratchRegisterScope tmp1(this, kNoRegister);
+ ScratchRegisterScope tmp2(this, tmp1.reg());
+ __ LoadFromOffset(kWord, tmp1.reg(), base_reg1, stack_offset1);
+ __ LoadFromOffset(kWord, tmp2.reg(), base_reg2, stack_offset2);
+ __ StoreToOffset(kWord, tmp1.reg(), base_reg2, stack_offset2);
+ __ StoreToOffset(kWord, tmp2.reg(), base_reg1, stack_offset1);
}
« runtime/vm/flow_graph_compiler.cc ('K') | « runtime/vm/flow_graph_compiler.cc ('k') | runtime/vm/flow_graph_compiler_arm64.cc » ('j') | runtime/vm/intermediate_language_ia32.cc » ('J')

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