[turbofan] Add backend support for load/store float32 values.

src/compiler/arm/instruction-selector-arm.cc

Index: src/compiler/arm/instruction-selector-arm.cc
diff --git a/src/compiler/arm/instruction-selector-arm.cc b/src/compiler/arm/instruction-selector-arm.cc
index 6ec86bd6413d9c3e3ff04b6d5877e97218f4a0f3..85969716015f4b3e4bfef64478ab53256823c41b 100644
--- a/src/compiler/arm/instruction-selector-arm.cc
+++ b/src/compiler/arm/instruction-selector-arm.cc
@@ -55,6 +55,8 @@ class ArmOperandGenerator V8_FINAL : public OperandGenerator {
       case kArmRsb:
         return ImmediateFitsAddrMode1Instruction(value);
 
+      case kArmVldr32:
+      case kArmVstr32:
       case kArmVldr64:
       case kArmVstr64:
         return value >= -1020 && value <= 1020 && (value % 4) == 0;
@@ -294,12 +296,15 @@ void InstructionSelector::VisitLoad(Node* node) {
   Node* base = node->InputAt(0);
   Node* index = node->InputAt(1);
 
-  InstructionOperand* result = rep == kRepFloat64
+  InstructionOperand* result = (rep == kRepFloat32 || rep == kRepFloat64)
                                    ? g.DefineAsDoubleRegister(node)
                                    : g.DefineAsRegister(node);
 
   ArchOpcode opcode;
   switch (rep) {
+    case kRepFloat32:
+      opcode = kArmVldr32;
+      break;
     case kRepFloat64:
       opcode = kArmVldr64;
       break;
@@ -349,11 +354,15 @@ void InstructionSelector::VisitStore(Node* node) {
     return;
   }
   DCHECK_EQ(kNoWriteBarrier, store_rep.write_barrier_kind);
-  InstructionOperand* val =
-      rep == kRepFloat64 ? g.UseDoubleRegister(value) : g.UseRegister(value);
+  InstructionOperand* val = (rep == kRepFloat32 || rep == kRepFloat64)
+                                ? g.UseDoubleRegister(value)
+                                : g.UseRegister(value);
 
   ArchOpcode opcode;
   switch (rep) {
+    case kRepFloat32:
+      opcode = kArmVstr32;
+      break;
     case kRepFloat64:
       opcode = kArmVstr64;
       break;