[turbofan] Add backend support for load/store float32 values.

src/compiler/arm/instruction-selector-arm.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/base/bits.h"
 #include "src/compiler/instruction-selector-impl.h"
 #include "src/compiler/node-matchers.h"
 
 namespace v8 {
 namespace internal {
@@ skipping 37 matching lines @@
         return ImmediateFitsAddrMode1Instruction(value) ||
                ImmediateFitsAddrMode1Instruction(-value);
 
       case kArmTst:
       case kArmTeq:
       case kArmOrr:
       case kArmEor:
       case kArmRsb:
         return ImmediateFitsAddrMode1Instruction(value);
 
+      case kArmVldr32:
+      case kArmVstr32:
       case kArmVldr64:
       case kArmVstr64:
         return value >= -1020 && value <= 1020 && (value % 4) == 0;
 
       case kArmLdrb:
       case kArmLdrsb:
       case kArmStrb:
       case kArmLdr:
       case kArmStr:
       case kArmStoreWriteBarrier:
@@ skipping 219 matching lines @@
 }
 
 
 void InstructionSelector::VisitLoad(Node* node) {
   MachineType rep = RepresentationOf(OpParameter<MachineType>(node));
   MachineType typ = TypeOf(OpParameter<MachineType>(node));
   ArmOperandGenerator g(this);
   Node* base = node->InputAt(0);
   Node* index = node->InputAt(1);
 
-  InstructionOperand* result = rep == kRepFloat64
+  InstructionOperand* result = (rep == kRepFloat32 || rep == kRepFloat64)
                                    ? g.DefineAsDoubleRegister(node)
                                    : g.DefineAsRegister(node);
 
   ArchOpcode opcode;
   switch (rep) {
+    case kRepFloat32:
+      opcode = kArmVldr32;
+      break;
     case kRepFloat64:
       opcode = kArmVldr64;
       break;
     case kRepBit:  // Fall through.
     case kRepWord8:
       opcode = typ == kTypeUint32 ? kArmLdrb : kArmLdrsb;
       break;
     case kRepWord16:
       opcode = typ == kTypeUint32 ? kArmLdrh : kArmLdrsh;
       break;
@@ skipping 29 matching lines @@
     // TODO(dcarney): refactor RecordWrite function to take temp registers
     //                and pass them here instead of using fixed regs
     // TODO(dcarney): handle immediate indices.
     InstructionOperand* temps[] = {g.TempRegister(r5), g.TempRegister(r6)};
     Emit(kArmStoreWriteBarrier, NULL, g.UseFixed(base, r4),
          g.UseFixed(index, r5), g.UseFixed(value, r6), ARRAY_SIZE(temps),
          temps);
     return;
   }
   DCHECK_EQ(kNoWriteBarrier, store_rep.write_barrier_kind);
-  InstructionOperand* val =
-      rep == kRepFloat64 ? g.UseDoubleRegister(value) : g.UseRegister(value);
+  InstructionOperand* val = (rep == kRepFloat32 || rep == kRepFloat64)
+                                ? g.UseDoubleRegister(value)
+                                : g.UseRegister(value);
 
   ArchOpcode opcode;
   switch (rep) {
+    case kRepFloat32:
+      opcode = kArmVstr32;
+      break;
     case kRepFloat64:
       opcode = kArmVstr64;
       break;
     case kRepBit:  // Fall through.
     case kRepWord8:
       opcode = kArmStrb;
       break;
     case kRepWord16:
       opcode = kArmStrh;
       break;
@@ skipping 588 matching lines @@
     DCHECK(cont->IsSet());
     Emit(cont->Encode(kArmVcmpF64), g.DefineAsRegister(cont->result()),
          g.UseDoubleRegister(m.left().node()),
          g.UseDoubleRegister(m.right().node()));
   }
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8