| Index: src/mips64/simulator-mips64.cc
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| diff --git a/src/mips64/simulator-mips64.cc b/src/mips64/simulator-mips64.cc
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| index c07558465fb71c545fba06dd77a54a138ee63867..cb6649a538a9d460da798d2d61932e7f86733c6d 100644
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| --- a/src/mips64/simulator-mips64.cc
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| +++ b/src/mips64/simulator-mips64.cc
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| @@ -12,6 +12,7 @@
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|  #if V8_TARGET_ARCH_MIPS64
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|  
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|  #include "src/assembler.h"
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| +#include "src/base/bits.h"
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|  #include "src/disasm.h"
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|  #include "src/globals.h"    // Need the BitCast.
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|  #include "src/mips64/constants-mips64.h"
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| @@ -2074,10 +2075,8 @@ void Simulator::ConfigureTypeRegister(Instruction* instr,
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|            } else {
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|              // MIPS spec: If no bits were set in GPR rs, the result written to
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|              // GPR rd is 32.
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| -            // GCC __builtin_clz: If input is 0, the result is undefined.
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|              DCHECK(instr->SaValue() == 1);
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| -            *alu_out =
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| -                rs_u == 0 ? 32 : CompilerIntrinsics::CountLeadingZeros(rs_u);
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| +            *alu_out = base::bits::CountLeadingZeros32(rs_u);
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|            }
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|            break;
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|          case MFLO:
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| @@ -2220,9 +2219,7 @@ void Simulator::ConfigureTypeRegister(Instruction* instr,
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|          case CLZ:
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|            // MIPS32 spec: If no bits were set in GPR rs, the result written to
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|            // GPR rd is 32.
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| -          // GCC __builtin_clz: If input is 0, the result is undefined.
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| -          *alu_out =
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| -              rs_u == 0 ? 32 : CompilerIntrinsics::CountLeadingZeros(rs_u);
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| +          *alu_out = base::bits::CountLeadingZeros32(rs_u);
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|            break;
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|          default:
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|            UNREACHABLE();
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| 
 |