Fix implementation of bit count functions.

src/mips64/simulator-mips64.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <limits.h>
 #include <stdarg.h>
 #include <stdlib.h>
 #include <cmath>
 
 #include "src/v8.h"
 
 #if V8_TARGET_ARCH_MIPS64
 
 #include "src/assembler.h"
+#include "src/base/bits.h"
 #include "src/disasm.h"
 #include "src/globals.h"    // Need the BitCast.
 #include "src/mips64/constants-mips64.h"
 #include "src/mips64/simulator-mips64.h"
 #include "src/ostreams.h"
 
 // Only build the simulator if not compiling for real MIPS hardware.
 #if defined(USE_SIMULATOR)
 
 namespace v8 {
@@ skipping 2042 matching lines @@
         case DSRAV:
           *alu_out = rt >> rs;
           break;
         case MFHI:  // MFHI == CLZ on R6.
           if (kArchVariant != kMips64r6) {
             DCHECK(instr->SaValue() == 0);
             *alu_out = get_register(HI);
           } else {
             // MIPS spec: If no bits were set in GPR rs, the result written to
             // GPR rd is 32.
-            // GCC __builtin_clz: If input is 0, the result is undefined.
             DCHECK(instr->SaValue() == 1);
-            *alu_out =
-                rs_u == 0 ? 32 : CompilerIntrinsics::CountLeadingZeros(rs_u);
+            *alu_out = base::bits::CountLeadingZeros32(rs_u);
           }
           break;
         case MFLO:
           *alu_out = get_register(LO);
           break;
         case MULT:  // MULT == D_MUL_MUH.
           // TODO(plind) - Unify MULT/DMULT with single set of 64-bit HI/Lo
           // regs.
           // TODO(plind) - make the 32-bit MULT ops conform to spec regarding
           //   checking of 32-bit input values, and un-define operations of HW.
@@ skipping 122 matching lines @@
       break;
     case SPECIAL2:
       switch (instr->FunctionFieldRaw()) {
         case MUL:
           // Only the lower 32 bits are kept.
           *alu_out = (int32_t)rs_u * (int32_t)rt_u;
           break;
         case CLZ:
           // MIPS32 spec: If no bits were set in GPR rs, the result written to
           // GPR rd is 32.
-          // GCC __builtin_clz: If input is 0, the result is undefined.
-          *alu_out =
-              rs_u == 0 ? 32 : CompilerIntrinsics::CountLeadingZeros(rs_u);
+          *alu_out = base::bits::CountLeadingZeros32(rs_u);
           break;
         default:
           UNREACHABLE();
       }
       break;
     case SPECIAL3:
       switch (instr->FunctionFieldRaw()) {
         case INS: {   // Mips32r2 instruction.
           // Interpret rd field as 5-bit msb of insert.
           uint16_t msb = rd_reg;
@@ skipping 1206 matching lines @@
 }
 
 
 #undef UNSUPPORTED
 
 } }  // namespace v8::internal
 
 #endif  // USE_SIMULATOR
 
 #endif  // V8_TARGET_ARCH_MIPS64