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Unified Diff: arch/arm/include/asm/arch-tegra2/tegra2.h

Issue 4841001: Tegra2: implement Warmboot code and lp0_vec (Closed) Base URL: http://git.chromium.org/git/u-boot-next.git@chromeos-v2010.09
Patch Set: Created 10 years, 1 month ago
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« arch/arm/include/asm/arch-tegra2/nvbl_assembly.h ('K') | « arch/arm/include/asm/arch-tegra2/nvboot_sdram_param.h ('k') | arch/arm/lib/board.c » ('j') | arch/arm/lib/board.c » ('J')
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Index: arch/arm/include/asm/arch-tegra2/tegra2.h
diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h b/arch/arm/include/asm/arch-tegra2/tegra2.h
index 049e99ca077d2f2d46c462b2d0d63e36ff9220c3..0e536dabbd4fb9be93171b02406aa7d85157e636 100644
--- a/arch/arm/include/asm/arch-tegra2/tegra2.h
+++ b/arch/arm/include/asm/arch-tegra2/tegra2.h
@@ -47,6 +47,8 @@
#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0 _MK_ADDR_CONST(0x310)
#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0 _MK_ADDR_CONST(0x330)
#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0 _MK_ADDR_CONST(0x314)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0 _MK_ADDR_CONST(0x320)
+
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0 _MK_ADDR_CONST(0x124)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0 _MK_ADDR_CONST(0x128)
@@ -61,6 +63,7 @@
#define CLK_RST_CONTROLLER_PLLC_BASE_0 _MK_ADDR_CONST(0x80)
#define CLK_RST_CONTROLLER_PLLC_MISC_0 _MK_ADDR_CONST(0x8c)
#define CLK_RST_CONTROLLER_PLLM_BASE_0 _MK_ADDR_CONST(0x90)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0 _MK_ADDR_CONST(0x94)
#define CLK_RST_CONTROLLER_PLLM_MISC_0 _MK_ADDR_CONST(0x9c)
#define CLK_RST_CONTROLLER_PLLU_BASE_0 _MK_ADDR_CONST(0xc0)
#define CLK_RST_CONTROLLER_PLLU_MISC_0 _MK_ADDR_CONST(0xcc)
@@ -315,6 +318,17 @@
#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_RANGE 7:0
#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0 _MK_ADDR_CONST(0x2c)
#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_DISABLE _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_RANGE 1:1
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_RANGE 4:0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_RANGE 17:8
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_RANGE 22:20
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_RANGE 11:8
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_RANGE 7:4
+
+
+/* ap20/aremc.h */
+#define EMC_FBIO_SPARE_0 _MK_ADDR_CONST(0x100)
+
/* ap20/arevp.h */
#define EVP_CPU_RESET_VECTOR_0 _MK_ADDR_CONST(0x100)
@@ -520,6 +534,35 @@
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_RANGE 29:29
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_NORMAL _MK_ENUM_CONST(0)
+#define APB_MISC_GP_HIDREV_0 _MK_ADDR_CONST(0x804)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_RANGE 7:4
+#define APB_MISC_GP_HIDREV_0_CHIPID_RANGE 15:8
+
+#define APB_MISC_GP_XM2CFGAPADCTRL_0 _MK_ADDR_CONST(0x8c4)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_RANGE 5:5
+#define APB_MISC_GP_XM2CFGDPADCTRL_0 _MK_ADDR_CONST(0x8cc)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_RANGE 3:3
+
+
+/* ap20/nvboot_pmc_scratch_map.h */
+#define APBDEV_PMC_SCRATCH2_0_CLK_RST_OSC_CTRL_XOBP_RANGE 28:28
+#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_BASE_PLLM_DIVM_RANGE 4:0
+#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_BASE_PLLM_DIVN_RANGE 14:5
+#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_BASE_PLLM_DIVP_RANGE 17:15
+#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_MISC_CPCON_RANGE 25:22
+#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_MISC_LFCON_RANGE 21:18
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_WB0_RANGE 31:24
+#define APBDEV_PMC_SCRATCH4_0_EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_WB0_RANGE 31:24
+#define APBDEV_PMC_SCRATCH2_0_APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_RANGE 26:26
+#define APBDEV_PMC_SCRATCH2_0_APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_RANGE 27:27
+#define APBDEV_PMC_SCRATCH2_0_MEMORY_TYPE_RANGE 31:29
+#define APBDEV_PMC_SCRATCH4_0_EMC_CLOCK_DIVIDER_RANGE 7:0
+#define APBDEV_PMC_SCRATCH4_0_PLLM_STABLE_TIME_RANGE 15:8
+#define APBDEV_PMC_SCRATCH4_0_PLLX_STABLE_TIME_RANGE 23:16
+#define APBDEV_PMC_SCRATCH24_0_EMC_AUTO_CAL_WAIT_RANGE 7:0
+#define APBDEV_PMC_SCRATCH24_0_EMC_PIN_PROGRAM_WAIT_RANGE 15:8
+#define APBDEV_PMC_SCRATCH24_0_WARMBOOT_WAIT_RANGE 23:16
+
/* ap20/aruart.h */
#define UART_LSR_0_THRE_SHIFT _MK_SHIFT_CONST(5)
#define UART_LSR_0_THRE_FIELD (_MK_MASK_CONST(0x1) << UART_LSR_0_THRE_SHIFT)
@@ -538,8 +581,15 @@
/* ap20/arapbpm.h */
#define APBDEV_PMC_SCRATCH1_0 _MK_ADDR_CONST(0x54)
+#define APBDEV_PMC_SCRATCH2_0 _MK_ADDR_CONST(0x58)
+#define APBDEV_PMC_SCRATCH3_0 _MK_ADDR_CONST(0x5c)
+#define APBDEV_PMC_SCRATCH4_0 _MK_ADDR_CONST(0x60)
#define APBDEV_PMC_SCRATCH20_0 _MK_ADDR_CONST(0xa0)
#define APBDEV_PMC_SCRATCH23_0 _MK_ADDR_CONST(0xac)
+#define APBDEV_PMC_SCRATCH24_0 _MK_ADDR_CONST(0xfc)
+#define APBDEV_PMC_SCRATCH39_0 _MK_ADDR_CONST(0x138)
+#define APBDEV_PMC_SCRATCH41_0 _MK_ADDR_CONST(0x140)
+#define APBDEV_PMC_SCRATCH42_0 _MK_ADDR_CONST(0x144)
#define APBDEV_PMC_CNTRL_0 _MK_ADDR_CONST(0x0)
#define APBDEV_PMC_CNTRL_0_MAIN_RST_RANGE 4:4
#define APBDEV_PMC_CNTRL_0_MAIN_RST_ENABLE _MK_ENUM_CONST(1)
@@ -576,17 +626,28 @@
/* ap20/arflow_ctlr.h */
#define FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_RANGE 7:0
-#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_STOP _MK_ENUM_CONST(2)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_STOP _MK_ENUM_CONST(2)
#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_RANGE 31:29
#define FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_RANGE 28:28
#define FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_RANGE 25:25
#define FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_RANGE 24:24
-
#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_RANGE 11:11
#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_RANGE 9:9
-#define FLOW_CTLR_HALT_COP_EVENTS_0 _MK_ADDR_CONST(0x4)
-#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FLOW_MODE_STOP _MK_ENUM_CONST(2)
+#define FLOW_CTLR_HALT_COP_EVENTS_0 _MK_ADDR_CONST(0x4)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_DEFAULT_MASK _MK_MASK_CONST(0xff)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_SHIFT _MK_SHIFT_CONST(0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_DEFAULT_MASK _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_SHIFT _MK_SHIFT_CONST(24)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_DEFAULT_MASK _MK_MASK_CONST(0x7)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_SHIFT _MK_SHIFT_CONST(29)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_DEFAULT_MASK _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_SHIFT _MK_SHIFT_CONST(28)
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0 _MK_ADDR_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0 _MK_ADDR_CONST(0x14)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FLOW_MODE_STOP _MK_ENUM_CONST(2)
#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_RANGE 31:29
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_SHIFT _MK_SHIFT_CONST(29)
/* arcsite.h */
#define CSITE_CPUDBG0_LAR_0 _MK_ADDR_CONST(0x10fb0)
@@ -901,4 +962,108 @@ typedef volatile struct timerus {
#define AP20_BOOT_INFO_BASE 0x40000000UL
#define AP20_PMC_BASE 0x7000e400UL
+#define APB_MISC_PP_CONFIG_CTL_0 _MK_ADDR_CONST(0x24)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_SHIFT _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_ENABLE _MK_ENUM_CONST(1)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_SHIFT _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_ENABLE _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_SHIFT _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_DEFAULT_MASK _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_SHIFT _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_DEFAULT_MASK _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_SHIFT _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_SHIFT _MK_SHIFT_CONST(8)
+
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET1_DEFAULT_MASK _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET1_SHIFT _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET1_DEFAULT_MASK _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET1_SHIFT _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET1_DEFAULT_MASK _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET1_SHIFT _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET0_DEFAULT_MASK _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET0_SHIFT _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET0_DEFAULT_MASK _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET0_SHIFT _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET0_DEFAULT_MASK _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET0_SHIFT _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_PLLP_OUT0 _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_SHIFT _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_PLLP_OUT0 _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_SHIFT _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_PLLP_OUT0 _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_SHIFT _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_PLLP_OUT0 _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_SHIFT _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_SHIFT _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU_BRIDGE_CLKDIV_DEFAULT _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU_BRIDGE_CLKDIV_SHIFT _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU0_CLK_STP_DEFAULT_MASK _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU0_CLK_STP_SHIFT _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU1_CLK_STP_DEFAULT_MASK _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU1_CLK_STP_SHIFT _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET0_DEFAULT_MASK _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET0_SHIFT _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET0_DEFAULT_MASK _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET0_SHIFT _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET0_DEFAULT_MASK _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET0_SHIFT _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_RESET_DISABLE _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_SHIFT _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_ENABLE _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_SHIFT _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_DEFAULT_MASK _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_SHIFT _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_PLLM_OUT1 _MK_ENUM_CONST(7)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_SHIFT _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_PLLM_OUT1 _MK_ENUM_CONST(7)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_SHIFT _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_PLLM_OUT1 _MK_ENUM_CONST(7)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_SHIFT _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_PLLM_OUT1 _MK_ENUM_CONST(7)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_SHIFT _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_IDLE _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_SHIFT _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_CSITE_RST_DEFAULT_MASK _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_CSITE_RST_SHIFT _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CPU_RST_DEFAULT_MASK _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CPU_RST_SHIFT _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CPU_DEFAULT_MASK _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CPU_SHIFT _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_CSITE_RST_DEFAULT_MASK _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_CSITE_RST_SHIFT _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVN_SHIFT _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVP_SHIFT _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_BYPASS_SHIFT _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_ENABLE_SHIFT _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_REF_DIS_SHIFT _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_DCCON_DEFAULT _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_DCCON_SHIFT _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LFCON_SHIFT _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_CPCON_SHIFT _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CPU_RST_DEFAULT_MASK _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CPU_RST_SHIFT _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_ENABLE _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_SHIFT _MK_SHIFT_CONST(2)
+
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_DEFAULT_MASK _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_SHIFT _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_DEFAULT_MASK _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_SHIFT _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_SHIFT _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVM_DEFAULT_MASK _MK_MASK_CONST(0x0000001F)
+#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVP_SHIFT _MK_SHIFT_CONST(15)
+#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVM_SHIFT _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVN_SHIFT _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVP_DEFAULT_MASK _MK_MASK_CONST(0x00000007)
+#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_MISC_LFCON_SHIFT _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_MISC_LFCON_DEFAULT_MASK _MK_MASK_CONST(0x0000000F)
+#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_MISC_CPCON_SHIFT _MK_SHIFT_CONST(22)
+#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVN_DEFAULT_MASK _MK_MASK_CONST(0x000003FF)
+#define APBDEV_PMC_SCRATCH_FOR_AVP_RESUME_PTR_0 APBDEV_PMC_SCRATCH39_0
+
+#define TIMERUS_USEC_CFG_0_USEC_DIVISOR_DEFAULT_MASK _MK_MASK_CONST(0xff)
+#define TIMERUS_USEC_CFG_0_USEC_DIVISOR_SHIFT _MK_SHIFT_CONST(0)
+
+#define PG_UP_TAG_0_PID_COP _MK_ENUM_CONST(-1431655766) // // COP aka "arm2" aka "arm7"
+
#endif
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