Start adding an integrated assembler.

src/IceInstX8632.def

Index: src/IceInstX8632.def
diff --git a/src/IceInstX8632.def b/src/IceInstX8632.def
index 932500cbddb07057e433bc10be6e8f6f319c91e2..dc7cd6b7f9b434b6ca86e4d1fb416f04967b13a4 100644
--- a/src/IceInstX8632.def
+++ b/src/IceInstX8632.def
@@ -50,21 +50,27 @@
   X(SegReg_GS, "gs")        \
 //#define X(val, name)
 
-#define ICEINSTX8632BR_TABLE   \
-  /* enum value, dump, emit */ \
-  X(Br_a,        "a",  "ja")   \
-  X(Br_ae,       "ae", "jae")  \
-  X(Br_b,        "b",  "jb")   \
-  X(Br_be,       "be", "jbe")  \
-  X(Br_e,        "e",  "je")   \
-  X(Br_g,        "g",  "jg")   \
-  X(Br_ge,       "ge", "jge")  \
-  X(Br_l,        "l",  "jl")   \
-  X(Br_le,       "le", "jle")  \
-  X(Br_ne,       "ne", "jne")  \
-  X(Br_np,       "np", "jnp")  \
-  X(Br_p,        "p",  "jp")   \
-//#define X(tag, dump, emit)
+// X86 condition codes. Note: the enum value follows instruction encoding
+// (the "Instruction Subcode" in B.1 of the Intel Manuals).
+#define ICEINSTX8632BR_TABLE                    \
+  /* enum value, dump, emit */                  \
+  X(Br_o,        "o",  "jo")                    \
+  X(Br_no,       "no", "jno")                   \
+  X(Br_b,        "b",  "jb")                    \
+  X(Br_ae,       "ae", "jae")                   \
+  X(Br_e,        "e",  "je")                    \
+  X(Br_ne,       "ne", "jne")                   \
+  X(Br_be,       "be", "jbe")                   \
+  X(Br_a,        "a",  "ja")                    \
+  X(Br_s,        "s",  "js")                    \
+  X(Br_ns,       "ns", "jns")                   \
+  X(Br_p,        "p",  "jp")                    \
+  X(Br_np,       "np", "jnp")                   \
+  X(Br_l,        "l",  "jl")                    \
+  X(Br_ge,       "ge", "jge")                   \
+  X(Br_le,       "le", "jle")                   \
+  X(Br_g,        "g",  "jg")                    \
+  //#define X(tag, dump, emit)
 
 #define ICEINSTX8632CMPPS_TABLE \
   /* enum value, emit */        \