Start adding an integrated assembler.

src/IceInstX8632.def

 //===- subzero/src/IceInstX8632.def - X-macros for x86-32 insts -*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines properties of lowered x86-32 instructions in the
@@ skipping 32 matching lines @@
 #define SEG_REGX8632_TABLE  \
   /* enum value, name */    \
   X(SegReg_CS, "cs")        \
   X(SegReg_DS, "ds")        \
   X(SegReg_ES, "es")        \
   X(SegReg_SS, "ss")        \
   X(SegReg_FS, "fs")        \
   X(SegReg_GS, "gs")        \
 //#define X(val, name)
 
-#define ICEINSTX8632BR_TABLE   \
-  /* enum value, dump, emit */ \
-  X(Br_a,        "a",  "ja")   \
-  X(Br_ae,       "ae", "jae")  \
-  X(Br_b,        "b",  "jb")   \
-  X(Br_be,       "be", "jbe")  \
-  X(Br_e,        "e",  "je")   \
-  X(Br_g,        "g",  "jg")   \
-  X(Br_ge,       "ge", "jge")  \
-  X(Br_l,        "l",  "jl")   \
-  X(Br_le,       "le", "jle")  \
-  X(Br_ne,       "ne", "jne")  \
-  X(Br_np,       "np", "jnp")  \
-  X(Br_p,        "p",  "jp")   \
-//#define X(tag, dump, emit)
+// X86 condition codes. Note: the enum value follows instruction encoding
+// (the "Instruction Subcode" in B.1 of the Intel Manuals).
+#define ICEINSTX8632BR_TABLE                    \
+  /* enum value, dump, emit */                  \
+  X(Br_o,        "o",  "jo")                    \
+  X(Br_no,       "no", "jno")                   \
+  X(Br_b,        "b",  "jb")                    \
+  X(Br_ae,       "ae", "jae")                   \
+  X(Br_e,        "e",  "je")                    \
+  X(Br_ne,       "ne", "jne")                   \
+  X(Br_be,       "be", "jbe")                   \
+  X(Br_a,        "a",  "ja")                    \
+  X(Br_s,        "s",  "js")                    \
+  X(Br_ns,       "ns", "jns")                   \
+  X(Br_p,        "p",  "jp")                    \
+  X(Br_np,       "np", "jnp")                   \
+  X(Br_l,        "l",  "jl")                    \
+  X(Br_ge,       "ge", "jge")                   \
+  X(Br_le,       "le", "jle")                   \
+  X(Br_g,        "g",  "jg")                    \
+  //#define X(tag, dump, emit)
 
 #define ICEINSTX8632CMPPS_TABLE \
   /* enum value, emit */        \
   X(Cmpps_eq,    "eq")          \
   X(Cmpps_lt,    "lt")          \
   X(Cmpps_le,    "le")          \
   X(Cmpps_unord, "unord")       \
   X(Cmpps_neq,   "neq")         \
   X(Cmpps_nlt,   "nlt")         \
   X(Cmpps_nle,   "nle")         \
@@ skipping 13 matching lines @@
   X(IceType_v4i1,  IceType_i32 , "?" , ""  , "d",  "xmmword ptr") \
   X(IceType_v8i1,  IceType_i16 , "?" , ""  , "w",  "xmmword ptr") \
   X(IceType_v16i1, IceType_i8  , "?" , ""  , "b",  "xmmword ptr") \
   X(IceType_v16i8, IceType_i8  , "?" , ""  , "b",  "xmmword ptr") \
   X(IceType_v8i16, IceType_i16 , "?" , ""  , "w",  "xmmword ptr") \
   X(IceType_v4i32, IceType_i32 , "dq", ""  , "d",  "xmmword ptr") \
   X(IceType_v4f32, IceType_f32 , "ps", ""  , "" ,  "xmmword ptr") \
 //#define X(tag, elementty, cvt, sdss, width)
 
 #endif // SUBZERO_SRC_ICEINSTX8632_DEF