src/mips/assembler-mips.cc - Issue 430503007: Rename ASSERT* to DCHECK*.

Unified Diff: src/mips/assembler-mips.cc

Issue 430503007: Rename ASSERT* to DCHECK*. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge

Patch Set: REBASE and fixes Created 6 years, 4 months ago

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Index: src/mips/assembler-mips.cc

diff --git a/src/mips/assembler-mips.cc b/src/mips/assembler-mips.cc

index c63714032c50904a5c1f2e6f746bb523b29e6ac9..e959b41adfee2eb2adc1e50ed1ce5cb7367a9594 100644

--- a/src/mips/assembler-mips.cc

+++ b/src/mips/assembler-mips.cc

@@ -66,7 +66,7 @@ static unsigned CpuFeaturesImpliedByCompiler() {

const char* DoubleRegister::AllocationIndexToString(int index) {

- ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters);

+ DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);

const char* const names[] = {

"f0",

"f2",

@@ -111,7 +111,7 @@ void CpuFeatures::PrintFeatures() { }

int ToNumber(Register reg) {

- ASSERT(reg.is_valid());

+ DCHECK(reg.is_valid());

const int kNumbers[] = {

0, // zero_reg

1, // at

@@ -151,7 +151,7 @@ int ToNumber(Register reg) {

- ASSERT(num >= 0 && num < kNumRegisters);

+ DCHECK(num >= 0 && num < kNumRegisters);

const Register kRegisters[] = {

zero_reg,

at,

@@ -221,7 +221,7 @@ Operand::Operand(Handle<Object> handle) {

// Verify all Objects referred by code are NOT in new space.

Object* obj = *handle;

if (obj->IsHeapObject()) {

- ASSERT(!HeapObject::cast(obj)->GetHeap()->InNewSpace(obj));

+ DCHECK(!HeapObject::cast(obj)->GetHeap()->InNewSpace(obj));

imm32_ = reinterpret_cast<intptr_t>(handle.location());

rmode_ = RelocInfo::EMBEDDED_OBJECT;

} else {

@@ -306,7 +306,7 @@ Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size)

void Assembler::GetCode(CodeDesc* desc) {

- ASSERT(pc_ <= reloc_info_writer.pos()); // No overlap.

+ DCHECK(pc_ <= reloc_info_writer.pos()); // No overlap.

// Set up code descriptor.

desc->buffer = buffer_;

desc->buffer_size = buffer_size_;

@@ -317,7 +317,7 @@ void Assembler::GetCode(CodeDesc* desc) {

void Assembler::Align(int m) {

- ASSERT(m >= 4 && IsPowerOf2(m));

+ DCHECK(m >= 4 && IsPowerOf2(m));

while ((pc_offset() & (m - 1)) != 0) {

nop();

}

@@ -554,7 +554,7 @@ bool Assembler::IsOri(Instr instr) {

bool Assembler::IsNop(Instr instr, unsigned int type) {

// See Assembler::nop(type).

- ASSERT(type < 32);

+ DCHECK(type < 32);

uint32_t opcode = GetOpcodeField(instr);

uint32_t function = GetFunctionField(instr);

uint32_t rt = GetRt(instr);

@@ -577,7 +577,7 @@ bool Assembler::IsNop(Instr instr, unsigned int type) {

int32_t Assembler::GetBranchOffset(Instr instr) {

- ASSERT(IsBranch(instr));

+ DCHECK(IsBranch(instr));

return (static_cast<int16_t>(instr & kImm16Mask)) << 2;

}

@@ -588,13 +588,13 @@ bool Assembler::IsLw(Instr instr) {

int16_t Assembler::GetLwOffset(Instr instr) {

- ASSERT(IsLw(instr));

+ DCHECK(IsLw(instr));

return ((instr & kImm16Mask));

}

Instr Assembler::SetLwOffset(Instr instr, int16_t offset) {

- ASSERT(IsLw(instr));

+ DCHECK(IsLw(instr));

// We actually create a new lw instruction based on the original one.

Instr temp_instr = LW | (instr & kRsFieldMask) | (instr & kRtFieldMask)

@@ -610,7 +610,7 @@ bool Assembler::IsSw(Instr instr) {

Instr Assembler::SetSwOffset(Instr instr, int16_t offset) {

- ASSERT(IsSw(instr));

+ DCHECK(IsSw(instr));

return ((instr & ~kImm16Mask) | (offset & kImm16Mask));

}

@@ -621,7 +621,7 @@ bool Assembler::IsAddImmediate(Instr instr) {

Instr Assembler::SetAddImmediateOffset(Instr instr, int16_t offset) {

- ASSERT(IsAddImmediate(instr));

+ DCHECK(IsAddImmediate(instr));

return ((instr & ~kImm16Mask) | (offset & kImm16Mask));

}

@@ -643,7 +643,7 @@ int Assembler::target_at(int32_t pos) {

}

// Check we have a branch or jump instruction.

- ASSERT(IsBranch(instr) || IsJ(instr) || IsLui(instr));

+ DCHECK(IsBranch(instr) || IsJ(instr) || IsLui(instr));

// Do NOT change this to <<2. We rely on arithmetic shifts here, assuming

// the compiler uses arithmectic shifts for signed integers.

if (IsBranch(instr)) {

@@ -658,7 +658,7 @@ int Assembler::target_at(int32_t pos) {

} else if (IsLui(instr)) {

Instr instr_lui = instr_at(pos + 0 * Assembler::kInstrSize);

Instr instr_ori = instr_at(pos + 1 * Assembler::kInstrSize);

- ASSERT(IsOri(instr_ori));

+ DCHECK(IsOri(instr_ori));

int32_t imm = (instr_lui & static_cast<int32_t>(kImm16Mask)) << kLuiShift;

imm |= (instr_ori & static_cast<int32_t>(kImm16Mask));

@@ -668,7 +668,7 @@ int Assembler::target_at(int32_t pos) {

} else {

uint32_t instr_address = reinterpret_cast<int32_t>(buffer_ + pos);

int32_t delta = instr_address - imm;

- ASSERT(pos > delta);

+ DCHECK(pos > delta);

return pos - delta;

}

} else {

@@ -680,7 +680,7 @@ int Assembler::target_at(int32_t pos) {

uint32_t instr_address = reinterpret_cast<int32_t>(buffer_ + pos);

instr_address &= kImm28Mask;

int32_t delta = instr_address - imm28;

- ASSERT(pos > delta);

+ DCHECK(pos > delta);

return pos - delta;

}

@@ -690,29 +690,29 @@ int Assembler::target_at(int32_t pos) {

void Assembler::target_at_put(int32_t pos, int32_t target_pos) {

Instr instr = instr_at(pos);

if ((instr & ~kImm16Mask) == 0) {

- ASSERT(target_pos == kEndOfChain || target_pos >= 0);

+ DCHECK(target_pos == kEndOfChain || target_pos >= 0);

// Emitted label constant, not part of a branch.

// Make label relative to Code* of generated Code object.

instr_at_put(pos, target_pos + (Code::kHeaderSize - kHeapObjectTag));

return;

}

- ASSERT(IsBranch(instr) || IsJ(instr) || IsLui(instr));

+ DCHECK(IsBranch(instr) || IsJ(instr) || IsLui(instr));

if (IsBranch(instr)) {

int32_t imm18 = target_pos - (pos + kBranchPCOffset);

- ASSERT((imm18 & 3) == 0);

+ DCHECK((imm18 & 3) == 0);

instr &= ~kImm16Mask;

int32_t imm16 = imm18 >> 2;

- ASSERT(is_int16(imm16));

+ DCHECK(is_int16(imm16));

instr_at_put(pos, instr | (imm16 & kImm16Mask));

} else if (IsLui(instr)) {

Instr instr_lui = instr_at(pos + 0 * Assembler::kInstrSize);

Instr instr_ori = instr_at(pos + 1 * Assembler::kInstrSize);

- ASSERT(IsOri(instr_ori));

+ DCHECK(IsOri(instr_ori));

uint32_t imm = reinterpret_cast<uint32_t>(buffer_) + target_pos;

- ASSERT((imm & 3) == 0);

+ DCHECK((imm & 3) == 0);

instr_lui &= ~kImm16Mask;

instr_ori &= ~kImm16Mask;

@@ -724,11 +724,11 @@ void Assembler::target_at_put(int32_t pos, int32_t target_pos) {

} else {

uint32_t imm28 = reinterpret_cast<uint32_t>(buffer_) + target_pos;

imm28 &= kImm28Mask;

- ASSERT((imm28 & 3) == 0);

+ DCHECK((imm28 & 3) == 0);

instr &= ~kImm26Mask;

uint32_t imm26 = imm28 >> 2;

- ASSERT(is_uint26(imm26));

+ DCHECK(is_uint26(imm26));

instr_at_put(pos, instr | (imm26 & kImm26Mask));

}

@@ -760,7 +760,7 @@ void Assembler::print(Label* L) {

void Assembler::bind_to(Label* L, int pos) {

- ASSERT(0 <= pos && pos <= pc_offset()); // Must have valid binding position.

+ DCHECK(0 <= pos && pos <= pc_offset()); // Must have valid binding position.

int32_t trampoline_pos = kInvalidSlotPos;

if (L->is_linked() && !trampoline_emitted_) {

unbound_labels_count_--;

@@ -778,14 +778,14 @@ void Assembler::bind_to(Label* L, int pos) {

trampoline_pos = get_trampoline_entry(fixup_pos);

CHECK(trampoline_pos != kInvalidSlotPos);

}

- ASSERT((trampoline_pos - fixup_pos) <= kMaxBranchOffset);

+ DCHECK((trampoline_pos - fixup_pos) <= kMaxBranchOffset);

target_at_put(fixup_pos, trampoline_pos);

fixup_pos = trampoline_pos;

dist = pos - fixup_pos;

}

target_at_put(fixup_pos, pos);

} else {

- ASSERT(IsJ(instr) || IsLui(instr) || IsEmittedConstant(instr));

+ DCHECK(IsJ(instr) || IsLui(instr) || IsEmittedConstant(instr));

target_at_put(fixup_pos, pos);

}

@@ -799,18 +799,18 @@ void Assembler::bind_to(Label* L, int pos) {

void Assembler::bind(Label* L) {

- ASSERT(!L->is_bound()); // Label can only be bound once.

+ DCHECK(!L->is_bound()); // Label can only be bound once.

bind_to(L, pc_offset());

}

void Assembler::next(Label* L) {

- ASSERT(L->is_linked());

+ DCHECK(L->is_linked());

int link = target_at(L->pos());

if (link == kEndOfChain) {

L->Unuse();

} else {

- ASSERT(link >= 0);

+ DCHECK(link >= 0);

L->link_to(link);

}

@@ -838,7 +838,7 @@ void Assembler::GenInstrRegister(Opcode opcode,

uint16_t sa,

SecondaryField func) {

- ASSERT(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa));

+ DCHECK(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa));

Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift)

| (rd.code() << kRdShift) | (sa << kSaShift) | func;

emit(instr);

@@ -851,7 +851,7 @@ void Assembler::GenInstrRegister(Opcode opcode,

uint16_t msb,

uint16_t lsb,

SecondaryField func) {

- ASSERT(rs.is_valid() && rt.is_valid() && is_uint5(msb) && is_uint5(lsb));

+ DCHECK(rs.is_valid() && rt.is_valid() && is_uint5(msb) && is_uint5(lsb));

Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift)

| (msb << kRdShift) | (lsb << kSaShift) | func;

emit(instr);

@@ -864,7 +864,7 @@ void Assembler::GenInstrRegister(Opcode opcode,

FPURegister fs,

FPURegister fd,

SecondaryField func) {

- ASSERT(fd.is_valid() && fs.is_valid() && ft.is_valid());

+ DCHECK(fd.is_valid() && fs.is_valid() && ft.is_valid());

Instr instr = opcode | fmt | (ft.code() << kFtShift) | (fs.code() << kFsShift)

| (fd.code() << kFdShift) | func;

emit(instr);

@@ -877,7 +877,7 @@ void Assembler::GenInstrRegister(Opcode opcode,

FPURegister fs,

FPURegister fd,

SecondaryField func) {

- ASSERT(fd.is_valid() && fr.is_valid() && fs.is_valid() && ft.is_valid());

+ DCHECK(fd.is_valid() && fr.is_valid() && fs.is_valid() && ft.is_valid());

Instr instr = opcode | (fr.code() << kFrShift) | (ft.code() << kFtShift)

| (fs.code() << kFsShift) | (fd.code() << kFdShift) | func;

emit(instr);

@@ -890,7 +890,7 @@ void Assembler::GenInstrRegister(Opcode opcode,

FPURegister fs,

FPURegister fd,

SecondaryField func) {

- ASSERT(fd.is_valid() && fs.is_valid() && rt.is_valid());

+ DCHECK(fd.is_valid() && fs.is_valid() && rt.is_valid());

Instr instr = opcode | fmt | (rt.code() << kRtShift)

| (fs.code() << kFsShift) | (fd.code() << kFdShift) | func;

emit(instr);

@@ -902,7 +902,7 @@ void Assembler::GenInstrRegister(Opcode opcode,

FPUControlRegister fs,

SecondaryField func) {

- ASSERT(fs.is_valid() && rt.is_valid());

+ DCHECK(fs.is_valid() && rt.is_valid());

Instr instr =

opcode | fmt | (rt.code() << kRtShift) | (fs.code() << kFsShift) | func;

emit(instr);

@@ -915,7 +915,7 @@ void Assembler::GenInstrImmediate(Opcode opcode,

int32_t j) {

- ASSERT(rs.is_valid() && rt.is_valid() && (is_int16(j) || is_uint16(j)));

+ DCHECK(rs.is_valid() && rt.is_valid() && (is_int16(j) || is_uint16(j)));

Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift)

| (j & kImm16Mask);

emit(instr);

@@ -926,7 +926,7 @@ void Assembler::GenInstrImmediate(Opcode opcode,

SecondaryField SF,

int32_t j) {

- ASSERT(rs.is_valid() && (is_int16(j) || is_uint16(j)));

+ DCHECK(rs.is_valid() && (is_int16(j) || is_uint16(j)));

Instr instr = opcode | (rs.code() << kRsShift) | SF | (j & kImm16Mask);

emit(instr);

}

@@ -936,7 +936,7 @@ void Assembler::GenInstrImmediate(Opcode opcode,

FPURegister ft,

int32_t j) {

- ASSERT(rs.is_valid() && ft.is_valid() && (is_int16(j) || is_uint16(j)));

+ DCHECK(rs.is_valid() && ft.is_valid() && (is_int16(j) || is_uint16(j)));

Instr instr = opcode | (rs.code() << kRsShift) | (ft.code() << kFtShift)

| (j & kImm16Mask);

emit(instr);

@@ -946,7 +946,7 @@ void Assembler::GenInstrImmediate(Opcode opcode,

void Assembler::GenInstrJump(Opcode opcode,

uint32_t address) {

BlockTrampolinePoolScope block_trampoline_pool(this);

- ASSERT(is_uint26(address));

+ DCHECK(is_uint26(address));

Instr instr = opcode | address;

emit(instr);

BlockTrampolinePoolFor(1); // For associated delay slot.

@@ -986,7 +986,7 @@ uint32_t Assembler::jump_address(Label* L) {

}

uint32_t imm = reinterpret_cast<uint32_t>(buffer_) + target_pos;

- ASSERT((imm & 3) == 0);

+ DCHECK((imm & 3) == 0);

return imm;

}

@@ -1012,8 +1012,8 @@ int32_t Assembler::branch_offset(Label* L, bool jump_elimination_allowed) {

}

int32_t offset = target_pos - (pc_offset() + kBranchPCOffset);

- ASSERT((offset & 3) == 0);

- ASSERT(is_int16(offset >> 2));

+ DCHECK((offset & 3) == 0);

+ DCHECK(is_int16(offset >> 2));

return offset;

}

@@ -1028,9 +1028,9 @@ void Assembler::label_at_put(Label* L, int at_offset) {

if (L->is_linked()) {

target_pos = L->pos(); // L's link.

int32_t imm18 = target_pos - at_offset;

- ASSERT((imm18 & 3) == 0);

+ DCHECK((imm18 & 3) == 0);

int32_t imm16 = imm18 >> 2;

- ASSERT(is_int16(imm16));

+ DCHECK(is_int16(imm16));

instr_at_put(at_offset, (imm16 & kImm16Mask));

} else {

target_pos = kEndOfChain;

@@ -1122,7 +1122,7 @@ void Assembler::j(int32_t target) {

uint32_t ipc = reinterpret_cast<uint32_t>(pc_ + 1 * kInstrSize);

bool in_range = (ipc ^ static_cast<uint32_t>(target) >>

(kImm26Bits + kImmFieldShift)) == 0;

- ASSERT(in_range && ((target & 3) == 0));

+ DCHECK(in_range && ((target & 3) == 0));

#endif

GenInstrJump(J, target >> 2);

}

@@ -1144,7 +1144,7 @@ void Assembler::jal(int32_t target) {

uint32_t ipc = reinterpret_cast<uint32_t>(pc_ + 1 * kInstrSize);

bool in_range = (ipc ^ static_cast<uint32_t>(target) >>

(kImm26Bits + kImmFieldShift)) == 0;

- ASSERT(in_range && ((target & 3) == 0));

+ DCHECK(in_range && ((target & 3) == 0));

#endif

positions_recorder()->WriteRecordedPositions();

GenInstrJump(JAL, target >> 2);

@@ -1237,7 +1237,7 @@ void Assembler::and_(Register rd, Register rs, Register rt) {

void Assembler::andi(Register rt, Register rs, int32_t j) {

- ASSERT(is_uint16(j));

+ DCHECK(is_uint16(j));

GenInstrImmediate(ANDI, rs, rt, j);

}

@@ -1248,7 +1248,7 @@ void Assembler::or_(Register rd, Register rs, Register rt) {

void Assembler::ori(Register rt, Register rs, int32_t j) {

- ASSERT(is_uint16(j));

+ DCHECK(is_uint16(j));

GenInstrImmediate(ORI, rs, rt, j);

}

@@ -1259,7 +1259,7 @@ void Assembler::xor_(Register rd, Register rs, Register rt) {

void Assembler::xori(Register rt, Register rs, int32_t j) {

- ASSERT(is_uint16(j));

+ DCHECK(is_uint16(j));

GenInstrImmediate(XORI, rs, rt, j);

}

@@ -1278,7 +1278,7 @@ void Assembler::sll(Register rd,

// generated using the sll instruction. They must be generated using

// nop(int/NopMarkerTypes) or MarkCode(int/NopMarkerTypes) pseudo

// instructions.

- ASSERT(coming_from_nop || !(rd.is(zero_reg) && rt.is(zero_reg)));

+ DCHECK(coming_from_nop || !(rd.is(zero_reg) && rt.is(zero_reg)));

GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SLL);

}

@@ -1310,8 +1310,8 @@ void Assembler::srav(Register rd, Register rt, Register rs) {

void Assembler::rotr(Register rd, Register rt, uint16_t sa) {

// Should be called via MacroAssembler::Ror.

- ASSERT(rd.is_valid() && rt.is_valid() && is_uint5(sa));

- ASSERT(kArchVariant == kMips32r2);

+ DCHECK(rd.is_valid() && rt.is_valid() && is_uint5(sa));

+ DCHECK(kArchVariant == kMips32r2);

Instr instr = SPECIAL | (1 << kRsShift) | (rt.code() << kRtShift)

| (rd.code() << kRdShift) | (sa << kSaShift) | SRL;

emit(instr);

@@ -1320,8 +1320,8 @@ void Assembler::rotr(Register rd, Register rt, uint16_t sa) {

void Assembler::rotrv(Register rd, Register rt, Register rs) {

// Should be called via MacroAssembler::Ror.

- ASSERT(rd.is_valid() && rt.is_valid() && rs.is_valid() );

- ASSERT(kArchVariant == kMips32r2);

+ DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid() );

+ DCHECK(kArchVariant == kMips32r2);

Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift)

| (rd.code() << kRdShift) | (1 << kSaShift) | SRLV;

emit(instr);

@@ -1332,7 +1332,7 @@ void Assembler::rotrv(Register rd, Register rt, Register rs) {

// Helper for base-reg + offset, when offset is larger than int16.

void Assembler::LoadRegPlusOffsetToAt(const MemOperand& src) {

- ASSERT(!src.rm().is(at));

+ DCHECK(!src.rm().is(at));

lui(at, (src.offset_ >> kLuiShift) & kImm16Mask);

ori(at, at, src.offset_ & kImm16Mask); // Load 32-bit offset.

addu(at, at, src.rm()); // Add base register.

@@ -1440,7 +1440,7 @@ void Assembler::swr(Register rd, const MemOperand& rs) {

void Assembler::lui(Register rd, int32_t j) {

- ASSERT(is_uint16(j));

+ DCHECK(is_uint16(j));

GenInstrImmediate(LUI, zero_reg, rd, j);

}

@@ -1449,11 +1449,11 @@ void Assembler::lui(Register rd, int32_t j) {

// Break / Trap instructions.

void Assembler::break_(uint32_t code, bool break_as_stop) {

- ASSERT((code & ~0xfffff) == 0);

+ DCHECK((code & ~0xfffff) == 0);

// We need to invalidate breaks that could be stops as well because the

// simulator expects a char pointer after the stop instruction.

// See constants-mips.h for explanation.

- ASSERT((break_as_stop &&

+ DCHECK((break_as_stop &&

code <= kMaxStopCode &&

code > kMaxWatchpointCode) ||

(!break_as_stop &&

@@ -1465,8 +1465,8 @@ void Assembler::break_(uint32_t code, bool break_as_stop) {

void Assembler::stop(const char* msg, uint32_t code) {

- ASSERT(code > kMaxWatchpointCode);

- ASSERT(code <= kMaxStopCode);

+ DCHECK(code > kMaxWatchpointCode);

+ DCHECK(code <= kMaxStopCode);

#if V8_HOST_ARCH_MIPS

break_(0x54321);

#else // V8_HOST_ARCH_MIPS

@@ -1480,7 +1480,7 @@ void Assembler::stop(const char* msg, uint32_t code) {

void Assembler::tge(Register rs, Register rt, uint16_t code) {

- ASSERT(is_uint10(code));

+ DCHECK(is_uint10(code));

Instr instr = SPECIAL | TGE | rs.code() << kRsShift

| rt.code() << kRtShift | code << 6;

emit(instr);

@@ -1488,7 +1488,7 @@ void Assembler::tge(Register rs, Register rt, uint16_t code) {

void Assembler::tgeu(Register rs, Register rt, uint16_t code) {

- ASSERT(is_uint10(code));

+ DCHECK(is_uint10(code));

Instr instr = SPECIAL | TGEU | rs.code() << kRsShift

| rt.code() << kRtShift | code << 6;

emit(instr);

@@ -1496,7 +1496,7 @@ void Assembler::tgeu(Register rs, Register rt, uint16_t code) {

void Assembler::tlt(Register rs, Register rt, uint16_t code) {

- ASSERT(is_uint10(code));

+ DCHECK(is_uint10(code));

Instr instr =

SPECIAL | TLT | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;

emit(instr);

@@ -1504,7 +1504,7 @@ void Assembler::tlt(Register rs, Register rt, uint16_t code) {

void Assembler::tltu(Register rs, Register rt, uint16_t code) {

- ASSERT(is_uint10(code));

+ DCHECK(is_uint10(code));

Instr instr =

SPECIAL | TLTU | rs.code() << kRsShift

| rt.code() << kRtShift | code << 6;

@@ -1513,7 +1513,7 @@ void Assembler::tltu(Register rs, Register rt, uint16_t code) {

void Assembler::teq(Register rs, Register rt, uint16_t code) {

- ASSERT(is_uint10(code));

+ DCHECK(is_uint10(code));

Instr instr =

SPECIAL | TEQ | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;

emit(instr);

@@ -1521,7 +1521,7 @@ void Assembler::teq(Register rs, Register rt, uint16_t code) {

void Assembler::tne(Register rs, Register rt, uint16_t code) {

- ASSERT(is_uint10(code));

+ DCHECK(is_uint10(code));

Instr instr =

SPECIAL | TNE | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;

emit(instr);

@@ -1596,7 +1596,7 @@ void Assembler::clz(Register rd, Register rs) {

void Assembler::ins_(Register rt, Register rs, uint16_t pos, uint16_t size) {

// Should be called via MacroAssembler::Ins.

// Ins instr has 'rt' field as dest, and two uint5: msb, lsb.

- ASSERT(kArchVariant == kMips32r2);

+ DCHECK(kArchVariant == kMips32r2);

GenInstrRegister(SPECIAL3, rs, rt, pos + size - 1, pos, INS);

}

@@ -1604,14 +1604,14 @@ void Assembler::ins_(Register rt, Register rs, uint16_t pos, uint16_t size) {

void Assembler::ext_(Register rt, Register rs, uint16_t pos, uint16_t size) {

// Should be called via MacroAssembler::Ext.

// Ext instr has 'rt' field as dest, and two uint5: msb, lsb.

- ASSERT(kArchVariant == kMips32r2);

+ DCHECK(kArchVariant == kMips32r2);

GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos, EXT);

}

void Assembler::pref(int32_t hint, const MemOperand& rs) {

- ASSERT(kArchVariant != kLoongson);

- ASSERT(is_uint5(hint) && is_uint16(rs.offset_));

+ DCHECK(kArchVariant != kLoongson);

+ DCHECK(is_uint5(hint) && is_uint16(rs.offset_));

Instr instr = PREF | (rs.rm().code() << kRsShift) | (hint << kRtShift)

| (rs.offset_);

emit(instr);

@@ -1785,25 +1785,25 @@ void Assembler::ceil_w_d(FPURegister fd, FPURegister fs) {

void Assembler::cvt_l_s(FPURegister fd, FPURegister fs) {

- ASSERT(kArchVariant == kMips32r2);

+ DCHECK(kArchVariant == kMips32r2);

GenInstrRegister(COP1, S, f0, fs, fd, CVT_L_S);

}

void Assembler::cvt_l_d(FPURegister fd, FPURegister fs) {

- ASSERT(kArchVariant == kMips32r2);

+ DCHECK(kArchVariant == kMips32r2);

GenInstrRegister(COP1, D, f0, fs, fd, CVT_L_D);

}

void Assembler::trunc_l_s(FPURegister fd, FPURegister fs) {

- ASSERT(kArchVariant == kMips32r2);

+ DCHECK(kArchVariant == kMips32r2);

GenInstrRegister(COP1, S, f0, fs, fd, TRUNC_L_S);

}

void Assembler::trunc_l_d(FPURegister fd, FPURegister fs) {

- ASSERT(kArchVariant == kMips32r2);

+ DCHECK(kArchVariant == kMips32r2);

GenInstrRegister(COP1, D, f0, fs, fd, TRUNC_L_D);

}

@@ -1844,7 +1844,7 @@ void Assembler::cvt_s_w(FPURegister fd, FPURegister fs) {

void Assembler::cvt_s_l(FPURegister fd, FPURegister fs) {

- ASSERT(kArchVariant == kMips32r2);

+ DCHECK(kArchVariant == kMips32r2);

GenInstrRegister(COP1, L, f0, fs, fd, CVT_S_L);

}

@@ -1860,7 +1860,7 @@ void Assembler::cvt_d_w(FPURegister fd, FPURegister fs) {

void Assembler::cvt_d_l(FPURegister fd, FPURegister fs) {

- ASSERT(kArchVariant == kMips32r2);

+ DCHECK(kArchVariant == kMips32r2);

GenInstrRegister(COP1, L, f0, fs, fd, CVT_D_L);

}

@@ -1873,8 +1873,8 @@ void Assembler::cvt_d_s(FPURegister fd, FPURegister fs) {

// Conditions.

void Assembler::c(FPUCondition cond, SecondaryField fmt,

FPURegister fs, FPURegister ft, uint16_t cc) {

- ASSERT(is_uint3(cc));

- ASSERT((fmt & ~(31 << kRsShift)) == 0);

+ DCHECK(is_uint3(cc));

+ DCHECK((fmt & ~(31 << kRsShift)) == 0);

Instr instr = COP1 | fmt | ft.code() << 16 | fs.code() << kFsShift

| cc << 8 | 3 << 4 | cond;

emit(instr);

@@ -1883,7 +1883,7 @@ void Assembler::c(FPUCondition cond, SecondaryField fmt,

void Assembler::fcmp(FPURegister src1, const double src2,

FPUCondition cond) {

- ASSERT(src2 == 0.0);

+ DCHECK(src2 == 0.0);

mtc1(zero_reg, f14);

cvt_d_w(f14, f14);

c(cond, D, src1, f14, 0);

@@ -1891,14 +1891,14 @@ void Assembler::fcmp(FPURegister src1, const double src2,

void Assembler::bc1f(int16_t offset, uint16_t cc) {

- ASSERT(is_uint3(cc));

+ DCHECK(is_uint3(cc));

Instr instr = COP1 | BC1 | cc << 18 | 0 << 16 | (offset & kImm16Mask);

emit(instr);

}

void Assembler::bc1t(int16_t offset, uint16_t cc) {

- ASSERT(is_uint3(cc));

+ DCHECK(is_uint3(cc));

Instr instr = COP1 | BC1 | cc << 18 | 1 << 16 | (offset & kImm16Mask);

emit(instr);

}

@@ -1929,18 +1929,18 @@ void Assembler::RecordComment(const char* msg) {

int Assembler::RelocateInternalReference(byte* pc, intptr_t pc_delta) {

Instr instr = instr_at(pc);

- ASSERT(IsJ(instr) || IsLui(instr));

+ DCHECK(IsJ(instr) || IsLui(instr));

if (IsLui(instr)) {

Instr instr_lui = instr_at(pc + 0 * Assembler::kInstrSize);

Instr instr_ori = instr_at(pc + 1 * Assembler::kInstrSize);

- ASSERT(IsOri(instr_ori));

+ DCHECK(IsOri(instr_ori));

int32_t imm = (instr_lui & static_cast<int32_t>(kImm16Mask)) << kLuiShift;

imm |= (instr_ori & static_cast<int32_t>(kImm16Mask));

if (imm == kEndOfJumpChain) {

return 0; // Number of instructions patched.

}

imm += pc_delta;

- ASSERT((imm & 3) == 0);

+ DCHECK((imm & 3) == 0);

instr_lui &= ~kImm16Mask;

instr_ori &= ~kImm16Mask;

@@ -1957,11 +1957,11 @@ int Assembler::RelocateInternalReference(byte* pc, intptr_t pc_delta) {

}

imm28 += pc_delta;

imm28 &= kImm28Mask;

- ASSERT((imm28 & 3) == 0);

+ DCHECK((imm28 & 3) == 0);

instr &= ~kImm26Mask;

uint32_t imm26 = imm28 >> 2;

- ASSERT(is_uint26(imm26));

+ DCHECK(is_uint26(imm26));

instr_at_put(pc, instr | (imm26 & kImm26Mask));

return 1; // Number of instructions patched.

@@ -2013,7 +2013,7 @@ void Assembler::GrowBuffer() {

}

- ASSERT(!overflow());

+ DCHECK(!overflow());

}

@@ -2044,7 +2044,7 @@ void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {

RelocInfo rinfo(pc_, rmode, data, NULL);

if (rmode >= RelocInfo::JS_RETURN && rmode <= RelocInfo::DEBUG_BREAK_SLOT) {

// Adjust code for new modes.

- ASSERT(RelocInfo::IsDebugBreakSlot(rmode)

+ DCHECK(RelocInfo::IsDebugBreakSlot(rmode)

|| RelocInfo::IsJSReturn(rmode)

|| RelocInfo::IsComment(rmode)

|| RelocInfo::IsPosition(rmode));

@@ -2056,7 +2056,7 @@ void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {

!serializer_enabled() && !emit_debug_code()) {

return;

}

- ASSERT(buffer_space() >= kMaxRelocSize); // Too late to grow buffer here.

+ DCHECK(buffer_space() >= kMaxRelocSize); // Too late to grow buffer here.

if (rmode == RelocInfo::CODE_TARGET_WITH_ID) {

RelocInfo reloc_info_with_ast_id(pc_,

rmode,

@@ -2094,8 +2094,8 @@ void Assembler::CheckTrampolinePool() {

return;

}

- ASSERT(!trampoline_emitted_);

- ASSERT(unbound_labels_count_ >= 0);

+ DCHECK(!trampoline_emitted_);

+ DCHECK(unbound_labels_count_ >= 0);

if (unbound_labels_count_ > 0) {

// First we emit jump (2 instructions), then we emit trampoline pool.

{ BlockTrampolinePoolScope block_trampoline_pool(this);

@@ -2282,16 +2282,16 @@ void Assembler::JumpLabelToJumpRegister(Address pc) {

bool patched = false;

if (IsJal(instr3)) {

- ASSERT(GetOpcodeField(instr1) == LUI);

- ASSERT(GetOpcodeField(instr2) == ORI);

+ DCHECK(GetOpcodeField(instr1) == LUI);

+ DCHECK(GetOpcodeField(instr2) == ORI);

uint32_t rs_field = GetRt(instr2) << kRsShift;

uint32_t rd_field = ra.code() << kRdShift; // Return-address (ra) reg.

*(p+2) = SPECIAL | rs_field | rd_field | JALR;

patched = true;

} else if (IsJ(instr3)) {

- ASSERT(GetOpcodeField(instr1) == LUI);

- ASSERT(GetOpcodeField(instr2) == ORI);

+ DCHECK(GetOpcodeField(instr1) == LUI);

+ DCHECK(GetOpcodeField(instr2) == ORI);

uint32_t rs_field = GetRt(instr2) << kRsShift;

*(p+2) = SPECIAL | rs_field | JR;

@@ -2306,14 +2306,14 @@ void Assembler::JumpLabelToJumpRegister(Address pc) {

Handle<ConstantPoolArray> Assembler::NewConstantPool(Isolate* isolate) {

// No out-of-line constant pool support.

- ASSERT(!FLAG_enable_ool_constant_pool);

+ DCHECK(!FLAG_enable_ool_constant_pool);

return isolate->factory()->empty_constant_pool_array();

}

void Assembler::PopulateConstantPool(ConstantPoolArray* constant_pool) {

// No out-of-line constant pool support.

- ASSERT(!FLAG_enable_ool_constant_pool);

+ DCHECK(!FLAG_enable_ool_constant_pool);

return;

}

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