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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
6 // met: | 6 // met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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59 // compilation. | 59 // compilation. |
60 #if defined(__mips__) && defined(__mips_hard_float) && __mips_hard_float != 0 | 60 #if defined(__mips__) && defined(__mips_hard_float) && __mips_hard_float != 0 |
61 answer |= 1u << FPU; | 61 answer |= 1u << FPU; |
62 #endif | 62 #endif |
63 | 63 |
64 return answer; | 64 return answer; |
65 } | 65 } |
66 | 66 |
67 | 67 |
68 const char* DoubleRegister::AllocationIndexToString(int index) { | 68 const char* DoubleRegister::AllocationIndexToString(int index) { |
69 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters); | 69 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters); |
70 const char* const names[] = { | 70 const char* const names[] = { |
71 "f0", | 71 "f0", |
72 "f2", | 72 "f2", |
73 "f4", | 73 "f4", |
74 "f6", | 74 "f6", |
75 "f8", | 75 "f8", |
76 "f10", | 76 "f10", |
77 "f12", | 77 "f12", |
78 "f14", | 78 "f14", |
79 "f16", | 79 "f16", |
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104 if (cpu.has_fpu()) supported_ |= 1u << FPU; | 104 if (cpu.has_fpu()) supported_ |= 1u << FPU; |
105 #endif | 105 #endif |
106 } | 106 } |
107 | 107 |
108 | 108 |
109 void CpuFeatures::PrintTarget() { } | 109 void CpuFeatures::PrintTarget() { } |
110 void CpuFeatures::PrintFeatures() { } | 110 void CpuFeatures::PrintFeatures() { } |
111 | 111 |
112 | 112 |
113 int ToNumber(Register reg) { | 113 int ToNumber(Register reg) { |
114 ASSERT(reg.is_valid()); | 114 DCHECK(reg.is_valid()); |
115 const int kNumbers[] = { | 115 const int kNumbers[] = { |
116 0, // zero_reg | 116 0, // zero_reg |
117 1, // at | 117 1, // at |
118 2, // v0 | 118 2, // v0 |
119 3, // v1 | 119 3, // v1 |
120 4, // a0 | 120 4, // a0 |
121 5, // a1 | 121 5, // a1 |
122 6, // a2 | 122 6, // a2 |
123 7, // a3 | 123 7, // a3 |
124 8, // t0 | 124 8, // t0 |
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144 28, // gp | 144 28, // gp |
145 29, // sp | 145 29, // sp |
146 30, // fp | 146 30, // fp |
147 31, // ra | 147 31, // ra |
148 }; | 148 }; |
149 return kNumbers[reg.code()]; | 149 return kNumbers[reg.code()]; |
150 } | 150 } |
151 | 151 |
152 | 152 |
153 Register ToRegister(int num) { | 153 Register ToRegister(int num) { |
154 ASSERT(num >= 0 && num < kNumRegisters); | 154 DCHECK(num >= 0 && num < kNumRegisters); |
155 const Register kRegisters[] = { | 155 const Register kRegisters[] = { |
156 zero_reg, | 156 zero_reg, |
157 at, | 157 at, |
158 v0, v1, | 158 v0, v1, |
159 a0, a1, a2, a3, | 159 a0, a1, a2, a3, |
160 t0, t1, t2, t3, t4, t5, t6, t7, | 160 t0, t1, t2, t3, t4, t5, t6, t7, |
161 s0, s1, s2, s3, s4, s5, s6, s7, | 161 s0, s1, s2, s3, s4, s5, s6, s7, |
162 t8, t9, | 162 t8, t9, |
163 k0, k1, | 163 k0, k1, |
164 gp, | 164 gp, |
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214 // ----------------------------------------------------------------------------- | 214 // ----------------------------------------------------------------------------- |
215 // Implementation of Operand and MemOperand. | 215 // Implementation of Operand and MemOperand. |
216 // See assembler-mips-inl.h for inlined constructors. | 216 // See assembler-mips-inl.h for inlined constructors. |
217 | 217 |
218 Operand::Operand(Handle<Object> handle) { | 218 Operand::Operand(Handle<Object> handle) { |
219 AllowDeferredHandleDereference using_raw_address; | 219 AllowDeferredHandleDereference using_raw_address; |
220 rm_ = no_reg; | 220 rm_ = no_reg; |
221 // Verify all Objects referred by code are NOT in new space. | 221 // Verify all Objects referred by code are NOT in new space. |
222 Object* obj = *handle; | 222 Object* obj = *handle; |
223 if (obj->IsHeapObject()) { | 223 if (obj->IsHeapObject()) { |
224 ASSERT(!HeapObject::cast(obj)->GetHeap()->InNewSpace(obj)); | 224 DCHECK(!HeapObject::cast(obj)->GetHeap()->InNewSpace(obj)); |
225 imm32_ = reinterpret_cast<intptr_t>(handle.location()); | 225 imm32_ = reinterpret_cast<intptr_t>(handle.location()); |
226 rmode_ = RelocInfo::EMBEDDED_OBJECT; | 226 rmode_ = RelocInfo::EMBEDDED_OBJECT; |
227 } else { | 227 } else { |
228 // No relocation needed. | 228 // No relocation needed. |
229 imm32_ = reinterpret_cast<intptr_t>(obj); | 229 imm32_ = reinterpret_cast<intptr_t>(obj); |
230 rmode_ = RelocInfo::NONE32; | 230 rmode_ = RelocInfo::NONE32; |
231 } | 231 } |
232 } | 232 } |
233 | 233 |
234 | 234 |
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299 | 299 |
300 trampoline_emitted_ = FLAG_force_long_branches; | 300 trampoline_emitted_ = FLAG_force_long_branches; |
301 unbound_labels_count_ = 0; | 301 unbound_labels_count_ = 0; |
302 block_buffer_growth_ = false; | 302 block_buffer_growth_ = false; |
303 | 303 |
304 ClearRecordedAstId(); | 304 ClearRecordedAstId(); |
305 } | 305 } |
306 | 306 |
307 | 307 |
308 void Assembler::GetCode(CodeDesc* desc) { | 308 void Assembler::GetCode(CodeDesc* desc) { |
309 ASSERT(pc_ <= reloc_info_writer.pos()); // No overlap. | 309 DCHECK(pc_ <= reloc_info_writer.pos()); // No overlap. |
310 // Set up code descriptor. | 310 // Set up code descriptor. |
311 desc->buffer = buffer_; | 311 desc->buffer = buffer_; |
312 desc->buffer_size = buffer_size_; | 312 desc->buffer_size = buffer_size_; |
313 desc->instr_size = pc_offset(); | 313 desc->instr_size = pc_offset(); |
314 desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos(); | 314 desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos(); |
315 desc->origin = this; | 315 desc->origin = this; |
316 } | 316 } |
317 | 317 |
318 | 318 |
319 void Assembler::Align(int m) { | 319 void Assembler::Align(int m) { |
320 ASSERT(m >= 4 && IsPowerOf2(m)); | 320 DCHECK(m >= 4 && IsPowerOf2(m)); |
321 while ((pc_offset() & (m - 1)) != 0) { | 321 while ((pc_offset() & (m - 1)) != 0) { |
322 nop(); | 322 nop(); |
323 } | 323 } |
324 } | 324 } |
325 | 325 |
326 | 326 |
327 void Assembler::CodeTargetAlign() { | 327 void Assembler::CodeTargetAlign() { |
328 // No advantage to aligning branch/call targets to more than | 328 // No advantage to aligning branch/call targets to more than |
329 // single instruction, that I am aware of. | 329 // single instruction, that I am aware of. |
330 Align(4); | 330 Align(4); |
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547 | 547 |
548 bool Assembler::IsOri(Instr instr) { | 548 bool Assembler::IsOri(Instr instr) { |
549 uint32_t opcode = GetOpcodeField(instr); | 549 uint32_t opcode = GetOpcodeField(instr); |
550 // Checks if the instruction is a load upper immediate. | 550 // Checks if the instruction is a load upper immediate. |
551 return opcode == ORI; | 551 return opcode == ORI; |
552 } | 552 } |
553 | 553 |
554 | 554 |
555 bool Assembler::IsNop(Instr instr, unsigned int type) { | 555 bool Assembler::IsNop(Instr instr, unsigned int type) { |
556 // See Assembler::nop(type). | 556 // See Assembler::nop(type). |
557 ASSERT(type < 32); | 557 DCHECK(type < 32); |
558 uint32_t opcode = GetOpcodeField(instr); | 558 uint32_t opcode = GetOpcodeField(instr); |
559 uint32_t function = GetFunctionField(instr); | 559 uint32_t function = GetFunctionField(instr); |
560 uint32_t rt = GetRt(instr); | 560 uint32_t rt = GetRt(instr); |
561 uint32_t rd = GetRd(instr); | 561 uint32_t rd = GetRd(instr); |
562 uint32_t sa = GetSa(instr); | 562 uint32_t sa = GetSa(instr); |
563 | 563 |
564 // Traditional mips nop == sll(zero_reg, zero_reg, 0) | 564 // Traditional mips nop == sll(zero_reg, zero_reg, 0) |
565 // When marking non-zero type, use sll(zero_reg, at, type) | 565 // When marking non-zero type, use sll(zero_reg, at, type) |
566 // to avoid use of mips ssnop and ehb special encodings | 566 // to avoid use of mips ssnop and ehb special encodings |
567 // of the sll instruction. | 567 // of the sll instruction. |
568 | 568 |
569 Register nop_rt_reg = (type == 0) ? zero_reg : at; | 569 Register nop_rt_reg = (type == 0) ? zero_reg : at; |
570 bool ret = (opcode == SPECIAL && function == SLL && | 570 bool ret = (opcode == SPECIAL && function == SLL && |
571 rd == static_cast<uint32_t>(ToNumber(zero_reg)) && | 571 rd == static_cast<uint32_t>(ToNumber(zero_reg)) && |
572 rt == static_cast<uint32_t>(ToNumber(nop_rt_reg)) && | 572 rt == static_cast<uint32_t>(ToNumber(nop_rt_reg)) && |
573 sa == type); | 573 sa == type); |
574 | 574 |
575 return ret; | 575 return ret; |
576 } | 576 } |
577 | 577 |
578 | 578 |
579 int32_t Assembler::GetBranchOffset(Instr instr) { | 579 int32_t Assembler::GetBranchOffset(Instr instr) { |
580 ASSERT(IsBranch(instr)); | 580 DCHECK(IsBranch(instr)); |
581 return (static_cast<int16_t>(instr & kImm16Mask)) << 2; | 581 return (static_cast<int16_t>(instr & kImm16Mask)) << 2; |
582 } | 582 } |
583 | 583 |
584 | 584 |
585 bool Assembler::IsLw(Instr instr) { | 585 bool Assembler::IsLw(Instr instr) { |
586 return ((instr & kOpcodeMask) == LW); | 586 return ((instr & kOpcodeMask) == LW); |
587 } | 587 } |
588 | 588 |
589 | 589 |
590 int16_t Assembler::GetLwOffset(Instr instr) { | 590 int16_t Assembler::GetLwOffset(Instr instr) { |
591 ASSERT(IsLw(instr)); | 591 DCHECK(IsLw(instr)); |
592 return ((instr & kImm16Mask)); | 592 return ((instr & kImm16Mask)); |
593 } | 593 } |
594 | 594 |
595 | 595 |
596 Instr Assembler::SetLwOffset(Instr instr, int16_t offset) { | 596 Instr Assembler::SetLwOffset(Instr instr, int16_t offset) { |
597 ASSERT(IsLw(instr)); | 597 DCHECK(IsLw(instr)); |
598 | 598 |
599 // We actually create a new lw instruction based on the original one. | 599 // We actually create a new lw instruction based on the original one. |
600 Instr temp_instr = LW | (instr & kRsFieldMask) | (instr & kRtFieldMask) | 600 Instr temp_instr = LW | (instr & kRsFieldMask) | (instr & kRtFieldMask) |
601 | (offset & kImm16Mask); | 601 | (offset & kImm16Mask); |
602 | 602 |
603 return temp_instr; | 603 return temp_instr; |
604 } | 604 } |
605 | 605 |
606 | 606 |
607 bool Assembler::IsSw(Instr instr) { | 607 bool Assembler::IsSw(Instr instr) { |
608 return ((instr & kOpcodeMask) == SW); | 608 return ((instr & kOpcodeMask) == SW); |
609 } | 609 } |
610 | 610 |
611 | 611 |
612 Instr Assembler::SetSwOffset(Instr instr, int16_t offset) { | 612 Instr Assembler::SetSwOffset(Instr instr, int16_t offset) { |
613 ASSERT(IsSw(instr)); | 613 DCHECK(IsSw(instr)); |
614 return ((instr & ~kImm16Mask) | (offset & kImm16Mask)); | 614 return ((instr & ~kImm16Mask) | (offset & kImm16Mask)); |
615 } | 615 } |
616 | 616 |
617 | 617 |
618 bool Assembler::IsAddImmediate(Instr instr) { | 618 bool Assembler::IsAddImmediate(Instr instr) { |
619 return ((instr & kOpcodeMask) == ADDIU); | 619 return ((instr & kOpcodeMask) == ADDIU); |
620 } | 620 } |
621 | 621 |
622 | 622 |
623 Instr Assembler::SetAddImmediateOffset(Instr instr, int16_t offset) { | 623 Instr Assembler::SetAddImmediateOffset(Instr instr, int16_t offset) { |
624 ASSERT(IsAddImmediate(instr)); | 624 DCHECK(IsAddImmediate(instr)); |
625 return ((instr & ~kImm16Mask) | (offset & kImm16Mask)); | 625 return ((instr & ~kImm16Mask) | (offset & kImm16Mask)); |
626 } | 626 } |
627 | 627 |
628 | 628 |
629 bool Assembler::IsAndImmediate(Instr instr) { | 629 bool Assembler::IsAndImmediate(Instr instr) { |
630 return GetOpcodeField(instr) == ANDI; | 630 return GetOpcodeField(instr) == ANDI; |
631 } | 631 } |
632 | 632 |
633 | 633 |
634 int Assembler::target_at(int32_t pos) { | 634 int Assembler::target_at(int32_t pos) { |
635 Instr instr = instr_at(pos); | 635 Instr instr = instr_at(pos); |
636 if ((instr & ~kImm16Mask) == 0) { | 636 if ((instr & ~kImm16Mask) == 0) { |
637 // Emitted label constant, not part of a branch. | 637 // Emitted label constant, not part of a branch. |
638 if (instr == 0) { | 638 if (instr == 0) { |
639 return kEndOfChain; | 639 return kEndOfChain; |
640 } else { | 640 } else { |
641 int32_t imm18 =((instr & static_cast<int32_t>(kImm16Mask)) << 16) >> 14; | 641 int32_t imm18 =((instr & static_cast<int32_t>(kImm16Mask)) << 16) >> 14; |
642 return (imm18 + pos); | 642 return (imm18 + pos); |
643 } | 643 } |
644 } | 644 } |
645 // Check we have a branch or jump instruction. | 645 // Check we have a branch or jump instruction. |
646 ASSERT(IsBranch(instr) || IsJ(instr) || IsLui(instr)); | 646 DCHECK(IsBranch(instr) || IsJ(instr) || IsLui(instr)); |
647 // Do NOT change this to <<2. We rely on arithmetic shifts here, assuming | 647 // Do NOT change this to <<2. We rely on arithmetic shifts here, assuming |
648 // the compiler uses arithmectic shifts for signed integers. | 648 // the compiler uses arithmectic shifts for signed integers. |
649 if (IsBranch(instr)) { | 649 if (IsBranch(instr)) { |
650 int32_t imm18 = ((instr & static_cast<int32_t>(kImm16Mask)) << 16) >> 14; | 650 int32_t imm18 = ((instr & static_cast<int32_t>(kImm16Mask)) << 16) >> 14; |
651 | 651 |
652 if (imm18 == kEndOfChain) { | 652 if (imm18 == kEndOfChain) { |
653 // EndOfChain sentinel is returned directly, not relative to pc or pos. | 653 // EndOfChain sentinel is returned directly, not relative to pc or pos. |
654 return kEndOfChain; | 654 return kEndOfChain; |
655 } else { | 655 } else { |
656 return pos + kBranchPCOffset + imm18; | 656 return pos + kBranchPCOffset + imm18; |
657 } | 657 } |
658 } else if (IsLui(instr)) { | 658 } else if (IsLui(instr)) { |
659 Instr instr_lui = instr_at(pos + 0 * Assembler::kInstrSize); | 659 Instr instr_lui = instr_at(pos + 0 * Assembler::kInstrSize); |
660 Instr instr_ori = instr_at(pos + 1 * Assembler::kInstrSize); | 660 Instr instr_ori = instr_at(pos + 1 * Assembler::kInstrSize); |
661 ASSERT(IsOri(instr_ori)); | 661 DCHECK(IsOri(instr_ori)); |
662 int32_t imm = (instr_lui & static_cast<int32_t>(kImm16Mask)) << kLuiShift; | 662 int32_t imm = (instr_lui & static_cast<int32_t>(kImm16Mask)) << kLuiShift; |
663 imm |= (instr_ori & static_cast<int32_t>(kImm16Mask)); | 663 imm |= (instr_ori & static_cast<int32_t>(kImm16Mask)); |
664 | 664 |
665 if (imm == kEndOfJumpChain) { | 665 if (imm == kEndOfJumpChain) { |
666 // EndOfChain sentinel is returned directly, not relative to pc or pos. | 666 // EndOfChain sentinel is returned directly, not relative to pc or pos. |
667 return kEndOfChain; | 667 return kEndOfChain; |
668 } else { | 668 } else { |
669 uint32_t instr_address = reinterpret_cast<int32_t>(buffer_ + pos); | 669 uint32_t instr_address = reinterpret_cast<int32_t>(buffer_ + pos); |
670 int32_t delta = instr_address - imm; | 670 int32_t delta = instr_address - imm; |
671 ASSERT(pos > delta); | 671 DCHECK(pos > delta); |
672 return pos - delta; | 672 return pos - delta; |
673 } | 673 } |
674 } else { | 674 } else { |
675 int32_t imm28 = (instr & static_cast<int32_t>(kImm26Mask)) << 2; | 675 int32_t imm28 = (instr & static_cast<int32_t>(kImm26Mask)) << 2; |
676 if (imm28 == kEndOfJumpChain) { | 676 if (imm28 == kEndOfJumpChain) { |
677 // EndOfChain sentinel is returned directly, not relative to pc or pos. | 677 // EndOfChain sentinel is returned directly, not relative to pc or pos. |
678 return kEndOfChain; | 678 return kEndOfChain; |
679 } else { | 679 } else { |
680 uint32_t instr_address = reinterpret_cast<int32_t>(buffer_ + pos); | 680 uint32_t instr_address = reinterpret_cast<int32_t>(buffer_ + pos); |
681 instr_address &= kImm28Mask; | 681 instr_address &= kImm28Mask; |
682 int32_t delta = instr_address - imm28; | 682 int32_t delta = instr_address - imm28; |
683 ASSERT(pos > delta); | 683 DCHECK(pos > delta); |
684 return pos - delta; | 684 return pos - delta; |
685 } | 685 } |
686 } | 686 } |
687 } | 687 } |
688 | 688 |
689 | 689 |
690 void Assembler::target_at_put(int32_t pos, int32_t target_pos) { | 690 void Assembler::target_at_put(int32_t pos, int32_t target_pos) { |
691 Instr instr = instr_at(pos); | 691 Instr instr = instr_at(pos); |
692 if ((instr & ~kImm16Mask) == 0) { | 692 if ((instr & ~kImm16Mask) == 0) { |
693 ASSERT(target_pos == kEndOfChain || target_pos >= 0); | 693 DCHECK(target_pos == kEndOfChain || target_pos >= 0); |
694 // Emitted label constant, not part of a branch. | 694 // Emitted label constant, not part of a branch. |
695 // Make label relative to Code* of generated Code object. | 695 // Make label relative to Code* of generated Code object. |
696 instr_at_put(pos, target_pos + (Code::kHeaderSize - kHeapObjectTag)); | 696 instr_at_put(pos, target_pos + (Code::kHeaderSize - kHeapObjectTag)); |
697 return; | 697 return; |
698 } | 698 } |
699 | 699 |
700 ASSERT(IsBranch(instr) || IsJ(instr) || IsLui(instr)); | 700 DCHECK(IsBranch(instr) || IsJ(instr) || IsLui(instr)); |
701 if (IsBranch(instr)) { | 701 if (IsBranch(instr)) { |
702 int32_t imm18 = target_pos - (pos + kBranchPCOffset); | 702 int32_t imm18 = target_pos - (pos + kBranchPCOffset); |
703 ASSERT((imm18 & 3) == 0); | 703 DCHECK((imm18 & 3) == 0); |
704 | 704 |
705 instr &= ~kImm16Mask; | 705 instr &= ~kImm16Mask; |
706 int32_t imm16 = imm18 >> 2; | 706 int32_t imm16 = imm18 >> 2; |
707 ASSERT(is_int16(imm16)); | 707 DCHECK(is_int16(imm16)); |
708 | 708 |
709 instr_at_put(pos, instr | (imm16 & kImm16Mask)); | 709 instr_at_put(pos, instr | (imm16 & kImm16Mask)); |
710 } else if (IsLui(instr)) { | 710 } else if (IsLui(instr)) { |
711 Instr instr_lui = instr_at(pos + 0 * Assembler::kInstrSize); | 711 Instr instr_lui = instr_at(pos + 0 * Assembler::kInstrSize); |
712 Instr instr_ori = instr_at(pos + 1 * Assembler::kInstrSize); | 712 Instr instr_ori = instr_at(pos + 1 * Assembler::kInstrSize); |
713 ASSERT(IsOri(instr_ori)); | 713 DCHECK(IsOri(instr_ori)); |
714 uint32_t imm = reinterpret_cast<uint32_t>(buffer_) + target_pos; | 714 uint32_t imm = reinterpret_cast<uint32_t>(buffer_) + target_pos; |
715 ASSERT((imm & 3) == 0); | 715 DCHECK((imm & 3) == 0); |
716 | 716 |
717 instr_lui &= ~kImm16Mask; | 717 instr_lui &= ~kImm16Mask; |
718 instr_ori &= ~kImm16Mask; | 718 instr_ori &= ~kImm16Mask; |
719 | 719 |
720 instr_at_put(pos + 0 * Assembler::kInstrSize, | 720 instr_at_put(pos + 0 * Assembler::kInstrSize, |
721 instr_lui | ((imm & kHiMask) >> kLuiShift)); | 721 instr_lui | ((imm & kHiMask) >> kLuiShift)); |
722 instr_at_put(pos + 1 * Assembler::kInstrSize, | 722 instr_at_put(pos + 1 * Assembler::kInstrSize, |
723 instr_ori | (imm & kImm16Mask)); | 723 instr_ori | (imm & kImm16Mask)); |
724 } else { | 724 } else { |
725 uint32_t imm28 = reinterpret_cast<uint32_t>(buffer_) + target_pos; | 725 uint32_t imm28 = reinterpret_cast<uint32_t>(buffer_) + target_pos; |
726 imm28 &= kImm28Mask; | 726 imm28 &= kImm28Mask; |
727 ASSERT((imm28 & 3) == 0); | 727 DCHECK((imm28 & 3) == 0); |
728 | 728 |
729 instr &= ~kImm26Mask; | 729 instr &= ~kImm26Mask; |
730 uint32_t imm26 = imm28 >> 2; | 730 uint32_t imm26 = imm28 >> 2; |
731 ASSERT(is_uint26(imm26)); | 731 DCHECK(is_uint26(imm26)); |
732 | 732 |
733 instr_at_put(pos, instr | (imm26 & kImm26Mask)); | 733 instr_at_put(pos, instr | (imm26 & kImm26Mask)); |
734 } | 734 } |
735 } | 735 } |
736 | 736 |
737 | 737 |
738 void Assembler::print(Label* L) { | 738 void Assembler::print(Label* L) { |
739 if (L->is_unused()) { | 739 if (L->is_unused()) { |
740 PrintF("unused label\n"); | 740 PrintF("unused label\n"); |
741 } else if (L->is_bound()) { | 741 } else if (L->is_bound()) { |
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753 } | 753 } |
754 next(&l); | 754 next(&l); |
755 } | 755 } |
756 } else { | 756 } else { |
757 PrintF("label in inconsistent state (pos = %d)\n", L->pos_); | 757 PrintF("label in inconsistent state (pos = %d)\n", L->pos_); |
758 } | 758 } |
759 } | 759 } |
760 | 760 |
761 | 761 |
762 void Assembler::bind_to(Label* L, int pos) { | 762 void Assembler::bind_to(Label* L, int pos) { |
763 ASSERT(0 <= pos && pos <= pc_offset()); // Must have valid binding position. | 763 DCHECK(0 <= pos && pos <= pc_offset()); // Must have valid binding position. |
764 int32_t trampoline_pos = kInvalidSlotPos; | 764 int32_t trampoline_pos = kInvalidSlotPos; |
765 if (L->is_linked() && !trampoline_emitted_) { | 765 if (L->is_linked() && !trampoline_emitted_) { |
766 unbound_labels_count_--; | 766 unbound_labels_count_--; |
767 next_buffer_check_ += kTrampolineSlotsSize; | 767 next_buffer_check_ += kTrampolineSlotsSize; |
768 } | 768 } |
769 | 769 |
770 while (L->is_linked()) { | 770 while (L->is_linked()) { |
771 int32_t fixup_pos = L->pos(); | 771 int32_t fixup_pos = L->pos(); |
772 int32_t dist = pos - fixup_pos; | 772 int32_t dist = pos - fixup_pos; |
773 next(L); // Call next before overwriting link with target at fixup_pos. | 773 next(L); // Call next before overwriting link with target at fixup_pos. |
774 Instr instr = instr_at(fixup_pos); | 774 Instr instr = instr_at(fixup_pos); |
775 if (IsBranch(instr)) { | 775 if (IsBranch(instr)) { |
776 if (dist > kMaxBranchOffset) { | 776 if (dist > kMaxBranchOffset) { |
777 if (trampoline_pos == kInvalidSlotPos) { | 777 if (trampoline_pos == kInvalidSlotPos) { |
778 trampoline_pos = get_trampoline_entry(fixup_pos); | 778 trampoline_pos = get_trampoline_entry(fixup_pos); |
779 CHECK(trampoline_pos != kInvalidSlotPos); | 779 CHECK(trampoline_pos != kInvalidSlotPos); |
780 } | 780 } |
781 ASSERT((trampoline_pos - fixup_pos) <= kMaxBranchOffset); | 781 DCHECK((trampoline_pos - fixup_pos) <= kMaxBranchOffset); |
782 target_at_put(fixup_pos, trampoline_pos); | 782 target_at_put(fixup_pos, trampoline_pos); |
783 fixup_pos = trampoline_pos; | 783 fixup_pos = trampoline_pos; |
784 dist = pos - fixup_pos; | 784 dist = pos - fixup_pos; |
785 } | 785 } |
786 target_at_put(fixup_pos, pos); | 786 target_at_put(fixup_pos, pos); |
787 } else { | 787 } else { |
788 ASSERT(IsJ(instr) || IsLui(instr) || IsEmittedConstant(instr)); | 788 DCHECK(IsJ(instr) || IsLui(instr) || IsEmittedConstant(instr)); |
789 target_at_put(fixup_pos, pos); | 789 target_at_put(fixup_pos, pos); |
790 } | 790 } |
791 } | 791 } |
792 L->bind_to(pos); | 792 L->bind_to(pos); |
793 | 793 |
794 // Keep track of the last bound label so we don't eliminate any instructions | 794 // Keep track of the last bound label so we don't eliminate any instructions |
795 // before a bound label. | 795 // before a bound label. |
796 if (pos > last_bound_pos_) | 796 if (pos > last_bound_pos_) |
797 last_bound_pos_ = pos; | 797 last_bound_pos_ = pos; |
798 } | 798 } |
799 | 799 |
800 | 800 |
801 void Assembler::bind(Label* L) { | 801 void Assembler::bind(Label* L) { |
802 ASSERT(!L->is_bound()); // Label can only be bound once. | 802 DCHECK(!L->is_bound()); // Label can only be bound once. |
803 bind_to(L, pc_offset()); | 803 bind_to(L, pc_offset()); |
804 } | 804 } |
805 | 805 |
806 | 806 |
807 void Assembler::next(Label* L) { | 807 void Assembler::next(Label* L) { |
808 ASSERT(L->is_linked()); | 808 DCHECK(L->is_linked()); |
809 int link = target_at(L->pos()); | 809 int link = target_at(L->pos()); |
810 if (link == kEndOfChain) { | 810 if (link == kEndOfChain) { |
811 L->Unuse(); | 811 L->Unuse(); |
812 } else { | 812 } else { |
813 ASSERT(link >= 0); | 813 DCHECK(link >= 0); |
814 L->link_to(link); | 814 L->link_to(link); |
815 } | 815 } |
816 } | 816 } |
817 | 817 |
818 | 818 |
819 bool Assembler::is_near(Label* L) { | 819 bool Assembler::is_near(Label* L) { |
820 if (L->is_bound()) { | 820 if (L->is_bound()) { |
821 return ((pc_offset() - L->pos()) < kMaxBranchOffset - 4 * kInstrSize); | 821 return ((pc_offset() - L->pos()) < kMaxBranchOffset - 4 * kInstrSize); |
822 } | 822 } |
823 return false; | 823 return false; |
824 } | 824 } |
825 | 825 |
826 | 826 |
827 // We have to use a temporary register for things that can be relocated even | 827 // We have to use a temporary register for things that can be relocated even |
828 // if they can be encoded in the MIPS's 16 bits of immediate-offset instruction | 828 // if they can be encoded in the MIPS's 16 bits of immediate-offset instruction |
829 // space. There is no guarantee that the relocated location can be similarly | 829 // space. There is no guarantee that the relocated location can be similarly |
830 // encoded. | 830 // encoded. |
831 bool Assembler::MustUseReg(RelocInfo::Mode rmode) { | 831 bool Assembler::MustUseReg(RelocInfo::Mode rmode) { |
832 return !RelocInfo::IsNone(rmode); | 832 return !RelocInfo::IsNone(rmode); |
833 } | 833 } |
834 | 834 |
835 void Assembler::GenInstrRegister(Opcode opcode, | 835 void Assembler::GenInstrRegister(Opcode opcode, |
836 Register rs, | 836 Register rs, |
837 Register rt, | 837 Register rt, |
838 Register rd, | 838 Register rd, |
839 uint16_t sa, | 839 uint16_t sa, |
840 SecondaryField func) { | 840 SecondaryField func) { |
841 ASSERT(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa)); | 841 DCHECK(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa)); |
842 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) | 842 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
843 | (rd.code() << kRdShift) | (sa << kSaShift) | func; | 843 | (rd.code() << kRdShift) | (sa << kSaShift) | func; |
844 emit(instr); | 844 emit(instr); |
845 } | 845 } |
846 | 846 |
847 | 847 |
848 void Assembler::GenInstrRegister(Opcode opcode, | 848 void Assembler::GenInstrRegister(Opcode opcode, |
849 Register rs, | 849 Register rs, |
850 Register rt, | 850 Register rt, |
851 uint16_t msb, | 851 uint16_t msb, |
852 uint16_t lsb, | 852 uint16_t lsb, |
853 SecondaryField func) { | 853 SecondaryField func) { |
854 ASSERT(rs.is_valid() && rt.is_valid() && is_uint5(msb) && is_uint5(lsb)); | 854 DCHECK(rs.is_valid() && rt.is_valid() && is_uint5(msb) && is_uint5(lsb)); |
855 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) | 855 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
856 | (msb << kRdShift) | (lsb << kSaShift) | func; | 856 | (msb << kRdShift) | (lsb << kSaShift) | func; |
857 emit(instr); | 857 emit(instr); |
858 } | 858 } |
859 | 859 |
860 | 860 |
861 void Assembler::GenInstrRegister(Opcode opcode, | 861 void Assembler::GenInstrRegister(Opcode opcode, |
862 SecondaryField fmt, | 862 SecondaryField fmt, |
863 FPURegister ft, | 863 FPURegister ft, |
864 FPURegister fs, | 864 FPURegister fs, |
865 FPURegister fd, | 865 FPURegister fd, |
866 SecondaryField func) { | 866 SecondaryField func) { |
867 ASSERT(fd.is_valid() && fs.is_valid() && ft.is_valid()); | 867 DCHECK(fd.is_valid() && fs.is_valid() && ft.is_valid()); |
868 Instr instr = opcode | fmt | (ft.code() << kFtShift) | (fs.code() << kFsShift) | 868 Instr instr = opcode | fmt | (ft.code() << kFtShift) | (fs.code() << kFsShift) |
869 | (fd.code() << kFdShift) | func; | 869 | (fd.code() << kFdShift) | func; |
870 emit(instr); | 870 emit(instr); |
871 } | 871 } |
872 | 872 |
873 | 873 |
874 void Assembler::GenInstrRegister(Opcode opcode, | 874 void Assembler::GenInstrRegister(Opcode opcode, |
875 FPURegister fr, | 875 FPURegister fr, |
876 FPURegister ft, | 876 FPURegister ft, |
877 FPURegister fs, | 877 FPURegister fs, |
878 FPURegister fd, | 878 FPURegister fd, |
879 SecondaryField func) { | 879 SecondaryField func) { |
880 ASSERT(fd.is_valid() && fr.is_valid() && fs.is_valid() && ft.is_valid()); | 880 DCHECK(fd.is_valid() && fr.is_valid() && fs.is_valid() && ft.is_valid()); |
881 Instr instr = opcode | (fr.code() << kFrShift) | (ft.code() << kFtShift) | 881 Instr instr = opcode | (fr.code() << kFrShift) | (ft.code() << kFtShift) |
882 | (fs.code() << kFsShift) | (fd.code() << kFdShift) | func; | 882 | (fs.code() << kFsShift) | (fd.code() << kFdShift) | func; |
883 emit(instr); | 883 emit(instr); |
884 } | 884 } |
885 | 885 |
886 | 886 |
887 void Assembler::GenInstrRegister(Opcode opcode, | 887 void Assembler::GenInstrRegister(Opcode opcode, |
888 SecondaryField fmt, | 888 SecondaryField fmt, |
889 Register rt, | 889 Register rt, |
890 FPURegister fs, | 890 FPURegister fs, |
891 FPURegister fd, | 891 FPURegister fd, |
892 SecondaryField func) { | 892 SecondaryField func) { |
893 ASSERT(fd.is_valid() && fs.is_valid() && rt.is_valid()); | 893 DCHECK(fd.is_valid() && fs.is_valid() && rt.is_valid()); |
894 Instr instr = opcode | fmt | (rt.code() << kRtShift) | 894 Instr instr = opcode | fmt | (rt.code() << kRtShift) |
895 | (fs.code() << kFsShift) | (fd.code() << kFdShift) | func; | 895 | (fs.code() << kFsShift) | (fd.code() << kFdShift) | func; |
896 emit(instr); | 896 emit(instr); |
897 } | 897 } |
898 | 898 |
899 | 899 |
900 void Assembler::GenInstrRegister(Opcode opcode, | 900 void Assembler::GenInstrRegister(Opcode opcode, |
901 SecondaryField fmt, | 901 SecondaryField fmt, |
902 Register rt, | 902 Register rt, |
903 FPUControlRegister fs, | 903 FPUControlRegister fs, |
904 SecondaryField func) { | 904 SecondaryField func) { |
905 ASSERT(fs.is_valid() && rt.is_valid()); | 905 DCHECK(fs.is_valid() && rt.is_valid()); |
906 Instr instr = | 906 Instr instr = |
907 opcode | fmt | (rt.code() << kRtShift) | (fs.code() << kFsShift) | func; | 907 opcode | fmt | (rt.code() << kRtShift) | (fs.code() << kFsShift) | func; |
908 emit(instr); | 908 emit(instr); |
909 } | 909 } |
910 | 910 |
911 | 911 |
912 // Instructions with immediate value. | 912 // Instructions with immediate value. |
913 // Registers are in the order of the instruction encoding, from left to right. | 913 // Registers are in the order of the instruction encoding, from left to right. |
914 void Assembler::GenInstrImmediate(Opcode opcode, | 914 void Assembler::GenInstrImmediate(Opcode opcode, |
915 Register rs, | 915 Register rs, |
916 Register rt, | 916 Register rt, |
917 int32_t j) { | 917 int32_t j) { |
918 ASSERT(rs.is_valid() && rt.is_valid() && (is_int16(j) || is_uint16(j))); | 918 DCHECK(rs.is_valid() && rt.is_valid() && (is_int16(j) || is_uint16(j))); |
919 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) | 919 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
920 | (j & kImm16Mask); | 920 | (j & kImm16Mask); |
921 emit(instr); | 921 emit(instr); |
922 } | 922 } |
923 | 923 |
924 | 924 |
925 void Assembler::GenInstrImmediate(Opcode opcode, | 925 void Assembler::GenInstrImmediate(Opcode opcode, |
926 Register rs, | 926 Register rs, |
927 SecondaryField SF, | 927 SecondaryField SF, |
928 int32_t j) { | 928 int32_t j) { |
929 ASSERT(rs.is_valid() && (is_int16(j) || is_uint16(j))); | 929 DCHECK(rs.is_valid() && (is_int16(j) || is_uint16(j))); |
930 Instr instr = opcode | (rs.code() << kRsShift) | SF | (j & kImm16Mask); | 930 Instr instr = opcode | (rs.code() << kRsShift) | SF | (j & kImm16Mask); |
931 emit(instr); | 931 emit(instr); |
932 } | 932 } |
933 | 933 |
934 | 934 |
935 void Assembler::GenInstrImmediate(Opcode opcode, | 935 void Assembler::GenInstrImmediate(Opcode opcode, |
936 Register rs, | 936 Register rs, |
937 FPURegister ft, | 937 FPURegister ft, |
938 int32_t j) { | 938 int32_t j) { |
939 ASSERT(rs.is_valid() && ft.is_valid() && (is_int16(j) || is_uint16(j))); | 939 DCHECK(rs.is_valid() && ft.is_valid() && (is_int16(j) || is_uint16(j))); |
940 Instr instr = opcode | (rs.code() << kRsShift) | (ft.code() << kFtShift) | 940 Instr instr = opcode | (rs.code() << kRsShift) | (ft.code() << kFtShift) |
941 | (j & kImm16Mask); | 941 | (j & kImm16Mask); |
942 emit(instr); | 942 emit(instr); |
943 } | 943 } |
944 | 944 |
945 | 945 |
946 void Assembler::GenInstrJump(Opcode opcode, | 946 void Assembler::GenInstrJump(Opcode opcode, |
947 uint32_t address) { | 947 uint32_t address) { |
948 BlockTrampolinePoolScope block_trampoline_pool(this); | 948 BlockTrampolinePoolScope block_trampoline_pool(this); |
949 ASSERT(is_uint26(address)); | 949 DCHECK(is_uint26(address)); |
950 Instr instr = opcode | address; | 950 Instr instr = opcode | address; |
951 emit(instr); | 951 emit(instr); |
952 BlockTrampolinePoolFor(1); // For associated delay slot. | 952 BlockTrampolinePoolFor(1); // For associated delay slot. |
953 } | 953 } |
954 | 954 |
955 | 955 |
956 // Returns the next free trampoline entry. | 956 // Returns the next free trampoline entry. |
957 int32_t Assembler::get_trampoline_entry(int32_t pos) { | 957 int32_t Assembler::get_trampoline_entry(int32_t pos) { |
958 int32_t trampoline_entry = kInvalidSlotPos; | 958 int32_t trampoline_entry = kInvalidSlotPos; |
959 | 959 |
(...skipping 19 matching lines...) Expand all Loading... |
979 if (L->is_linked()) { | 979 if (L->is_linked()) { |
980 target_pos = L->pos(); // L's link. | 980 target_pos = L->pos(); // L's link. |
981 L->link_to(pc_offset()); | 981 L->link_to(pc_offset()); |
982 } else { | 982 } else { |
983 L->link_to(pc_offset()); | 983 L->link_to(pc_offset()); |
984 return kEndOfJumpChain; | 984 return kEndOfJumpChain; |
985 } | 985 } |
986 } | 986 } |
987 | 987 |
988 uint32_t imm = reinterpret_cast<uint32_t>(buffer_) + target_pos; | 988 uint32_t imm = reinterpret_cast<uint32_t>(buffer_) + target_pos; |
989 ASSERT((imm & 3) == 0); | 989 DCHECK((imm & 3) == 0); |
990 | 990 |
991 return imm; | 991 return imm; |
992 } | 992 } |
993 | 993 |
994 | 994 |
995 int32_t Assembler::branch_offset(Label* L, bool jump_elimination_allowed) { | 995 int32_t Assembler::branch_offset(Label* L, bool jump_elimination_allowed) { |
996 int32_t target_pos; | 996 int32_t target_pos; |
997 | 997 |
998 if (L->is_bound()) { | 998 if (L->is_bound()) { |
999 target_pos = L->pos(); | 999 target_pos = L->pos(); |
1000 } else { | 1000 } else { |
1001 if (L->is_linked()) { | 1001 if (L->is_linked()) { |
1002 target_pos = L->pos(); | 1002 target_pos = L->pos(); |
1003 L->link_to(pc_offset()); | 1003 L->link_to(pc_offset()); |
1004 } else { | 1004 } else { |
1005 L->link_to(pc_offset()); | 1005 L->link_to(pc_offset()); |
1006 if (!trampoline_emitted_) { | 1006 if (!trampoline_emitted_) { |
1007 unbound_labels_count_++; | 1007 unbound_labels_count_++; |
1008 next_buffer_check_ -= kTrampolineSlotsSize; | 1008 next_buffer_check_ -= kTrampolineSlotsSize; |
1009 } | 1009 } |
1010 return kEndOfChain; | 1010 return kEndOfChain; |
1011 } | 1011 } |
1012 } | 1012 } |
1013 | 1013 |
1014 int32_t offset = target_pos - (pc_offset() + kBranchPCOffset); | 1014 int32_t offset = target_pos - (pc_offset() + kBranchPCOffset); |
1015 ASSERT((offset & 3) == 0); | 1015 DCHECK((offset & 3) == 0); |
1016 ASSERT(is_int16(offset >> 2)); | 1016 DCHECK(is_int16(offset >> 2)); |
1017 | 1017 |
1018 return offset; | 1018 return offset; |
1019 } | 1019 } |
1020 | 1020 |
1021 | 1021 |
1022 void Assembler::label_at_put(Label* L, int at_offset) { | 1022 void Assembler::label_at_put(Label* L, int at_offset) { |
1023 int target_pos; | 1023 int target_pos; |
1024 if (L->is_bound()) { | 1024 if (L->is_bound()) { |
1025 target_pos = L->pos(); | 1025 target_pos = L->pos(); |
1026 instr_at_put(at_offset, target_pos + (Code::kHeaderSize - kHeapObjectTag)); | 1026 instr_at_put(at_offset, target_pos + (Code::kHeaderSize - kHeapObjectTag)); |
1027 } else { | 1027 } else { |
1028 if (L->is_linked()) { | 1028 if (L->is_linked()) { |
1029 target_pos = L->pos(); // L's link. | 1029 target_pos = L->pos(); // L's link. |
1030 int32_t imm18 = target_pos - at_offset; | 1030 int32_t imm18 = target_pos - at_offset; |
1031 ASSERT((imm18 & 3) == 0); | 1031 DCHECK((imm18 & 3) == 0); |
1032 int32_t imm16 = imm18 >> 2; | 1032 int32_t imm16 = imm18 >> 2; |
1033 ASSERT(is_int16(imm16)); | 1033 DCHECK(is_int16(imm16)); |
1034 instr_at_put(at_offset, (imm16 & kImm16Mask)); | 1034 instr_at_put(at_offset, (imm16 & kImm16Mask)); |
1035 } else { | 1035 } else { |
1036 target_pos = kEndOfChain; | 1036 target_pos = kEndOfChain; |
1037 instr_at_put(at_offset, 0); | 1037 instr_at_put(at_offset, 0); |
1038 if (!trampoline_emitted_) { | 1038 if (!trampoline_emitted_) { |
1039 unbound_labels_count_++; | 1039 unbound_labels_count_++; |
1040 next_buffer_check_ -= kTrampolineSlotsSize; | 1040 next_buffer_check_ -= kTrampolineSlotsSize; |
1041 } | 1041 } |
1042 } | 1042 } |
1043 L->link_to(at_offset); | 1043 L->link_to(at_offset); |
(...skipping 71 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1115 BlockTrampolinePoolFor(1); // For associated delay slot. | 1115 BlockTrampolinePoolFor(1); // For associated delay slot. |
1116 } | 1116 } |
1117 | 1117 |
1118 | 1118 |
1119 void Assembler::j(int32_t target) { | 1119 void Assembler::j(int32_t target) { |
1120 #if DEBUG | 1120 #if DEBUG |
1121 // Get pc of delay slot. | 1121 // Get pc of delay slot. |
1122 uint32_t ipc = reinterpret_cast<uint32_t>(pc_ + 1 * kInstrSize); | 1122 uint32_t ipc = reinterpret_cast<uint32_t>(pc_ + 1 * kInstrSize); |
1123 bool in_range = (ipc ^ static_cast<uint32_t>(target) >> | 1123 bool in_range = (ipc ^ static_cast<uint32_t>(target) >> |
1124 (kImm26Bits + kImmFieldShift)) == 0; | 1124 (kImm26Bits + kImmFieldShift)) == 0; |
1125 ASSERT(in_range && ((target & 3) == 0)); | 1125 DCHECK(in_range && ((target & 3) == 0)); |
1126 #endif | 1126 #endif |
1127 GenInstrJump(J, target >> 2); | 1127 GenInstrJump(J, target >> 2); |
1128 } | 1128 } |
1129 | 1129 |
1130 | 1130 |
1131 void Assembler::jr(Register rs) { | 1131 void Assembler::jr(Register rs) { |
1132 BlockTrampolinePoolScope block_trampoline_pool(this); | 1132 BlockTrampolinePoolScope block_trampoline_pool(this); |
1133 if (rs.is(ra)) { | 1133 if (rs.is(ra)) { |
1134 positions_recorder()->WriteRecordedPositions(); | 1134 positions_recorder()->WriteRecordedPositions(); |
1135 } | 1135 } |
1136 GenInstrRegister(SPECIAL, rs, zero_reg, zero_reg, 0, JR); | 1136 GenInstrRegister(SPECIAL, rs, zero_reg, zero_reg, 0, JR); |
1137 BlockTrampolinePoolFor(1); // For associated delay slot. | 1137 BlockTrampolinePoolFor(1); // For associated delay slot. |
1138 } | 1138 } |
1139 | 1139 |
1140 | 1140 |
1141 void Assembler::jal(int32_t target) { | 1141 void Assembler::jal(int32_t target) { |
1142 #ifdef DEBUG | 1142 #ifdef DEBUG |
1143 // Get pc of delay slot. | 1143 // Get pc of delay slot. |
1144 uint32_t ipc = reinterpret_cast<uint32_t>(pc_ + 1 * kInstrSize); | 1144 uint32_t ipc = reinterpret_cast<uint32_t>(pc_ + 1 * kInstrSize); |
1145 bool in_range = (ipc ^ static_cast<uint32_t>(target) >> | 1145 bool in_range = (ipc ^ static_cast<uint32_t>(target) >> |
1146 (kImm26Bits + kImmFieldShift)) == 0; | 1146 (kImm26Bits + kImmFieldShift)) == 0; |
1147 ASSERT(in_range && ((target & 3) == 0)); | 1147 DCHECK(in_range && ((target & 3) == 0)); |
1148 #endif | 1148 #endif |
1149 positions_recorder()->WriteRecordedPositions(); | 1149 positions_recorder()->WriteRecordedPositions(); |
1150 GenInstrJump(JAL, target >> 2); | 1150 GenInstrJump(JAL, target >> 2); |
1151 } | 1151 } |
1152 | 1152 |
1153 | 1153 |
1154 void Assembler::jalr(Register rs, Register rd) { | 1154 void Assembler::jalr(Register rs, Register rd) { |
1155 BlockTrampolinePoolScope block_trampoline_pool(this); | 1155 BlockTrampolinePoolScope block_trampoline_pool(this); |
1156 positions_recorder()->WriteRecordedPositions(); | 1156 positions_recorder()->WriteRecordedPositions(); |
1157 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR); | 1157 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR); |
(...skipping 72 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1230 | 1230 |
1231 | 1231 |
1232 // Logical. | 1232 // Logical. |
1233 | 1233 |
1234 void Assembler::and_(Register rd, Register rs, Register rt) { | 1234 void Assembler::and_(Register rd, Register rs, Register rt) { |
1235 GenInstrRegister(SPECIAL, rs, rt, rd, 0, AND); | 1235 GenInstrRegister(SPECIAL, rs, rt, rd, 0, AND); |
1236 } | 1236 } |
1237 | 1237 |
1238 | 1238 |
1239 void Assembler::andi(Register rt, Register rs, int32_t j) { | 1239 void Assembler::andi(Register rt, Register rs, int32_t j) { |
1240 ASSERT(is_uint16(j)); | 1240 DCHECK(is_uint16(j)); |
1241 GenInstrImmediate(ANDI, rs, rt, j); | 1241 GenInstrImmediate(ANDI, rs, rt, j); |
1242 } | 1242 } |
1243 | 1243 |
1244 | 1244 |
1245 void Assembler::or_(Register rd, Register rs, Register rt) { | 1245 void Assembler::or_(Register rd, Register rs, Register rt) { |
1246 GenInstrRegister(SPECIAL, rs, rt, rd, 0, OR); | 1246 GenInstrRegister(SPECIAL, rs, rt, rd, 0, OR); |
1247 } | 1247 } |
1248 | 1248 |
1249 | 1249 |
1250 void Assembler::ori(Register rt, Register rs, int32_t j) { | 1250 void Assembler::ori(Register rt, Register rs, int32_t j) { |
1251 ASSERT(is_uint16(j)); | 1251 DCHECK(is_uint16(j)); |
1252 GenInstrImmediate(ORI, rs, rt, j); | 1252 GenInstrImmediate(ORI, rs, rt, j); |
1253 } | 1253 } |
1254 | 1254 |
1255 | 1255 |
1256 void Assembler::xor_(Register rd, Register rs, Register rt) { | 1256 void Assembler::xor_(Register rd, Register rs, Register rt) { |
1257 GenInstrRegister(SPECIAL, rs, rt, rd, 0, XOR); | 1257 GenInstrRegister(SPECIAL, rs, rt, rd, 0, XOR); |
1258 } | 1258 } |
1259 | 1259 |
1260 | 1260 |
1261 void Assembler::xori(Register rt, Register rs, int32_t j) { | 1261 void Assembler::xori(Register rt, Register rs, int32_t j) { |
1262 ASSERT(is_uint16(j)); | 1262 DCHECK(is_uint16(j)); |
1263 GenInstrImmediate(XORI, rs, rt, j); | 1263 GenInstrImmediate(XORI, rs, rt, j); |
1264 } | 1264 } |
1265 | 1265 |
1266 | 1266 |
1267 void Assembler::nor(Register rd, Register rs, Register rt) { | 1267 void Assembler::nor(Register rd, Register rs, Register rt) { |
1268 GenInstrRegister(SPECIAL, rs, rt, rd, 0, NOR); | 1268 GenInstrRegister(SPECIAL, rs, rt, rd, 0, NOR); |
1269 } | 1269 } |
1270 | 1270 |
1271 | 1271 |
1272 // Shifts. | 1272 // Shifts. |
1273 void Assembler::sll(Register rd, | 1273 void Assembler::sll(Register rd, |
1274 Register rt, | 1274 Register rt, |
1275 uint16_t sa, | 1275 uint16_t sa, |
1276 bool coming_from_nop) { | 1276 bool coming_from_nop) { |
1277 // Don't allow nop instructions in the form sll zero_reg, zero_reg to be | 1277 // Don't allow nop instructions in the form sll zero_reg, zero_reg to be |
1278 // generated using the sll instruction. They must be generated using | 1278 // generated using the sll instruction. They must be generated using |
1279 // nop(int/NopMarkerTypes) or MarkCode(int/NopMarkerTypes) pseudo | 1279 // nop(int/NopMarkerTypes) or MarkCode(int/NopMarkerTypes) pseudo |
1280 // instructions. | 1280 // instructions. |
1281 ASSERT(coming_from_nop || !(rd.is(zero_reg) && rt.is(zero_reg))); | 1281 DCHECK(coming_from_nop || !(rd.is(zero_reg) && rt.is(zero_reg))); |
1282 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SLL); | 1282 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SLL); |
1283 } | 1283 } |
1284 | 1284 |
1285 | 1285 |
1286 void Assembler::sllv(Register rd, Register rt, Register rs) { | 1286 void Assembler::sllv(Register rd, Register rt, Register rs) { |
1287 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLLV); | 1287 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLLV); |
1288 } | 1288 } |
1289 | 1289 |
1290 | 1290 |
1291 void Assembler::srl(Register rd, Register rt, uint16_t sa) { | 1291 void Assembler::srl(Register rd, Register rt, uint16_t sa) { |
(...skipping 11 matching lines...) Expand all Loading... |
1303 } | 1303 } |
1304 | 1304 |
1305 | 1305 |
1306 void Assembler::srav(Register rd, Register rt, Register rs) { | 1306 void Assembler::srav(Register rd, Register rt, Register rs) { |
1307 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRAV); | 1307 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRAV); |
1308 } | 1308 } |
1309 | 1309 |
1310 | 1310 |
1311 void Assembler::rotr(Register rd, Register rt, uint16_t sa) { | 1311 void Assembler::rotr(Register rd, Register rt, uint16_t sa) { |
1312 // Should be called via MacroAssembler::Ror. | 1312 // Should be called via MacroAssembler::Ror. |
1313 ASSERT(rd.is_valid() && rt.is_valid() && is_uint5(sa)); | 1313 DCHECK(rd.is_valid() && rt.is_valid() && is_uint5(sa)); |
1314 ASSERT(kArchVariant == kMips32r2); | 1314 DCHECK(kArchVariant == kMips32r2); |
1315 Instr instr = SPECIAL | (1 << kRsShift) | (rt.code() << kRtShift) | 1315 Instr instr = SPECIAL | (1 << kRsShift) | (rt.code() << kRtShift) |
1316 | (rd.code() << kRdShift) | (sa << kSaShift) | SRL; | 1316 | (rd.code() << kRdShift) | (sa << kSaShift) | SRL; |
1317 emit(instr); | 1317 emit(instr); |
1318 } | 1318 } |
1319 | 1319 |
1320 | 1320 |
1321 void Assembler::rotrv(Register rd, Register rt, Register rs) { | 1321 void Assembler::rotrv(Register rd, Register rt, Register rs) { |
1322 // Should be called via MacroAssembler::Ror. | 1322 // Should be called via MacroAssembler::Ror. |
1323 ASSERT(rd.is_valid() && rt.is_valid() && rs.is_valid() ); | 1323 DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid() ); |
1324 ASSERT(kArchVariant == kMips32r2); | 1324 DCHECK(kArchVariant == kMips32r2); |
1325 Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift) | 1325 Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
1326 | (rd.code() << kRdShift) | (1 << kSaShift) | SRLV; | 1326 | (rd.code() << kRdShift) | (1 << kSaShift) | SRLV; |
1327 emit(instr); | 1327 emit(instr); |
1328 } | 1328 } |
1329 | 1329 |
1330 | 1330 |
1331 // ------------Memory-instructions------------- | 1331 // ------------Memory-instructions------------- |
1332 | 1332 |
1333 // Helper for base-reg + offset, when offset is larger than int16. | 1333 // Helper for base-reg + offset, when offset is larger than int16. |
1334 void Assembler::LoadRegPlusOffsetToAt(const MemOperand& src) { | 1334 void Assembler::LoadRegPlusOffsetToAt(const MemOperand& src) { |
1335 ASSERT(!src.rm().is(at)); | 1335 DCHECK(!src.rm().is(at)); |
1336 lui(at, (src.offset_ >> kLuiShift) & kImm16Mask); | 1336 lui(at, (src.offset_ >> kLuiShift) & kImm16Mask); |
1337 ori(at, at, src.offset_ & kImm16Mask); // Load 32-bit offset. | 1337 ori(at, at, src.offset_ & kImm16Mask); // Load 32-bit offset. |
1338 addu(at, at, src.rm()); // Add base register. | 1338 addu(at, at, src.rm()); // Add base register. |
1339 } | 1339 } |
1340 | 1340 |
1341 | 1341 |
1342 void Assembler::lb(Register rd, const MemOperand& rs) { | 1342 void Assembler::lb(Register rd, const MemOperand& rs) { |
1343 if (is_int16(rs.offset_)) { | 1343 if (is_int16(rs.offset_)) { |
1344 GenInstrImmediate(LB, rs.rm(), rd, rs.offset_); | 1344 GenInstrImmediate(LB, rs.rm(), rd, rs.offset_); |
1345 } else { // Offset > 16 bits, use multiple instructions to load. | 1345 } else { // Offset > 16 bits, use multiple instructions to load. |
(...skipping 87 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1433 GenInstrImmediate(SWL, rs.rm(), rd, rs.offset_); | 1433 GenInstrImmediate(SWL, rs.rm(), rd, rs.offset_); |
1434 } | 1434 } |
1435 | 1435 |
1436 | 1436 |
1437 void Assembler::swr(Register rd, const MemOperand& rs) { | 1437 void Assembler::swr(Register rd, const MemOperand& rs) { |
1438 GenInstrImmediate(SWR, rs.rm(), rd, rs.offset_); | 1438 GenInstrImmediate(SWR, rs.rm(), rd, rs.offset_); |
1439 } | 1439 } |
1440 | 1440 |
1441 | 1441 |
1442 void Assembler::lui(Register rd, int32_t j) { | 1442 void Assembler::lui(Register rd, int32_t j) { |
1443 ASSERT(is_uint16(j)); | 1443 DCHECK(is_uint16(j)); |
1444 GenInstrImmediate(LUI, zero_reg, rd, j); | 1444 GenInstrImmediate(LUI, zero_reg, rd, j); |
1445 } | 1445 } |
1446 | 1446 |
1447 | 1447 |
1448 // -------------Misc-instructions-------------- | 1448 // -------------Misc-instructions-------------- |
1449 | 1449 |
1450 // Break / Trap instructions. | 1450 // Break / Trap instructions. |
1451 void Assembler::break_(uint32_t code, bool break_as_stop) { | 1451 void Assembler::break_(uint32_t code, bool break_as_stop) { |
1452 ASSERT((code & ~0xfffff) == 0); | 1452 DCHECK((code & ~0xfffff) == 0); |
1453 // We need to invalidate breaks that could be stops as well because the | 1453 // We need to invalidate breaks that could be stops as well because the |
1454 // simulator expects a char pointer after the stop instruction. | 1454 // simulator expects a char pointer after the stop instruction. |
1455 // See constants-mips.h for explanation. | 1455 // See constants-mips.h for explanation. |
1456 ASSERT((break_as_stop && | 1456 DCHECK((break_as_stop && |
1457 code <= kMaxStopCode && | 1457 code <= kMaxStopCode && |
1458 code > kMaxWatchpointCode) || | 1458 code > kMaxWatchpointCode) || |
1459 (!break_as_stop && | 1459 (!break_as_stop && |
1460 (code > kMaxStopCode || | 1460 (code > kMaxStopCode || |
1461 code <= kMaxWatchpointCode))); | 1461 code <= kMaxWatchpointCode))); |
1462 Instr break_instr = SPECIAL | BREAK | (code << 6); | 1462 Instr break_instr = SPECIAL | BREAK | (code << 6); |
1463 emit(break_instr); | 1463 emit(break_instr); |
1464 } | 1464 } |
1465 | 1465 |
1466 | 1466 |
1467 void Assembler::stop(const char* msg, uint32_t code) { | 1467 void Assembler::stop(const char* msg, uint32_t code) { |
1468 ASSERT(code > kMaxWatchpointCode); | 1468 DCHECK(code > kMaxWatchpointCode); |
1469 ASSERT(code <= kMaxStopCode); | 1469 DCHECK(code <= kMaxStopCode); |
1470 #if V8_HOST_ARCH_MIPS | 1470 #if V8_HOST_ARCH_MIPS |
1471 break_(0x54321); | 1471 break_(0x54321); |
1472 #else // V8_HOST_ARCH_MIPS | 1472 #else // V8_HOST_ARCH_MIPS |
1473 BlockTrampolinePoolFor(2); | 1473 BlockTrampolinePoolFor(2); |
1474 // The Simulator will handle the stop instruction and get the message address. | 1474 // The Simulator will handle the stop instruction and get the message address. |
1475 // On MIPS stop() is just a special kind of break_(). | 1475 // On MIPS stop() is just a special kind of break_(). |
1476 break_(code, true); | 1476 break_(code, true); |
1477 emit(reinterpret_cast<Instr>(msg)); | 1477 emit(reinterpret_cast<Instr>(msg)); |
1478 #endif | 1478 #endif |
1479 } | 1479 } |
1480 | 1480 |
1481 | 1481 |
1482 void Assembler::tge(Register rs, Register rt, uint16_t code) { | 1482 void Assembler::tge(Register rs, Register rt, uint16_t code) { |
1483 ASSERT(is_uint10(code)); | 1483 DCHECK(is_uint10(code)); |
1484 Instr instr = SPECIAL | TGE | rs.code() << kRsShift | 1484 Instr instr = SPECIAL | TGE | rs.code() << kRsShift |
1485 | rt.code() << kRtShift | code << 6; | 1485 | rt.code() << kRtShift | code << 6; |
1486 emit(instr); | 1486 emit(instr); |
1487 } | 1487 } |
1488 | 1488 |
1489 | 1489 |
1490 void Assembler::tgeu(Register rs, Register rt, uint16_t code) { | 1490 void Assembler::tgeu(Register rs, Register rt, uint16_t code) { |
1491 ASSERT(is_uint10(code)); | 1491 DCHECK(is_uint10(code)); |
1492 Instr instr = SPECIAL | TGEU | rs.code() << kRsShift | 1492 Instr instr = SPECIAL | TGEU | rs.code() << kRsShift |
1493 | rt.code() << kRtShift | code << 6; | 1493 | rt.code() << kRtShift | code << 6; |
1494 emit(instr); | 1494 emit(instr); |
1495 } | 1495 } |
1496 | 1496 |
1497 | 1497 |
1498 void Assembler::tlt(Register rs, Register rt, uint16_t code) { | 1498 void Assembler::tlt(Register rs, Register rt, uint16_t code) { |
1499 ASSERT(is_uint10(code)); | 1499 DCHECK(is_uint10(code)); |
1500 Instr instr = | 1500 Instr instr = |
1501 SPECIAL | TLT | rs.code() << kRsShift | rt.code() << kRtShift | code << 6; | 1501 SPECIAL | TLT | rs.code() << kRsShift | rt.code() << kRtShift | code << 6; |
1502 emit(instr); | 1502 emit(instr); |
1503 } | 1503 } |
1504 | 1504 |
1505 | 1505 |
1506 void Assembler::tltu(Register rs, Register rt, uint16_t code) { | 1506 void Assembler::tltu(Register rs, Register rt, uint16_t code) { |
1507 ASSERT(is_uint10(code)); | 1507 DCHECK(is_uint10(code)); |
1508 Instr instr = | 1508 Instr instr = |
1509 SPECIAL | TLTU | rs.code() << kRsShift | 1509 SPECIAL | TLTU | rs.code() << kRsShift |
1510 | rt.code() << kRtShift | code << 6; | 1510 | rt.code() << kRtShift | code << 6; |
1511 emit(instr); | 1511 emit(instr); |
1512 } | 1512 } |
1513 | 1513 |
1514 | 1514 |
1515 void Assembler::teq(Register rs, Register rt, uint16_t code) { | 1515 void Assembler::teq(Register rs, Register rt, uint16_t code) { |
1516 ASSERT(is_uint10(code)); | 1516 DCHECK(is_uint10(code)); |
1517 Instr instr = | 1517 Instr instr = |
1518 SPECIAL | TEQ | rs.code() << kRsShift | rt.code() << kRtShift | code << 6; | 1518 SPECIAL | TEQ | rs.code() << kRsShift | rt.code() << kRtShift | code << 6; |
1519 emit(instr); | 1519 emit(instr); |
1520 } | 1520 } |
1521 | 1521 |
1522 | 1522 |
1523 void Assembler::tne(Register rs, Register rt, uint16_t code) { | 1523 void Assembler::tne(Register rs, Register rt, uint16_t code) { |
1524 ASSERT(is_uint10(code)); | 1524 DCHECK(is_uint10(code)); |
1525 Instr instr = | 1525 Instr instr = |
1526 SPECIAL | TNE | rs.code() << kRsShift | rt.code() << kRtShift | code << 6; | 1526 SPECIAL | TNE | rs.code() << kRsShift | rt.code() << kRtShift | code << 6; |
1527 emit(instr); | 1527 emit(instr); |
1528 } | 1528 } |
1529 | 1529 |
1530 | 1530 |
1531 // Move from HI/LO register. | 1531 // Move from HI/LO register. |
1532 | 1532 |
1533 void Assembler::mfhi(Register rd) { | 1533 void Assembler::mfhi(Register rd) { |
1534 GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFHI); | 1534 GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFHI); |
(...skipping 54 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1589 // Bit twiddling. | 1589 // Bit twiddling. |
1590 void Assembler::clz(Register rd, Register rs) { | 1590 void Assembler::clz(Register rd, Register rs) { |
1591 // Clz instr requires same GPR number in 'rd' and 'rt' fields. | 1591 // Clz instr requires same GPR number in 'rd' and 'rt' fields. |
1592 GenInstrRegister(SPECIAL2, rs, rd, rd, 0, CLZ); | 1592 GenInstrRegister(SPECIAL2, rs, rd, rd, 0, CLZ); |
1593 } | 1593 } |
1594 | 1594 |
1595 | 1595 |
1596 void Assembler::ins_(Register rt, Register rs, uint16_t pos, uint16_t size) { | 1596 void Assembler::ins_(Register rt, Register rs, uint16_t pos, uint16_t size) { |
1597 // Should be called via MacroAssembler::Ins. | 1597 // Should be called via MacroAssembler::Ins. |
1598 // Ins instr has 'rt' field as dest, and two uint5: msb, lsb. | 1598 // Ins instr has 'rt' field as dest, and two uint5: msb, lsb. |
1599 ASSERT(kArchVariant == kMips32r2); | 1599 DCHECK(kArchVariant == kMips32r2); |
1600 GenInstrRegister(SPECIAL3, rs, rt, pos + size - 1, pos, INS); | 1600 GenInstrRegister(SPECIAL3, rs, rt, pos + size - 1, pos, INS); |
1601 } | 1601 } |
1602 | 1602 |
1603 | 1603 |
1604 void Assembler::ext_(Register rt, Register rs, uint16_t pos, uint16_t size) { | 1604 void Assembler::ext_(Register rt, Register rs, uint16_t pos, uint16_t size) { |
1605 // Should be called via MacroAssembler::Ext. | 1605 // Should be called via MacroAssembler::Ext. |
1606 // Ext instr has 'rt' field as dest, and two uint5: msb, lsb. | 1606 // Ext instr has 'rt' field as dest, and two uint5: msb, lsb. |
1607 ASSERT(kArchVariant == kMips32r2); | 1607 DCHECK(kArchVariant == kMips32r2); |
1608 GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos, EXT); | 1608 GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos, EXT); |
1609 } | 1609 } |
1610 | 1610 |
1611 | 1611 |
1612 void Assembler::pref(int32_t hint, const MemOperand& rs) { | 1612 void Assembler::pref(int32_t hint, const MemOperand& rs) { |
1613 ASSERT(kArchVariant != kLoongson); | 1613 DCHECK(kArchVariant != kLoongson); |
1614 ASSERT(is_uint5(hint) && is_uint16(rs.offset_)); | 1614 DCHECK(is_uint5(hint) && is_uint16(rs.offset_)); |
1615 Instr instr = PREF | (rs.rm().code() << kRsShift) | (hint << kRtShift) | 1615 Instr instr = PREF | (rs.rm().code() << kRsShift) | (hint << kRtShift) |
1616 | (rs.offset_); | 1616 | (rs.offset_); |
1617 emit(instr); | 1617 emit(instr); |
1618 } | 1618 } |
1619 | 1619 |
1620 | 1620 |
1621 // --------Coprocessor-instructions---------------- | 1621 // --------Coprocessor-instructions---------------- |
1622 | 1622 |
1623 // Load, store, move. | 1623 // Load, store, move. |
1624 void Assembler::lwc1(FPURegister fd, const MemOperand& src) { | 1624 void Assembler::lwc1(FPURegister fd, const MemOperand& src) { |
(...skipping 153 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1778 GenInstrRegister(COP1, S, f0, fs, fd, CEIL_W_S); | 1778 GenInstrRegister(COP1, S, f0, fs, fd, CEIL_W_S); |
1779 } | 1779 } |
1780 | 1780 |
1781 | 1781 |
1782 void Assembler::ceil_w_d(FPURegister fd, FPURegister fs) { | 1782 void Assembler::ceil_w_d(FPURegister fd, FPURegister fs) { |
1783 GenInstrRegister(COP1, D, f0, fs, fd, CEIL_W_D); | 1783 GenInstrRegister(COP1, D, f0, fs, fd, CEIL_W_D); |
1784 } | 1784 } |
1785 | 1785 |
1786 | 1786 |
1787 void Assembler::cvt_l_s(FPURegister fd, FPURegister fs) { | 1787 void Assembler::cvt_l_s(FPURegister fd, FPURegister fs) { |
1788 ASSERT(kArchVariant == kMips32r2); | 1788 DCHECK(kArchVariant == kMips32r2); |
1789 GenInstrRegister(COP1, S, f0, fs, fd, CVT_L_S); | 1789 GenInstrRegister(COP1, S, f0, fs, fd, CVT_L_S); |
1790 } | 1790 } |
1791 | 1791 |
1792 | 1792 |
1793 void Assembler::cvt_l_d(FPURegister fd, FPURegister fs) { | 1793 void Assembler::cvt_l_d(FPURegister fd, FPURegister fs) { |
1794 ASSERT(kArchVariant == kMips32r2); | 1794 DCHECK(kArchVariant == kMips32r2); |
1795 GenInstrRegister(COP1, D, f0, fs, fd, CVT_L_D); | 1795 GenInstrRegister(COP1, D, f0, fs, fd, CVT_L_D); |
1796 } | 1796 } |
1797 | 1797 |
1798 | 1798 |
1799 void Assembler::trunc_l_s(FPURegister fd, FPURegister fs) { | 1799 void Assembler::trunc_l_s(FPURegister fd, FPURegister fs) { |
1800 ASSERT(kArchVariant == kMips32r2); | 1800 DCHECK(kArchVariant == kMips32r2); |
1801 GenInstrRegister(COP1, S, f0, fs, fd, TRUNC_L_S); | 1801 GenInstrRegister(COP1, S, f0, fs, fd, TRUNC_L_S); |
1802 } | 1802 } |
1803 | 1803 |
1804 | 1804 |
1805 void Assembler::trunc_l_d(FPURegister fd, FPURegister fs) { | 1805 void Assembler::trunc_l_d(FPURegister fd, FPURegister fs) { |
1806 ASSERT(kArchVariant == kMips32r2); | 1806 DCHECK(kArchVariant == kMips32r2); |
1807 GenInstrRegister(COP1, D, f0, fs, fd, TRUNC_L_D); | 1807 GenInstrRegister(COP1, D, f0, fs, fd, TRUNC_L_D); |
1808 } | 1808 } |
1809 | 1809 |
1810 | 1810 |
1811 void Assembler::round_l_s(FPURegister fd, FPURegister fs) { | 1811 void Assembler::round_l_s(FPURegister fd, FPURegister fs) { |
1812 GenInstrRegister(COP1, S, f0, fs, fd, ROUND_L_S); | 1812 GenInstrRegister(COP1, S, f0, fs, fd, ROUND_L_S); |
1813 } | 1813 } |
1814 | 1814 |
1815 | 1815 |
1816 void Assembler::round_l_d(FPURegister fd, FPURegister fs) { | 1816 void Assembler::round_l_d(FPURegister fd, FPURegister fs) { |
(...skipping 20 matching lines...) Expand all Loading... |
1837 GenInstrRegister(COP1, D, f0, fs, fd, CEIL_L_D); | 1837 GenInstrRegister(COP1, D, f0, fs, fd, CEIL_L_D); |
1838 } | 1838 } |
1839 | 1839 |
1840 | 1840 |
1841 void Assembler::cvt_s_w(FPURegister fd, FPURegister fs) { | 1841 void Assembler::cvt_s_w(FPURegister fd, FPURegister fs) { |
1842 GenInstrRegister(COP1, W, f0, fs, fd, CVT_S_W); | 1842 GenInstrRegister(COP1, W, f0, fs, fd, CVT_S_W); |
1843 } | 1843 } |
1844 | 1844 |
1845 | 1845 |
1846 void Assembler::cvt_s_l(FPURegister fd, FPURegister fs) { | 1846 void Assembler::cvt_s_l(FPURegister fd, FPURegister fs) { |
1847 ASSERT(kArchVariant == kMips32r2); | 1847 DCHECK(kArchVariant == kMips32r2); |
1848 GenInstrRegister(COP1, L, f0, fs, fd, CVT_S_L); | 1848 GenInstrRegister(COP1, L, f0, fs, fd, CVT_S_L); |
1849 } | 1849 } |
1850 | 1850 |
1851 | 1851 |
1852 void Assembler::cvt_s_d(FPURegister fd, FPURegister fs) { | 1852 void Assembler::cvt_s_d(FPURegister fd, FPURegister fs) { |
1853 GenInstrRegister(COP1, D, f0, fs, fd, CVT_S_D); | 1853 GenInstrRegister(COP1, D, f0, fs, fd, CVT_S_D); |
1854 } | 1854 } |
1855 | 1855 |
1856 | 1856 |
1857 void Assembler::cvt_d_w(FPURegister fd, FPURegister fs) { | 1857 void Assembler::cvt_d_w(FPURegister fd, FPURegister fs) { |
1858 GenInstrRegister(COP1, W, f0, fs, fd, CVT_D_W); | 1858 GenInstrRegister(COP1, W, f0, fs, fd, CVT_D_W); |
1859 } | 1859 } |
1860 | 1860 |
1861 | 1861 |
1862 void Assembler::cvt_d_l(FPURegister fd, FPURegister fs) { | 1862 void Assembler::cvt_d_l(FPURegister fd, FPURegister fs) { |
1863 ASSERT(kArchVariant == kMips32r2); | 1863 DCHECK(kArchVariant == kMips32r2); |
1864 GenInstrRegister(COP1, L, f0, fs, fd, CVT_D_L); | 1864 GenInstrRegister(COP1, L, f0, fs, fd, CVT_D_L); |
1865 } | 1865 } |
1866 | 1866 |
1867 | 1867 |
1868 void Assembler::cvt_d_s(FPURegister fd, FPURegister fs) { | 1868 void Assembler::cvt_d_s(FPURegister fd, FPURegister fs) { |
1869 GenInstrRegister(COP1, S, f0, fs, fd, CVT_D_S); | 1869 GenInstrRegister(COP1, S, f0, fs, fd, CVT_D_S); |
1870 } | 1870 } |
1871 | 1871 |
1872 | 1872 |
1873 // Conditions. | 1873 // Conditions. |
1874 void Assembler::c(FPUCondition cond, SecondaryField fmt, | 1874 void Assembler::c(FPUCondition cond, SecondaryField fmt, |
1875 FPURegister fs, FPURegister ft, uint16_t cc) { | 1875 FPURegister fs, FPURegister ft, uint16_t cc) { |
1876 ASSERT(is_uint3(cc)); | 1876 DCHECK(is_uint3(cc)); |
1877 ASSERT((fmt & ~(31 << kRsShift)) == 0); | 1877 DCHECK((fmt & ~(31 << kRsShift)) == 0); |
1878 Instr instr = COP1 | fmt | ft.code() << 16 | fs.code() << kFsShift | 1878 Instr instr = COP1 | fmt | ft.code() << 16 | fs.code() << kFsShift |
1879 | cc << 8 | 3 << 4 | cond; | 1879 | cc << 8 | 3 << 4 | cond; |
1880 emit(instr); | 1880 emit(instr); |
1881 } | 1881 } |
1882 | 1882 |
1883 | 1883 |
1884 void Assembler::fcmp(FPURegister src1, const double src2, | 1884 void Assembler::fcmp(FPURegister src1, const double src2, |
1885 FPUCondition cond) { | 1885 FPUCondition cond) { |
1886 ASSERT(src2 == 0.0); | 1886 DCHECK(src2 == 0.0); |
1887 mtc1(zero_reg, f14); | 1887 mtc1(zero_reg, f14); |
1888 cvt_d_w(f14, f14); | 1888 cvt_d_w(f14, f14); |
1889 c(cond, D, src1, f14, 0); | 1889 c(cond, D, src1, f14, 0); |
1890 } | 1890 } |
1891 | 1891 |
1892 | 1892 |
1893 void Assembler::bc1f(int16_t offset, uint16_t cc) { | 1893 void Assembler::bc1f(int16_t offset, uint16_t cc) { |
1894 ASSERT(is_uint3(cc)); | 1894 DCHECK(is_uint3(cc)); |
1895 Instr instr = COP1 | BC1 | cc << 18 | 0 << 16 | (offset & kImm16Mask); | 1895 Instr instr = COP1 | BC1 | cc << 18 | 0 << 16 | (offset & kImm16Mask); |
1896 emit(instr); | 1896 emit(instr); |
1897 } | 1897 } |
1898 | 1898 |
1899 | 1899 |
1900 void Assembler::bc1t(int16_t offset, uint16_t cc) { | 1900 void Assembler::bc1t(int16_t offset, uint16_t cc) { |
1901 ASSERT(is_uint3(cc)); | 1901 DCHECK(is_uint3(cc)); |
1902 Instr instr = COP1 | BC1 | cc << 18 | 1 << 16 | (offset & kImm16Mask); | 1902 Instr instr = COP1 | BC1 | cc << 18 | 1 << 16 | (offset & kImm16Mask); |
1903 emit(instr); | 1903 emit(instr); |
1904 } | 1904 } |
1905 | 1905 |
1906 | 1906 |
1907 // Debugging. | 1907 // Debugging. |
1908 void Assembler::RecordJSReturn() { | 1908 void Assembler::RecordJSReturn() { |
1909 positions_recorder()->WriteRecordedPositions(); | 1909 positions_recorder()->WriteRecordedPositions(); |
1910 CheckBuffer(); | 1910 CheckBuffer(); |
1911 RecordRelocInfo(RelocInfo::JS_RETURN); | 1911 RecordRelocInfo(RelocInfo::JS_RETURN); |
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1922 void Assembler::RecordComment(const char* msg) { | 1922 void Assembler::RecordComment(const char* msg) { |
1923 if (FLAG_code_comments) { | 1923 if (FLAG_code_comments) { |
1924 CheckBuffer(); | 1924 CheckBuffer(); |
1925 RecordRelocInfo(RelocInfo::COMMENT, reinterpret_cast<intptr_t>(msg)); | 1925 RecordRelocInfo(RelocInfo::COMMENT, reinterpret_cast<intptr_t>(msg)); |
1926 } | 1926 } |
1927 } | 1927 } |
1928 | 1928 |
1929 | 1929 |
1930 int Assembler::RelocateInternalReference(byte* pc, intptr_t pc_delta) { | 1930 int Assembler::RelocateInternalReference(byte* pc, intptr_t pc_delta) { |
1931 Instr instr = instr_at(pc); | 1931 Instr instr = instr_at(pc); |
1932 ASSERT(IsJ(instr) || IsLui(instr)); | 1932 DCHECK(IsJ(instr) || IsLui(instr)); |
1933 if (IsLui(instr)) { | 1933 if (IsLui(instr)) { |
1934 Instr instr_lui = instr_at(pc + 0 * Assembler::kInstrSize); | 1934 Instr instr_lui = instr_at(pc + 0 * Assembler::kInstrSize); |
1935 Instr instr_ori = instr_at(pc + 1 * Assembler::kInstrSize); | 1935 Instr instr_ori = instr_at(pc + 1 * Assembler::kInstrSize); |
1936 ASSERT(IsOri(instr_ori)); | 1936 DCHECK(IsOri(instr_ori)); |
1937 int32_t imm = (instr_lui & static_cast<int32_t>(kImm16Mask)) << kLuiShift; | 1937 int32_t imm = (instr_lui & static_cast<int32_t>(kImm16Mask)) << kLuiShift; |
1938 imm |= (instr_ori & static_cast<int32_t>(kImm16Mask)); | 1938 imm |= (instr_ori & static_cast<int32_t>(kImm16Mask)); |
1939 if (imm == kEndOfJumpChain) { | 1939 if (imm == kEndOfJumpChain) { |
1940 return 0; // Number of instructions patched. | 1940 return 0; // Number of instructions patched. |
1941 } | 1941 } |
1942 imm += pc_delta; | 1942 imm += pc_delta; |
1943 ASSERT((imm & 3) == 0); | 1943 DCHECK((imm & 3) == 0); |
1944 | 1944 |
1945 instr_lui &= ~kImm16Mask; | 1945 instr_lui &= ~kImm16Mask; |
1946 instr_ori &= ~kImm16Mask; | 1946 instr_ori &= ~kImm16Mask; |
1947 | 1947 |
1948 instr_at_put(pc + 0 * Assembler::kInstrSize, | 1948 instr_at_put(pc + 0 * Assembler::kInstrSize, |
1949 instr_lui | ((imm >> kLuiShift) & kImm16Mask)); | 1949 instr_lui | ((imm >> kLuiShift) & kImm16Mask)); |
1950 instr_at_put(pc + 1 * Assembler::kInstrSize, | 1950 instr_at_put(pc + 1 * Assembler::kInstrSize, |
1951 instr_ori | (imm & kImm16Mask)); | 1951 instr_ori | (imm & kImm16Mask)); |
1952 return 2; // Number of instructions patched. | 1952 return 2; // Number of instructions patched. |
1953 } else { | 1953 } else { |
1954 uint32_t imm28 = (instr & static_cast<int32_t>(kImm26Mask)) << 2; | 1954 uint32_t imm28 = (instr & static_cast<int32_t>(kImm26Mask)) << 2; |
1955 if (static_cast<int32_t>(imm28) == kEndOfJumpChain) { | 1955 if (static_cast<int32_t>(imm28) == kEndOfJumpChain) { |
1956 return 0; // Number of instructions patched. | 1956 return 0; // Number of instructions patched. |
1957 } | 1957 } |
1958 imm28 += pc_delta; | 1958 imm28 += pc_delta; |
1959 imm28 &= kImm28Mask; | 1959 imm28 &= kImm28Mask; |
1960 ASSERT((imm28 & 3) == 0); | 1960 DCHECK((imm28 & 3) == 0); |
1961 | 1961 |
1962 instr &= ~kImm26Mask; | 1962 instr &= ~kImm26Mask; |
1963 uint32_t imm26 = imm28 >> 2; | 1963 uint32_t imm26 = imm28 >> 2; |
1964 ASSERT(is_uint26(imm26)); | 1964 DCHECK(is_uint26(imm26)); |
1965 | 1965 |
1966 instr_at_put(pc, instr | (imm26 & kImm26Mask)); | 1966 instr_at_put(pc, instr | (imm26 & kImm26Mask)); |
1967 return 1; // Number of instructions patched. | 1967 return 1; // Number of instructions patched. |
1968 } | 1968 } |
1969 } | 1969 } |
1970 | 1970 |
1971 | 1971 |
1972 void Assembler::GrowBuffer() { | 1972 void Assembler::GrowBuffer() { |
1973 if (!own_buffer_) FATAL("external code buffer is too small"); | 1973 if (!own_buffer_) FATAL("external code buffer is too small"); |
1974 | 1974 |
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2006 | 2006 |
2007 // Relocate runtime entries. | 2007 // Relocate runtime entries. |
2008 for (RelocIterator it(desc); !it.done(); it.next()) { | 2008 for (RelocIterator it(desc); !it.done(); it.next()) { |
2009 RelocInfo::Mode rmode = it.rinfo()->rmode(); | 2009 RelocInfo::Mode rmode = it.rinfo()->rmode(); |
2010 if (rmode == RelocInfo::INTERNAL_REFERENCE) { | 2010 if (rmode == RelocInfo::INTERNAL_REFERENCE) { |
2011 byte* p = reinterpret_cast<byte*>(it.rinfo()->pc()); | 2011 byte* p = reinterpret_cast<byte*>(it.rinfo()->pc()); |
2012 RelocateInternalReference(p, pc_delta); | 2012 RelocateInternalReference(p, pc_delta); |
2013 } | 2013 } |
2014 } | 2014 } |
2015 | 2015 |
2016 ASSERT(!overflow()); | 2016 DCHECK(!overflow()); |
2017 } | 2017 } |
2018 | 2018 |
2019 | 2019 |
2020 void Assembler::db(uint8_t data) { | 2020 void Assembler::db(uint8_t data) { |
2021 CheckBuffer(); | 2021 CheckBuffer(); |
2022 *reinterpret_cast<uint8_t*>(pc_) = data; | 2022 *reinterpret_cast<uint8_t*>(pc_) = data; |
2023 pc_ += sizeof(uint8_t); | 2023 pc_ += sizeof(uint8_t); |
2024 } | 2024 } |
2025 | 2025 |
2026 | 2026 |
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2037 reinterpret_cast<uint32_t>(stub->instruction_start()); | 2037 reinterpret_cast<uint32_t>(stub->instruction_start()); |
2038 pc_ += sizeof(uint32_t); | 2038 pc_ += sizeof(uint32_t); |
2039 } | 2039 } |
2040 | 2040 |
2041 | 2041 |
2042 void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) { | 2042 void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) { |
2043 // We do not try to reuse pool constants. | 2043 // We do not try to reuse pool constants. |
2044 RelocInfo rinfo(pc_, rmode, data, NULL); | 2044 RelocInfo rinfo(pc_, rmode, data, NULL); |
2045 if (rmode >= RelocInfo::JS_RETURN && rmode <= RelocInfo::DEBUG_BREAK_SLOT) { | 2045 if (rmode >= RelocInfo::JS_RETURN && rmode <= RelocInfo::DEBUG_BREAK_SLOT) { |
2046 // Adjust code for new modes. | 2046 // Adjust code for new modes. |
2047 ASSERT(RelocInfo::IsDebugBreakSlot(rmode) | 2047 DCHECK(RelocInfo::IsDebugBreakSlot(rmode) |
2048 || RelocInfo::IsJSReturn(rmode) | 2048 || RelocInfo::IsJSReturn(rmode) |
2049 || RelocInfo::IsComment(rmode) | 2049 || RelocInfo::IsComment(rmode) |
2050 || RelocInfo::IsPosition(rmode)); | 2050 || RelocInfo::IsPosition(rmode)); |
2051 // These modes do not need an entry in the constant pool. | 2051 // These modes do not need an entry in the constant pool. |
2052 } | 2052 } |
2053 if (!RelocInfo::IsNone(rinfo.rmode())) { | 2053 if (!RelocInfo::IsNone(rinfo.rmode())) { |
2054 // Don't record external references unless the heap will be serialized. | 2054 // Don't record external references unless the heap will be serialized. |
2055 if (rmode == RelocInfo::EXTERNAL_REFERENCE && | 2055 if (rmode == RelocInfo::EXTERNAL_REFERENCE && |
2056 !serializer_enabled() && !emit_debug_code()) { | 2056 !serializer_enabled() && !emit_debug_code()) { |
2057 return; | 2057 return; |
2058 } | 2058 } |
2059 ASSERT(buffer_space() >= kMaxRelocSize); // Too late to grow buffer here. | 2059 DCHECK(buffer_space() >= kMaxRelocSize); // Too late to grow buffer here. |
2060 if (rmode == RelocInfo::CODE_TARGET_WITH_ID) { | 2060 if (rmode == RelocInfo::CODE_TARGET_WITH_ID) { |
2061 RelocInfo reloc_info_with_ast_id(pc_, | 2061 RelocInfo reloc_info_with_ast_id(pc_, |
2062 rmode, | 2062 rmode, |
2063 RecordedAstId().ToInt(), | 2063 RecordedAstId().ToInt(), |
2064 NULL); | 2064 NULL); |
2065 ClearRecordedAstId(); | 2065 ClearRecordedAstId(); |
2066 reloc_info_writer.Write(&reloc_info_with_ast_id); | 2066 reloc_info_writer.Write(&reloc_info_with_ast_id); |
2067 } else { | 2067 } else { |
2068 reloc_info_writer.Write(&rinfo); | 2068 reloc_info_writer.Write(&rinfo); |
2069 } | 2069 } |
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2087 // Emission is currently blocked; make sure we try again as soon as | 2087 // Emission is currently blocked; make sure we try again as soon as |
2088 // possible. | 2088 // possible. |
2089 if (trampoline_pool_blocked_nesting_ > 0) { | 2089 if (trampoline_pool_blocked_nesting_ > 0) { |
2090 next_buffer_check_ = pc_offset() + kInstrSize; | 2090 next_buffer_check_ = pc_offset() + kInstrSize; |
2091 } else { | 2091 } else { |
2092 next_buffer_check_ = no_trampoline_pool_before_; | 2092 next_buffer_check_ = no_trampoline_pool_before_; |
2093 } | 2093 } |
2094 return; | 2094 return; |
2095 } | 2095 } |
2096 | 2096 |
2097 ASSERT(!trampoline_emitted_); | 2097 DCHECK(!trampoline_emitted_); |
2098 ASSERT(unbound_labels_count_ >= 0); | 2098 DCHECK(unbound_labels_count_ >= 0); |
2099 if (unbound_labels_count_ > 0) { | 2099 if (unbound_labels_count_ > 0) { |
2100 // First we emit jump (2 instructions), then we emit trampoline pool. | 2100 // First we emit jump (2 instructions), then we emit trampoline pool. |
2101 { BlockTrampolinePoolScope block_trampoline_pool(this); | 2101 { BlockTrampolinePoolScope block_trampoline_pool(this); |
2102 Label after_pool; | 2102 Label after_pool; |
2103 b(&after_pool); | 2103 b(&after_pool); |
2104 nop(); | 2104 nop(); |
2105 | 2105 |
2106 int pool_start = pc_offset(); | 2106 int pool_start = pc_offset(); |
2107 for (int i = 0; i < unbound_labels_count_; i++) { | 2107 for (int i = 0; i < unbound_labels_count_; i++) { |
2108 uint32_t imm32; | 2108 uint32_t imm32; |
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2275 // Jump to label may follow at pc + 2 * kInstrSize. | 2275 // Jump to label may follow at pc + 2 * kInstrSize. |
2276 uint32_t* p = reinterpret_cast<uint32_t*>(pc); | 2276 uint32_t* p = reinterpret_cast<uint32_t*>(pc); |
2277 #ifdef DEBUG | 2277 #ifdef DEBUG |
2278 Instr instr1 = instr_at(pc); | 2278 Instr instr1 = instr_at(pc); |
2279 #endif | 2279 #endif |
2280 Instr instr2 = instr_at(pc + 1 * kInstrSize); | 2280 Instr instr2 = instr_at(pc + 1 * kInstrSize); |
2281 Instr instr3 = instr_at(pc + 2 * kInstrSize); | 2281 Instr instr3 = instr_at(pc + 2 * kInstrSize); |
2282 bool patched = false; | 2282 bool patched = false; |
2283 | 2283 |
2284 if (IsJal(instr3)) { | 2284 if (IsJal(instr3)) { |
2285 ASSERT(GetOpcodeField(instr1) == LUI); | 2285 DCHECK(GetOpcodeField(instr1) == LUI); |
2286 ASSERT(GetOpcodeField(instr2) == ORI); | 2286 DCHECK(GetOpcodeField(instr2) == ORI); |
2287 | 2287 |
2288 uint32_t rs_field = GetRt(instr2) << kRsShift; | 2288 uint32_t rs_field = GetRt(instr2) << kRsShift; |
2289 uint32_t rd_field = ra.code() << kRdShift; // Return-address (ra) reg. | 2289 uint32_t rd_field = ra.code() << kRdShift; // Return-address (ra) reg. |
2290 *(p+2) = SPECIAL | rs_field | rd_field | JALR; | 2290 *(p+2) = SPECIAL | rs_field | rd_field | JALR; |
2291 patched = true; | 2291 patched = true; |
2292 } else if (IsJ(instr3)) { | 2292 } else if (IsJ(instr3)) { |
2293 ASSERT(GetOpcodeField(instr1) == LUI); | 2293 DCHECK(GetOpcodeField(instr1) == LUI); |
2294 ASSERT(GetOpcodeField(instr2) == ORI); | 2294 DCHECK(GetOpcodeField(instr2) == ORI); |
2295 | 2295 |
2296 uint32_t rs_field = GetRt(instr2) << kRsShift; | 2296 uint32_t rs_field = GetRt(instr2) << kRsShift; |
2297 *(p+2) = SPECIAL | rs_field | JR; | 2297 *(p+2) = SPECIAL | rs_field | JR; |
2298 patched = true; | 2298 patched = true; |
2299 } | 2299 } |
2300 | 2300 |
2301 if (patched) { | 2301 if (patched) { |
2302 CpuFeatures::FlushICache(pc+2, sizeof(Address)); | 2302 CpuFeatures::FlushICache(pc+2, sizeof(Address)); |
2303 } | 2303 } |
2304 } | 2304 } |
2305 | 2305 |
2306 | 2306 |
2307 Handle<ConstantPoolArray> Assembler::NewConstantPool(Isolate* isolate) { | 2307 Handle<ConstantPoolArray> Assembler::NewConstantPool(Isolate* isolate) { |
2308 // No out-of-line constant pool support. | 2308 // No out-of-line constant pool support. |
2309 ASSERT(!FLAG_enable_ool_constant_pool); | 2309 DCHECK(!FLAG_enable_ool_constant_pool); |
2310 return isolate->factory()->empty_constant_pool_array(); | 2310 return isolate->factory()->empty_constant_pool_array(); |
2311 } | 2311 } |
2312 | 2312 |
2313 | 2313 |
2314 void Assembler::PopulateConstantPool(ConstantPoolArray* constant_pool) { | 2314 void Assembler::PopulateConstantPool(ConstantPoolArray* constant_pool) { |
2315 // No out-of-line constant pool support. | 2315 // No out-of-line constant pool support. |
2316 ASSERT(!FLAG_enable_ool_constant_pool); | 2316 DCHECK(!FLAG_enable_ool_constant_pool); |
2317 return; | 2317 return; |
2318 } | 2318 } |
2319 | 2319 |
2320 | 2320 |
2321 } } // namespace v8::internal | 2321 } } // namespace v8::internal |
2322 | 2322 |
2323 #endif // V8_TARGET_ARCH_MIPS | 2323 #endif // V8_TARGET_ARCH_MIPS |
OLD | NEW |