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Unified Diff: src/arm64/simulator-arm64.cc

Issue 430503007: Rename ASSERT* to DCHECK*. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: REBASE and fixes Created 6 years, 4 months ago
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Index: src/arm64/simulator-arm64.cc
diff --git a/src/arm64/simulator-arm64.cc b/src/arm64/simulator-arm64.cc
index 0d2ba3a2978f0790f3cdcc1ac98b627cda1d8c6c..8268342e0cb1092ae3b5d1456b26f3aea1201fcd 100644
--- a/src/arm64/simulator-arm64.cc
+++ b/src/arm64/simulator-arm64.cc
@@ -73,11 +73,11 @@ const Instruction* Simulator::kEndOfSimAddress = NULL;
void SimSystemRegister::SetBits(int msb, int lsb, uint32_t bits) {
int width = msb - lsb + 1;
- ASSERT(is_uintn(bits, width) || is_intn(bits, width));
+ DCHECK(is_uintn(bits, width) || is_intn(bits, width));
bits <<= lsb;
uint32_t mask = ((1 << width) - 1) << lsb;
- ASSERT((mask & write_ignore_mask_) == 0);
+ DCHECK((mask & write_ignore_mask_) == 0);
value_ = (value_ & ~mask) | (bits & mask);
}
@@ -107,7 +107,7 @@ void Simulator::Initialize(Isolate* isolate) {
Simulator* Simulator::current(Isolate* isolate) {
Isolate::PerIsolateThreadData* isolate_data =
isolate->FindOrAllocatePerThreadDataForThisThread();
- ASSERT(isolate_data != NULL);
+ DCHECK(isolate_data != NULL);
Simulator* sim = isolate_data->simulator();
if (sim == NULL) {
@@ -135,7 +135,7 @@ void Simulator::CallVoid(byte* entry, CallArgument* args) {
} else if (arg.IsD() && (index_d < 8)) {
set_dreg_bits(index_d++, arg.bits());
} else {
- ASSERT(arg.IsD() || arg.IsX());
+ DCHECK(arg.IsD() || arg.IsX());
stack_args.push_back(arg.bits());
}
}
@@ -154,7 +154,7 @@ void Simulator::CallVoid(byte* entry, CallArgument* args) {
stack += sizeof(*it);
}
- ASSERT(reinterpret_cast<uintptr_t>(stack) <= original_stack);
+ DCHECK(reinterpret_cast<uintptr_t>(stack) <= original_stack);
set_sp(entry_stack);
// Call the generated code.
@@ -256,7 +256,7 @@ void Simulator::CheckPCSComplianceAndRun() {
CHECK_EQ(saved_registers[i], xreg(register_list.PopLowestIndex().code()));
}
for (int i = 0; i < kNumberOfCalleeSavedFPRegisters; i++) {
- ASSERT(saved_fpregisters[i] ==
+ DCHECK(saved_fpregisters[i] ==
dreg_bits(fpregister_list.PopLowestIndex().code()));
}
@@ -289,7 +289,7 @@ void Simulator::CorruptRegisters(CPURegList* list, uint64_t value) {
set_xreg(code, value | code);
}
} else {
- ASSERT(list->type() == CPURegister::kFPRegister);
+ DCHECK(list->type() == CPURegister::kFPRegister);
while (!list->IsEmpty()) {
unsigned code = list->PopLowestIndex().code();
set_dreg_bits(code, value | code);
@@ -311,7 +311,7 @@ void Simulator::CorruptAllCallerSavedCPURegisters() {
// Extending the stack by 2 * 64 bits is required for stack alignment purposes.
uintptr_t Simulator::PushAddress(uintptr_t address) {
- ASSERT(sizeof(uintptr_t) < 2 * kXRegSize);
+ DCHECK(sizeof(uintptr_t) < 2 * kXRegSize);
intptr_t new_sp = sp() - 2 * kXRegSize;
uintptr_t* alignment_slot =
reinterpret_cast<uintptr_t*>(new_sp + kXRegSize);
@@ -327,7 +327,7 @@ uintptr_t Simulator::PopAddress() {
intptr_t current_sp = sp();
uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(current_sp);
uintptr_t address = *stack_slot;
- ASSERT(sizeof(uintptr_t) < 2 * kXRegSize);
+ DCHECK(sizeof(uintptr_t) < 2 * kXRegSize);
set_sp(current_sp + 2 * kXRegSize);
return address;
}
@@ -481,7 +481,7 @@ class Redirection {
Redirection* current = isolate->simulator_redirection();
for (; current != NULL; current = current->next_) {
if (current->external_function_ == external_function) {
- ASSERT_EQ(current->type(), type);
+ DCHECK_EQ(current->type(), type);
return current;
}
}
@@ -765,7 +765,7 @@ const char* Simulator::vreg_names[] = {
const char* Simulator::WRegNameForCode(unsigned code, Reg31Mode mode) {
- ASSERT(code < kNumberOfRegisters);
+ DCHECK(code < kNumberOfRegisters);
// If the code represents the stack pointer, index the name after zr.
if ((code == kZeroRegCode) && (mode == Reg31IsStackPointer)) {
code = kZeroRegCode + 1;
@@ -775,7 +775,7 @@ const char* Simulator::WRegNameForCode(unsigned code, Reg31Mode mode) {
const char* Simulator::XRegNameForCode(unsigned code, Reg31Mode mode) {
- ASSERT(code < kNumberOfRegisters);
+ DCHECK(code < kNumberOfRegisters);
// If the code represents the stack pointer, index the name after zr.
if ((code == kZeroRegCode) && (mode == Reg31IsStackPointer)) {
code = kZeroRegCode + 1;
@@ -785,19 +785,19 @@ const char* Simulator::XRegNameForCode(unsigned code, Reg31Mode mode) {
const char* Simulator::SRegNameForCode(unsigned code) {
- ASSERT(code < kNumberOfFPRegisters);
+ DCHECK(code < kNumberOfFPRegisters);
return sreg_names[code];
}
const char* Simulator::DRegNameForCode(unsigned code) {
- ASSERT(code < kNumberOfFPRegisters);
+ DCHECK(code < kNumberOfFPRegisters);
return dreg_names[code];
}
const char* Simulator::VRegNameForCode(unsigned code) {
- ASSERT(code < kNumberOfFPRegisters);
+ DCHECK(code < kNumberOfFPRegisters);
return vreg_names[code];
}
@@ -830,7 +830,7 @@ T Simulator::AddWithCarry(bool set_flags,
T src2,
T carry_in) {
typedef typename make_unsigned<T>::type unsignedT;
- ASSERT((carry_in == 0) || (carry_in == 1));
+ DCHECK((carry_in == 0) || (carry_in == 1));
T signed_sum = src1 + src2 + carry_in;
T result = signed_sum;
@@ -1065,7 +1065,7 @@ void Simulator::PrintSystemRegisters(bool print_all) {
"0b10 (Round towards Minus Infinity)",
"0b11 (Round towards Zero)"
};
- ASSERT(fpcr().RMode() <= (sizeof(rmode) / sizeof(rmode[0])));
+ DCHECK(fpcr().RMode() <= (sizeof(rmode) / sizeof(rmode[0])));
fprintf(stream_, "# %sFPCR: %sAHP:%d DN:%d FZ:%d RMode:%s%s\n",
clr_flag_name,
clr_flag_value,
@@ -1205,7 +1205,7 @@ void Simulator::VisitUnconditionalBranch(Instruction* instr) {
void Simulator::VisitConditionalBranch(Instruction* instr) {
- ASSERT(instr->Mask(ConditionalBranchMask) == B_cond);
+ DCHECK(instr->Mask(ConditionalBranchMask) == B_cond);
if (ConditionPassed(static_cast<Condition>(instr->ConditionBranch()))) {
set_pc(instr->ImmPCOffsetTarget());
}
@@ -1418,7 +1418,7 @@ void Simulator::ConditionalCompareHelper(Instruction* instr, T op2) {
if (instr->Mask(ConditionalCompareMask) == CCMP) {
AddWithCarry<T>(true, op1, ~op2, 1);
} else {
- ASSERT(instr->Mask(ConditionalCompareMask) == CCMN);
+ DCHECK(instr->Mask(ConditionalCompareMask) == CCMN);
AddWithCarry<T>(true, op1, op2, 0);
}
} else {
@@ -1451,7 +1451,7 @@ void Simulator::VisitLoadStorePostIndex(Instruction* instr) {
void Simulator::VisitLoadStoreRegisterOffset(Instruction* instr) {
Extend ext = static_cast<Extend>(instr->ExtendMode());
- ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX));
+ DCHECK((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX));
unsigned shift_amount = instr->ImmShiftLS() * instr->SizeLS();
int64_t offset = ExtendValue(xreg(instr->Rm()), ext, shift_amount);
@@ -1586,7 +1586,7 @@ void Simulator::LoadStorePairHelper(Instruction* instr,
static_cast<LoadStorePairOp>(instr->Mask(LoadStorePairMask));
// 'rt' and 'rt2' can only be aliased for stores.
- ASSERT(((op & LoadStorePairLBit) == 0) || (rt != rt2));
+ DCHECK(((op & LoadStorePairLBit) == 0) || (rt != rt2));
switch (op) {
case LDP_w: {
@@ -1694,7 +1694,7 @@ void Simulator::LoadStoreWriteBack(unsigned addr_reg,
int64_t offset,
AddrMode addrmode) {
if ((addrmode == PreIndex) || (addrmode == PostIndex)) {
- ASSERT(offset != 0);
+ DCHECK(offset != 0);
uint64_t address = xreg(addr_reg, Reg31IsStackPointer);
set_reg(addr_reg, address + offset, Reg31IsStackPointer);
}
@@ -1714,8 +1714,8 @@ void Simulator::CheckMemoryAccess(uint8_t* address, uint8_t* stack) {
uint64_t Simulator::MemoryRead(uint8_t* address, unsigned num_bytes) {
- ASSERT(address != NULL);
- ASSERT((num_bytes > 0) && (num_bytes <= sizeof(uint64_t)));
+ DCHECK(address != NULL);
+ DCHECK((num_bytes > 0) && (num_bytes <= sizeof(uint64_t)));
uint64_t read = 0;
memcpy(&read, address, num_bytes);
return read;
@@ -1755,8 +1755,8 @@ double Simulator::MemoryReadFP64(uint8_t* address) {
void Simulator::MemoryWrite(uint8_t* address,
uint64_t value,
unsigned num_bytes) {
- ASSERT(address != NULL);
- ASSERT((num_bytes > 0) && (num_bytes <= sizeof(uint64_t)));
+ DCHECK(address != NULL);
+ DCHECK((num_bytes > 0) && (num_bytes <= sizeof(uint64_t)));
LogWrite(address, value, num_bytes);
memcpy(address, &value, num_bytes);
@@ -1790,7 +1790,7 @@ void Simulator::VisitMoveWideImmediate(Instruction* instr) {
bool is_64_bits = instr->SixtyFourBits() == 1;
// Shift is limited for W operations.
- ASSERT(is_64_bits || (instr->ShiftMoveWide() < 2));
+ DCHECK(is_64_bits || (instr->ShiftMoveWide() < 2));
// Get the shifted immediate.
int64_t shift = instr->ShiftMoveWide() * 16;
@@ -1880,7 +1880,7 @@ void Simulator::VisitDataProcessing1Source(Instruction* instr) {
uint64_t Simulator::ReverseBits(uint64_t value, unsigned num_bits) {
- ASSERT((num_bits == kWRegSizeInBits) || (num_bits == kXRegSizeInBits));
+ DCHECK((num_bits == kWRegSizeInBits) || (num_bits == kXRegSizeInBits));
uint64_t result = 0;
for (unsigned i = 0; i < num_bits; i++) {
result = (result << 1) | (value & 1);
@@ -1904,7 +1904,7 @@ uint64_t Simulator::ReverseBytes(uint64_t value, ReverseByteMode mode) {
// permute_table[Reverse16] is used by REV16_x, REV16_w
// permute_table[Reverse32] is used by REV32_x, REV_w
// permute_table[Reverse64] is used by REV_x
- ASSERT((Reverse16 == 0) && (Reverse32 == 1) && (Reverse64 == 2));
+ DCHECK((Reverse16 == 0) && (Reverse32 == 1) && (Reverse64 == 2));
static const uint8_t permute_table[3][8] = { {6, 7, 4, 5, 2, 3, 0, 1},
{4, 5, 6, 7, 0, 1, 2, 3},
{0, 1, 2, 3, 4, 5, 6, 7} };
@@ -2027,7 +2027,7 @@ void Simulator::VisitDataProcessing3Source(Instruction* instr) {
case UMADDL_x: result = xreg(instr->Ra()) + (rn_u32 * rm_u32); break;
case UMSUBL_x: result = xreg(instr->Ra()) - (rn_u32 * rm_u32); break;
case SMULH_x:
- ASSERT(instr->Ra() == kZeroRegCode);
+ DCHECK(instr->Ra() == kZeroRegCode);
result = MultiplyHighSigned(xreg(instr->Rn()), xreg(instr->Rm()));
break;
default: UNIMPLEMENTED();
@@ -2407,10 +2407,10 @@ void Simulator::VisitFPDataProcessing1Source(Instruction* instr) {
template <class T, int ebits, int mbits>
static T FPRound(int64_t sign, int64_t exponent, uint64_t mantissa,
FPRounding round_mode) {
- ASSERT((sign == 0) || (sign == 1));
+ DCHECK((sign == 0) || (sign == 1));
// Only the FPTieEven rounding mode is implemented.
- ASSERT(round_mode == FPTieEven);
+ DCHECK(round_mode == FPTieEven);
USE(round_mode);
// Rounding can promote subnormals to normals, and normals to infinities. For
@@ -2727,7 +2727,7 @@ double Simulator::FPToDouble(float value) {
float Simulator::FPToFloat(double value, FPRounding round_mode) {
// Only the FPTieEven rounding mode is implemented.
- ASSERT(round_mode == FPTieEven);
+ DCHECK(round_mode == FPTieEven);
USE(round_mode);
switch (std::fpclassify(value)) {
@@ -2856,7 +2856,7 @@ void Simulator::VisitFPDataProcessing3Source(Instruction* instr) {
template <typename T>
T Simulator::FPAdd(T op1, T op2) {
// NaNs should be handled elsewhere.
- ASSERT(!std::isnan(op1) && !std::isnan(op2));
+ DCHECK(!std::isnan(op1) && !std::isnan(op2));
if (std::isinf(op1) && std::isinf(op2) && (op1 != op2)) {
// inf + -inf returns the default NaN.
@@ -2871,7 +2871,7 @@ T Simulator::FPAdd(T op1, T op2) {
template <typename T>
T Simulator::FPDiv(T op1, T op2) {
// NaNs should be handled elsewhere.
- ASSERT(!std::isnan(op1) && !std::isnan(op2));
+ DCHECK(!std::isnan(op1) && !std::isnan(op2));
if ((std::isinf(op1) && std::isinf(op2)) || ((op1 == 0.0) && (op2 == 0.0))) {
// inf / inf and 0.0 / 0.0 return the default NaN.
@@ -2886,7 +2886,7 @@ T Simulator::FPDiv(T op1, T op2) {
template <typename T>
T Simulator::FPMax(T a, T b) {
// NaNs should be handled elsewhere.
- ASSERT(!std::isnan(a) && !std::isnan(b));
+ DCHECK(!std::isnan(a) && !std::isnan(b));
if ((a == 0.0) && (b == 0.0) &&
(copysign(1.0, a) != copysign(1.0, b))) {
@@ -2913,7 +2913,7 @@ T Simulator::FPMaxNM(T a, T b) {
template <typename T>
T Simulator::FPMin(T a, T b) {
// NaNs should be handled elsewhere.
- ASSERT(!std::isnan(a) && !std::isnan(b));
+ DCHECK(!std::isnan(a) && !std::isnan(b));
if ((a == 0.0) && (b == 0.0) &&
(copysign(1.0, a) != copysign(1.0, b))) {
@@ -2941,7 +2941,7 @@ T Simulator::FPMinNM(T a, T b) {
template <typename T>
T Simulator::FPMul(T op1, T op2) {
// NaNs should be handled elsewhere.
- ASSERT(!std::isnan(op1) && !std::isnan(op2));
+ DCHECK(!std::isnan(op1) && !std::isnan(op2));
if ((std::isinf(op1) && (op2 == 0.0)) || (std::isinf(op2) && (op1 == 0.0))) {
// inf * 0.0 returns the default NaN.
@@ -2986,7 +2986,7 @@ T Simulator::FPMulAdd(T a, T op1, T op2) {
}
result = FusedMultiplyAdd(op1, op2, a);
- ASSERT(!std::isnan(result));
+ DCHECK(!std::isnan(result));
// Work around broken fma implementations for rounded zero results: If a is
// 0.0, the sign of the result is the sign of op1 * op2 before rounding.
@@ -3013,7 +3013,7 @@ T Simulator::FPSqrt(T op) {
template <typename T>
T Simulator::FPSub(T op1, T op2) {
// NaNs should be handled elsewhere.
- ASSERT(!std::isnan(op1) && !std::isnan(op2));
+ DCHECK(!std::isnan(op1) && !std::isnan(op2));
if (std::isinf(op1) && std::isinf(op2) && (op1 == op2)) {
// inf - inf returns the default NaN.
@@ -3027,7 +3027,7 @@ T Simulator::FPSub(T op1, T op2) {
template <typename T>
T Simulator::FPProcessNaN(T op) {
- ASSERT(std::isnan(op));
+ DCHECK(std::isnan(op));
return fpcr().DN() ? FPDefaultNaN<T>() : ToQuietNaN(op);
}
@@ -3039,10 +3039,10 @@ T Simulator::FPProcessNaNs(T op1, T op2) {
} else if (IsSignallingNaN(op2)) {
return FPProcessNaN(op2);
} else if (std::isnan(op1)) {
- ASSERT(IsQuietNaN(op1));
+ DCHECK(IsQuietNaN(op1));
return FPProcessNaN(op1);
} else if (std::isnan(op2)) {
- ASSERT(IsQuietNaN(op2));
+ DCHECK(IsQuietNaN(op2));
return FPProcessNaN(op2);
} else {
return 0.0;
@@ -3059,13 +3059,13 @@ T Simulator::FPProcessNaNs3(T op1, T op2, T op3) {
} else if (IsSignallingNaN(op3)) {
return FPProcessNaN(op3);
} else if (std::isnan(op1)) {
- ASSERT(IsQuietNaN(op1));
+ DCHECK(IsQuietNaN(op1));
return FPProcessNaN(op1);
} else if (std::isnan(op2)) {
- ASSERT(IsQuietNaN(op2));
+ DCHECK(IsQuietNaN(op2));
return FPProcessNaN(op2);
} else if (std::isnan(op3)) {
- ASSERT(IsQuietNaN(op3));
+ DCHECK(IsQuietNaN(op3));
return FPProcessNaN(op3);
} else {
return 0.0;
@@ -3121,7 +3121,7 @@ void Simulator::VisitSystem(Instruction* instr) {
}
}
} else if (instr->Mask(SystemHintFMask) == SystemHintFixed) {
- ASSERT(instr->Mask(SystemHintMask) == HINT);
+ DCHECK(instr->Mask(SystemHintMask) == HINT);
switch (instr->ImmHint()) {
case NOP: break;
default: UNIMPLEMENTED();
@@ -3164,12 +3164,12 @@ bool Simulator::GetValue(const char* desc, int64_t* value) {
bool Simulator::PrintValue(const char* desc) {
if (strcmp(desc, "csp") == 0) {
- ASSERT(CodeFromName(desc) == static_cast<int>(kSPRegInternalCode));
+ DCHECK(CodeFromName(desc) == static_cast<int>(kSPRegInternalCode));
PrintF(stream_, "%s csp:%s 0x%016" PRIx64 "%s\n",
clr_reg_name, clr_reg_value, xreg(31, Reg31IsStackPointer), clr_normal);
return true;
} else if (strcmp(desc, "wcsp") == 0) {
- ASSERT(CodeFromName(desc) == static_cast<int>(kSPRegInternalCode));
+ DCHECK(CodeFromName(desc) == static_cast<int>(kSPRegInternalCode));
PrintF(stream_, "%s wcsp:%s 0x%08" PRIx32 "%s\n",
clr_reg_name, clr_reg_value, wreg(31, Reg31IsStackPointer), clr_normal);
return true;
@@ -3561,7 +3561,7 @@ void Simulator::VisitException(Instruction* instr) {
break;
default:
// We don't support a one-shot LOG_DISASM.
- ASSERT((parameters & LOG_DISASM) == 0);
+ DCHECK((parameters & LOG_DISASM) == 0);
// Don't print information that is already being traced.
parameters &= ~log_parameters();
// Print the requested information.
@@ -3575,8 +3575,8 @@ void Simulator::VisitException(Instruction* instr) {
size_t size = kDebugMessageOffset + strlen(message) + 1;
pc_ = pc_->InstructionAtOffset(RoundUp(size, kInstructionSize));
// - Verify that the unreachable marker is present.
- ASSERT(pc_->Mask(ExceptionMask) == HLT);
- ASSERT(pc_->ImmException() == kImmExceptionIsUnreachable);
+ DCHECK(pc_->Mask(ExceptionMask) == HLT);
+ DCHECK(pc_->ImmException() == kImmExceptionIsUnreachable);
// - Skip past the unreachable marker.
set_pc(pc_->following());
@@ -3606,7 +3606,7 @@ void Simulator::VisitException(Instruction* instr) {
void Simulator::DoPrintf(Instruction* instr) {
- ASSERT((instr->Mask(ExceptionMask) == HLT) &&
+ DCHECK((instr->Mask(ExceptionMask) == HLT) &&
(instr->ImmException() == kImmExceptionIsPrintf));
// Read the arguments encoded inline in the instruction stream.
@@ -3620,8 +3620,8 @@ void Simulator::DoPrintf(Instruction* instr) {
instr + kPrintfArgPatternListOffset,
sizeof(arg_pattern_list));
- ASSERT(arg_count <= kPrintfMaxArgCount);
- ASSERT((arg_pattern_list >> (kPrintfArgPatternBits * arg_count)) == 0);
+ DCHECK(arg_count <= kPrintfMaxArgCount);
+ DCHECK((arg_pattern_list >> (kPrintfArgPatternBits * arg_count)) == 0);
// We need to call the host printf function with a set of arguments defined by
// arg_pattern_list. Because we don't know the types and sizes of the
@@ -3633,7 +3633,7 @@ void Simulator::DoPrintf(Instruction* instr) {
// Leave enough space for one extra character per expected argument (plus the
// '\0' termination).
const char * format_base = reg<const char *>(0);
- ASSERT(format_base != NULL);
+ DCHECK(format_base != NULL);
size_t length = strlen(format_base) + 1;
char * const format = new char[length + arg_count];
@@ -3668,7 +3668,7 @@ void Simulator::DoPrintf(Instruction* instr) {
}
}
}
- ASSERT(format_scratch <= (format + length + arg_count));
+ DCHECK(format_scratch <= (format + length + arg_count));
CHECK(placeholder_count == arg_count);
// Finally, call printf with each chunk, passing the appropriate register
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