Rename ASSERT* to DCHECK*.

src/arm64/simulator-arm64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <stdlib.h>
 #include <cmath>
 #include <cstdarg>
 #include "src/v8.h"
 
 #if V8_TARGET_ARCH_ARM64
@@ skipping 55 matching lines @@
     va_end(arguments);
   }
 }
 
 
 const Instruction* Simulator::kEndOfSimAddress = NULL;
 
 
 void SimSystemRegister::SetBits(int msb, int lsb, uint32_t bits) {
   int width = msb - lsb + 1;
-  ASSERT(is_uintn(bits, width) || is_intn(bits, width));
+  DCHECK(is_uintn(bits, width) || is_intn(bits, width));
 
   bits <<= lsb;
   uint32_t mask = ((1 << width) - 1) << lsb;
-  ASSERT((mask & write_ignore_mask_) == 0);
+  DCHECK((mask & write_ignore_mask_) == 0);
 
   value_ = (value_ & ~mask) | (bits & mask);
 }
 
 
 SimSystemRegister SimSystemRegister::DefaultValueFor(SystemRegister id) {
   switch (id) {
     case NZCV:
       return SimSystemRegister(0x00000000, NZCVWriteIgnoreMask);
     case FPCR:
       return SimSystemRegister(0x00000000, FPCRWriteIgnoreMask);
     default:
       UNREACHABLE();
       return SimSystemRegister();
   }
 }
 
 
 void Simulator::Initialize(Isolate* isolate) {
   if (isolate->simulator_initialized()) return;
   isolate->set_simulator_initialized(true);
   ExternalReference::set_redirector(isolate, &RedirectExternalReference);
 }
 
 
 // Get the active Simulator for the current thread.
 Simulator* Simulator::current(Isolate* isolate) {
   Isolate::PerIsolateThreadData* isolate_data =
       isolate->FindOrAllocatePerThreadDataForThisThread();
-  ASSERT(isolate_data != NULL);
+  DCHECK(isolate_data != NULL);
 
   Simulator* sim = isolate_data->simulator();
   if (sim == NULL) {
     if (FLAG_trace_sim || FLAG_log_instruction_stats || FLAG_debug_sim) {
       sim = new Simulator(new Decoder<DispatchingDecoderVisitor>(), isolate);
     } else {
       sim = new Decoder<Simulator>();
       sim->isolate_ = isolate;
     }
     isolate_data->set_simulator(sim);
   }
   return sim;
 }
 
 
 void Simulator::CallVoid(byte* entry, CallArgument* args) {
   int index_x = 0;
   int index_d = 0;
 
   std::vector<int64_t> stack_args(0);
   for (int i = 0; !args[i].IsEnd(); i++) {
     CallArgument arg = args[i];
     if (arg.IsX() && (index_x < 8)) {
       set_xreg(index_x++, arg.bits());
     } else if (arg.IsD() && (index_d < 8)) {
       set_dreg_bits(index_d++, arg.bits());
     } else {
-      ASSERT(arg.IsD() || arg.IsX());
+      DCHECK(arg.IsD() || arg.IsX());
       stack_args.push_back(arg.bits());
     }
   }
 
   // Process stack arguments, and make sure the stack is suitably aligned.
   uintptr_t original_stack = sp();
   uintptr_t entry_stack = original_stack -
                           stack_args.size() * sizeof(stack_args[0]);
   if (base::OS::ActivationFrameAlignment() != 0) {
     entry_stack &= -base::OS::ActivationFrameAlignment();
   }
   char * stack = reinterpret_cast<char*>(entry_stack);
   std::vector<int64_t>::const_iterator it;
   for (it = stack_args.begin(); it != stack_args.end(); it++) {
     memcpy(stack, &(*it), sizeof(*it));
     stack += sizeof(*it);
   }
 
-  ASSERT(reinterpret_cast<uintptr_t>(stack) <= original_stack);
+  DCHECK(reinterpret_cast<uintptr_t>(stack) <= original_stack);
   set_sp(entry_stack);
 
   // Call the generated code.
   set_pc(entry);
   set_lr(kEndOfSimAddress);
   CheckPCSComplianceAndRun();
 
   set_sp(original_stack);
 }
 
@@ skipping 81 matching lines @@
   Run();
 #ifdef DEBUG
   CHECK_EQ(original_stack, sp());
   // Check that callee-saved registers have been preserved.
   register_list = kCalleeSaved;
   fpregister_list = kCalleeSavedFP;
   for (int i = 0; i < kNumberOfCalleeSavedRegisters; i++) {
     CHECK_EQ(saved_registers[i], xreg(register_list.PopLowestIndex().code()));
   }
   for (int i = 0; i < kNumberOfCalleeSavedFPRegisters; i++) {
-    ASSERT(saved_fpregisters[i] ==
+    DCHECK(saved_fpregisters[i] ==
            dreg_bits(fpregister_list.PopLowestIndex().code()));
   }
 
   // Corrupt caller saved register minus the return regiters.
 
   // In theory x0 to x7 can be used for return values, but V8 only uses x0, x1
   // for now .
   register_list = kCallerSaved;
   register_list.Remove(x0);
   register_list.Remove(x1);
@@ skipping 12 matching lines @@
 #ifdef DEBUG
 // The least significant byte of the curruption value holds the corresponding
 // register's code.
 void Simulator::CorruptRegisters(CPURegList* list, uint64_t value) {
   if (list->type() == CPURegister::kRegister) {
     while (!list->IsEmpty()) {
       unsigned code = list->PopLowestIndex().code();
       set_xreg(code, value | code);
     }
   } else {
-    ASSERT(list->type() == CPURegister::kFPRegister);
+    DCHECK(list->type() == CPURegister::kFPRegister);
     while (!list->IsEmpty()) {
       unsigned code = list->PopLowestIndex().code();
       set_dreg_bits(code, value | code);
     }
   }
 }
 
 
 void Simulator::CorruptAllCallerSavedCPURegisters() {
   // Corrupt alters its parameter so copy them first.
   CPURegList register_list = kCallerSaved;
   CPURegList fpregister_list = kCallerSavedFP;
 
   CorruptRegisters(&register_list, kCallerSavedRegisterCorruptionValue);
   CorruptRegisters(&fpregister_list, kCallerSavedFPRegisterCorruptionValue);
 }
 #endif
 
 
 // Extending the stack by 2 * 64 bits is required for stack alignment purposes.
 uintptr_t Simulator::PushAddress(uintptr_t address) {
-  ASSERT(sizeof(uintptr_t) < 2 * kXRegSize);
+  DCHECK(sizeof(uintptr_t) < 2 * kXRegSize);
   intptr_t new_sp = sp() - 2 * kXRegSize;
   uintptr_t* alignment_slot =
     reinterpret_cast<uintptr_t*>(new_sp + kXRegSize);
   memcpy(alignment_slot, &kSlotsZapValue, kPointerSize);
   uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(new_sp);
   memcpy(stack_slot, &address, kPointerSize);
   set_sp(new_sp);
   return new_sp;
 }
 
 
 uintptr_t Simulator::PopAddress() {
   intptr_t current_sp = sp();
   uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(current_sp);
   uintptr_t address = *stack_slot;
-  ASSERT(sizeof(uintptr_t) < 2 * kXRegSize);
+  DCHECK(sizeof(uintptr_t) < 2 * kXRegSize);
   set_sp(current_sp + 2 * kXRegSize);
   return address;
 }
 
 
 // Returns the limit of the stack area to enable checking for stack overflows.
 uintptr_t Simulator::StackLimit() const {
   // Leave a safety margin of 1024 bytes to prevent overrunning the stack when
   // pushing values.
   return reinterpret_cast<uintptr_t>(stack_limit_) + 1024;
@@ skipping 133 matching lines @@
   T external_function() { return reinterpret_cast<T>(external_function_); }
 
   ExternalReference::Type type() { return type_; }
 
   static Redirection* Get(void* external_function,
                           ExternalReference::Type type) {
     Isolate* isolate = Isolate::Current();
     Redirection* current = isolate->simulator_redirection();
     for (; current != NULL; current = current->next_) {
       if (current->external_function_ == external_function) {
-        ASSERT_EQ(current->type(), type);
+        DCHECK_EQ(current->type(), type);
         return current;
       }
     }
     return new Redirection(external_function, type);
   }
 
   static Redirection* FromHltInstruction(Instruction* redirect_call) {
     char* addr_of_hlt = reinterpret_cast<char*>(redirect_call);
     char* addr_of_redirection =
         addr_of_hlt - OFFSET_OF(Redirection, redirect_call_);
@@ skipping 263 matching lines @@
 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31"};
 
 const char* Simulator::vreg_names[] = {
 "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",
 "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",
 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"};
 
 
 const char* Simulator::WRegNameForCode(unsigned code, Reg31Mode mode) {
-  ASSERT(code < kNumberOfRegisters);
+  DCHECK(code < kNumberOfRegisters);
   // If the code represents the stack pointer, index the name after zr.
   if ((code == kZeroRegCode) && (mode == Reg31IsStackPointer)) {
     code = kZeroRegCode + 1;
   }
   return wreg_names[code];
 }
 
 
 const char* Simulator::XRegNameForCode(unsigned code, Reg31Mode mode) {
-  ASSERT(code < kNumberOfRegisters);
+  DCHECK(code < kNumberOfRegisters);
   // If the code represents the stack pointer, index the name after zr.
   if ((code == kZeroRegCode) && (mode == Reg31IsStackPointer)) {
     code = kZeroRegCode + 1;
   }
   return xreg_names[code];
 }
 
 
 const char* Simulator::SRegNameForCode(unsigned code) {
-  ASSERT(code < kNumberOfFPRegisters);
+  DCHECK(code < kNumberOfFPRegisters);
   return sreg_names[code];
 }
 
 
 const char* Simulator::DRegNameForCode(unsigned code) {
-  ASSERT(code < kNumberOfFPRegisters);
+  DCHECK(code < kNumberOfFPRegisters);
   return dreg_names[code];
 }
 
 
 const char* Simulator::VRegNameForCode(unsigned code) {
-  ASSERT(code < kNumberOfFPRegisters);
+  DCHECK(code < kNumberOfFPRegisters);
   return vreg_names[code];
 }
 
 
 int Simulator::CodeFromName(const char* name) {
   for (unsigned i = 0; i < kNumberOfRegisters; i++) {
     if ((strcmp(xreg_names[i], name) == 0) ||
         (strcmp(wreg_names[i], name) == 0)) {
       return i;
     }
@@ skipping 12 matching lines @@
 }
 
 
 // Helpers ---------------------------------------------------------------------
 template <typename T>
 T Simulator::AddWithCarry(bool set_flags,
                           T src1,
                           T src2,
                           T carry_in) {
   typedef typename make_unsigned<T>::type unsignedT;
-  ASSERT((carry_in == 0) || (carry_in == 1));
+  DCHECK((carry_in == 0) || (carry_in == 1));
 
   T signed_sum = src1 + src2 + carry_in;
   T result = signed_sum;
 
   bool N, Z, C, V;
 
   // Compute the C flag
   unsignedT u1 = static_cast<unsignedT>(src1);
   unsignedT u2 = static_cast<unsignedT>(src2);
   unsignedT urest = std::numeric_limits<unsignedT>::max() - u1;
@@ skipping 214 matching lines @@
   last_nzcv = nzcv();
 
   static SimSystemRegister last_fpcr;
   if (print_all || first_run || (last_fpcr.RawValue() != fpcr().RawValue())) {
     static const char * rmode[] = {
       "0b00 (Round to Nearest)",
       "0b01 (Round towards Plus Infinity)",
       "0b10 (Round towards Minus Infinity)",
       "0b11 (Round towards Zero)"
     };
-    ASSERT(fpcr().RMode() <= (sizeof(rmode) / sizeof(rmode[0])));
+    DCHECK(fpcr().RMode() <= (sizeof(rmode) / sizeof(rmode[0])));
     fprintf(stream_, "# %sFPCR: %sAHP:%d DN:%d FZ:%d RMode:%s%s\n",
             clr_flag_name,
             clr_flag_value,
             fpcr().AHP(), fpcr().DN(), fpcr().FZ(), rmode[fpcr().RMode()],
             clr_normal);
   }
   last_fpcr = fpcr();
 
   first_run = false;
 }
@@ skipping 119 matching lines @@
     case B:
       set_pc(instr->ImmPCOffsetTarget());
       break;
     default:
       UNREACHABLE();
   }
 }
 
 
 void Simulator::VisitConditionalBranch(Instruction* instr) {
-  ASSERT(instr->Mask(ConditionalBranchMask) == B_cond);
+  DCHECK(instr->Mask(ConditionalBranchMask) == B_cond);
   if (ConditionPassed(static_cast<Condition>(instr->ConditionBranch()))) {
     set_pc(instr->ImmPCOffsetTarget());
   }
 }
 
 
 void Simulator::VisitUnconditionalBranchToRegister(Instruction* instr) {
   Instruction* target = reg<Instruction*>(instr->Rn());
   switch (instr->Mask(UnconditionalBranchToRegisterMask)) {
     case BLR: {
@@ skipping 192 matching lines @@
 template<typename T>
 void Simulator::ConditionalCompareHelper(Instruction* instr, T op2) {
   T op1 = reg<T>(instr->Rn());
 
   if (ConditionPassed(static_cast<Condition>(instr->Condition()))) {
     // If the condition passes, set the status flags to the result of comparing
     // the operands.
     if (instr->Mask(ConditionalCompareMask) == CCMP) {
       AddWithCarry<T>(true, op1, ~op2, 1);
     } else {
-      ASSERT(instr->Mask(ConditionalCompareMask) == CCMN);
+      DCHECK(instr->Mask(ConditionalCompareMask) == CCMN);
       AddWithCarry<T>(true, op1, op2, 0);
     }
   } else {
     // If the condition fails, set the status flags to the nzcv immediate.
     nzcv().SetFlags(instr->Nzcv());
   }
 }
 
 
 void Simulator::VisitLoadStoreUnsignedOffset(Instruction* instr) {
@@ skipping 12 matching lines @@
 }
 
 
 void Simulator::VisitLoadStorePostIndex(Instruction* instr) {
   LoadStoreHelper(instr, instr->ImmLS(), PostIndex);
 }
 
 
 void Simulator::VisitLoadStoreRegisterOffset(Instruction* instr) {
   Extend ext = static_cast<Extend>(instr->ExtendMode());
-  ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX));
+  DCHECK((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX));
   unsigned shift_amount = instr->ImmShiftLS() * instr->SizeLS();
 
   int64_t offset = ExtendValue(xreg(instr->Rm()), ext, shift_amount);
   LoadStoreHelper(instr, offset, Offset);
 }
 
 
 void Simulator::LoadStoreHelper(Instruction* instr,
                                 int64_t offset,
                                 AddrMode addrmode) {
@@ skipping 114 matching lines @@
 
     // For store the address post writeback is used to check access below the
     // stack.
     stack = reinterpret_cast<uint8_t*>(sp());
   }
 
   LoadStorePairOp op =
     static_cast<LoadStorePairOp>(instr->Mask(LoadStorePairMask));
 
   // 'rt' and 'rt2' can only be aliased for stores.
-  ASSERT(((op & LoadStorePairLBit) == 0) || (rt != rt2));
+  DCHECK(((op & LoadStorePairLBit) == 0) || (rt != rt2));
 
   switch (op) {
     case LDP_w: {
       set_wreg(rt, MemoryRead32(address));
       set_wreg(rt2, MemoryRead32(address + kWRegSize));
       break;
     }
     case LDP_s: {
       set_sreg(rt, MemoryReadFP32(address));
       set_sreg(rt2, MemoryReadFP32(address + kSRegSize));
@@ skipping 87 matching lines @@
   }
 
   return reinterpret_cast<uint8_t*>(address);
 }
 
 
 void Simulator::LoadStoreWriteBack(unsigned addr_reg,
                                    int64_t offset,
                                    AddrMode addrmode) {
   if ((addrmode == PreIndex) || (addrmode == PostIndex)) {
-    ASSERT(offset != 0);
+    DCHECK(offset != 0);
     uint64_t address = xreg(addr_reg, Reg31IsStackPointer);
     set_reg(addr_reg, address + offset, Reg31IsStackPointer);
   }
 }
 
 
 void Simulator::CheckMemoryAccess(uint8_t* address, uint8_t* stack) {
   if ((address >= stack_limit_) && (address < stack)) {
     fprintf(stream_, "ACCESS BELOW STACK POINTER:\n");
     fprintf(stream_, "  sp is here:          0x%16p\n", stack);
     fprintf(stream_, "  access was here:     0x%16p\n", address);
     fprintf(stream_, "  stack limit is here: 0x%16p\n", stack_limit_);
     fprintf(stream_, "\n");
     FATAL("ACCESS BELOW STACK POINTER");
   }
 }
 
 
 uint64_t Simulator::MemoryRead(uint8_t* address, unsigned num_bytes) {
-  ASSERT(address != NULL);
-  ASSERT((num_bytes > 0) && (num_bytes <= sizeof(uint64_t)));
+  DCHECK(address != NULL);
+  DCHECK((num_bytes > 0) && (num_bytes <= sizeof(uint64_t)));
   uint64_t read = 0;
   memcpy(&read, address, num_bytes);
   return read;
 }
 
 
 uint8_t Simulator::MemoryRead8(uint8_t* address) {
   return MemoryRead(address, sizeof(uint8_t));
 }
 
@@ skipping 19 matching lines @@
 
 
 double Simulator::MemoryReadFP64(uint8_t* address) {
   return rawbits_to_double(MemoryRead64(address));
 }
 
 
 void Simulator::MemoryWrite(uint8_t* address,
                             uint64_t value,
                             unsigned num_bytes) {
-  ASSERT(address != NULL);
-  ASSERT((num_bytes > 0) && (num_bytes <= sizeof(uint64_t)));
+  DCHECK(address != NULL);
+  DCHECK((num_bytes > 0) && (num_bytes <= sizeof(uint64_t)));
 
   LogWrite(address, value, num_bytes);
   memcpy(address, &value, num_bytes);
 }
 
 
 void Simulator::MemoryWrite32(uint8_t* address, uint32_t value) {
   MemoryWrite(address, value, sizeof(uint32_t));
 }
 
@@ skipping 13 matching lines @@
 }
 
 
 void Simulator::VisitMoveWideImmediate(Instruction* instr) {
   MoveWideImmediateOp mov_op =
     static_cast<MoveWideImmediateOp>(instr->Mask(MoveWideImmediateMask));
   int64_t new_xn_val = 0;
 
   bool is_64_bits = instr->SixtyFourBits() == 1;
   // Shift is limited for W operations.
-  ASSERT(is_64_bits || (instr->ShiftMoveWide() < 2));
+  DCHECK(is_64_bits || (instr->ShiftMoveWide() < 2));
 
   // Get the shifted immediate.
   int64_t shift = instr->ShiftMoveWide() * 16;
   int64_t shifted_imm16 = instr->ImmMoveWide() << shift;
 
   // Compute the new value.
   switch (mov_op) {
     case MOVN_w:
     case MOVN_x: {
         new_xn_val = ~shifted_imm16;
@@ skipping 69 matching lines @@
     case CLS_x: {
       set_xreg(dst, CountLeadingSignBits(xreg(src), kXRegSizeInBits));
       break;
     }
     default: UNIMPLEMENTED();
   }
 }
 
 
 uint64_t Simulator::ReverseBits(uint64_t value, unsigned num_bits) {
-  ASSERT((num_bits == kWRegSizeInBits) || (num_bits == kXRegSizeInBits));
+  DCHECK((num_bits == kWRegSizeInBits) || (num_bits == kXRegSizeInBits));
   uint64_t result = 0;
   for (unsigned i = 0; i < num_bits; i++) {
     result = (result << 1) | (value & 1);
     value >>= 1;
   }
   return result;
 }
 
 
 uint64_t Simulator::ReverseBytes(uint64_t value, ReverseByteMode mode) {
   // Split the 64-bit value into an 8-bit array, where b[0] is the least
   // significant byte, and b[7] is the most significant.
   uint8_t bytes[8];
   uint64_t mask = 0xff00000000000000UL;
   for (int i = 7; i >= 0; i--) {
     bytes[i] = (value & mask) >> (i * 8);
     mask >>= 8;
   }
 
   // Permutation tables for REV instructions.
   //  permute_table[Reverse16] is used by REV16_x, REV16_w
   //  permute_table[Reverse32] is used by REV32_x, REV_w
   //  permute_table[Reverse64] is used by REV_x
-  ASSERT((Reverse16 == 0) && (Reverse32 == 1) && (Reverse64 == 2));
+  DCHECK((Reverse16 == 0) && (Reverse32 == 1) && (Reverse64 == 2));
   static const uint8_t permute_table[3][8] = { {6, 7, 4, 5, 2, 3, 0, 1},
                                                {4, 5, 6, 7, 0, 1, 2, 3},
                                                {0, 1, 2, 3, 4, 5, 6, 7} };
   uint64_t result = 0;
   for (int i = 0; i < 8; i++) {
     result <<= 8;
     result |= bytes[permute_table[mode][i]];
   }
   return result;
 }
@@ skipping 102 matching lines @@
       break;
     case MSUB_w:
     case MSUB_x:
       result = xreg(instr->Ra()) - (xreg(instr->Rn()) * xreg(instr->Rm()));
       break;
     case SMADDL_x: result = xreg(instr->Ra()) + (rn_s32 * rm_s32); break;
     case SMSUBL_x: result = xreg(instr->Ra()) - (rn_s32 * rm_s32); break;
     case UMADDL_x: result = xreg(instr->Ra()) + (rn_u32 * rm_u32); break;
     case UMSUBL_x: result = xreg(instr->Ra()) - (rn_u32 * rm_u32); break;
     case SMULH_x:
-      ASSERT(instr->Ra() == kZeroRegCode);
+      DCHECK(instr->Ra() == kZeroRegCode);
       result = MultiplyHighSigned(xreg(instr->Rn()), xreg(instr->Rm()));
       break;
     default: UNIMPLEMENTED();
   }
 
   if (instr->SixtyFourBits()) {
     set_xreg(instr->Rd(), result);
   } else {
     set_wreg(instr->Rd(), result);
   }
@@ skipping 359 matching lines @@
 // The input value is assumed to be a normalized value. That is, the input may
 // not be infinity or NaN. If the source value is subnormal, it must be
 // normalized before calling this function such that the highest set bit in the
 // mantissa has the value 'pow(2, exponent)'.
 //
 // Callers should use FPRoundToFloat or FPRoundToDouble directly, rather than
 // calling a templated FPRound.
 template <class T, int ebits, int mbits>
 static T FPRound(int64_t sign, int64_t exponent, uint64_t mantissa,
                  FPRounding round_mode) {
-  ASSERT((sign == 0) || (sign == 1));
+  DCHECK((sign == 0) || (sign == 1));
 
   // Only the FPTieEven rounding mode is implemented.
-  ASSERT(round_mode == FPTieEven);
+  DCHECK(round_mode == FPTieEven);
   USE(round_mode);
 
   // Rounding can promote subnormals to normals, and normals to infinities. For
   // example, a double with exponent 127 (FLT_MAX_EXP) would appear to be
   // encodable as a float, but rounding based on the low-order mantissa bits
   // could make it overflow. With ties-to-even rounding, this value would become
   // an infinity.
 
   // ---- Rounding Method ----
   //
@@ skipping 296 matching lines @@
     }
   }
 
   UNREACHABLE();
   return static_cast<double>(value);
 }
 
 
 float Simulator::FPToFloat(double value, FPRounding round_mode) {
   // Only the FPTieEven rounding mode is implemented.
-  ASSERT(round_mode == FPTieEven);
+  DCHECK(round_mode == FPTieEven);
   USE(round_mode);
 
   switch (std::fpclassify(value)) {
     case FP_NAN: {
       if (fpcr().DN()) return kFP32DefaultNaN;
 
       // Convert NaNs as the processor would:
       //  - The sign is propagated.
       //  - The payload (mantissa) is transferred as much as possible, except
       //    that the top bit is forced to '1', making the result a quiet NaN.
@@ skipping 108 matching lines @@
       set_dreg(fd, FPMulAdd(-dreg(fa), dreg(fn), dreg(fm)));
       break;
     default: UNIMPLEMENTED();
   }
 }
 
 
 template <typename T>
 T Simulator::FPAdd(T op1, T op2) {
   // NaNs should be handled elsewhere.
-  ASSERT(!std::isnan(op1) && !std::isnan(op2));
+  DCHECK(!std::isnan(op1) && !std::isnan(op2));
 
   if (std::isinf(op1) && std::isinf(op2) && (op1 != op2)) {
     // inf + -inf returns the default NaN.
     return FPDefaultNaN<T>();
   } else {
     // Other cases should be handled by standard arithmetic.
     return op1 + op2;
   }
 }
 
 
 template <typename T>
 T Simulator::FPDiv(T op1, T op2) {
   // NaNs should be handled elsewhere.
-  ASSERT(!std::isnan(op1) && !std::isnan(op2));
+  DCHECK(!std::isnan(op1) && !std::isnan(op2));
 
   if ((std::isinf(op1) && std::isinf(op2)) || ((op1 == 0.0) && (op2 == 0.0))) {
     // inf / inf and 0.0 / 0.0 return the default NaN.
     return FPDefaultNaN<T>();
   } else {
     // Other cases should be handled by standard arithmetic.
     return op1 / op2;
   }
 }
 
 
 template <typename T>
 T Simulator::FPMax(T a, T b) {
   // NaNs should be handled elsewhere.
-  ASSERT(!std::isnan(a) && !std::isnan(b));
+  DCHECK(!std::isnan(a) && !std::isnan(b));
 
   if ((a == 0.0) && (b == 0.0) &&
       (copysign(1.0, a) != copysign(1.0, b))) {
     // a and b are zero, and the sign differs: return +0.0.
     return 0.0;
   } else {
     return (a > b) ? a : b;
   }
 }
 
 
 template <typename T>
 T Simulator::FPMaxNM(T a, T b) {
   if (IsQuietNaN(a) && !IsQuietNaN(b)) {
     a = kFP64NegativeInfinity;
   } else if (!IsQuietNaN(a) && IsQuietNaN(b)) {
     b = kFP64NegativeInfinity;
   }
 
   T result = FPProcessNaNs(a, b);
   return std::isnan(result) ? result : FPMax(a, b);
 }
 
 template <typename T>
 T Simulator::FPMin(T a, T b) {
   // NaNs should be handled elsewhere.
-  ASSERT(!std::isnan(a) && !std::isnan(b));
+  DCHECK(!std::isnan(a) && !std::isnan(b));
 
   if ((a == 0.0) && (b == 0.0) &&
       (copysign(1.0, a) != copysign(1.0, b))) {
     // a and b are zero, and the sign differs: return -0.0.
     return -0.0;
   } else {
     return (a < b) ? a : b;
   }
 }
 
 
 template <typename T>
 T Simulator::FPMinNM(T a, T b) {
   if (IsQuietNaN(a) && !IsQuietNaN(b)) {
     a = kFP64PositiveInfinity;
   } else if (!IsQuietNaN(a) && IsQuietNaN(b)) {
     b = kFP64PositiveInfinity;
   }
 
   T result = FPProcessNaNs(a, b);
   return std::isnan(result) ? result : FPMin(a, b);
 }
 
 
 template <typename T>
 T Simulator::FPMul(T op1, T op2) {
   // NaNs should be handled elsewhere.
-  ASSERT(!std::isnan(op1) && !std::isnan(op2));
+  DCHECK(!std::isnan(op1) && !std::isnan(op2));
 
   if ((std::isinf(op1) && (op2 == 0.0)) || (std::isinf(op2) && (op1 == 0.0))) {
     // inf * 0.0 returns the default NaN.
     return FPDefaultNaN<T>();
   } else {
     // Other cases should be handled by standard arithmetic.
     return op1 * op2;
   }
 }
 
@@ skipping 24 matching lines @@
     return FPDefaultNaN<T>();
   }
 
   // Work around broken fma implementations for exact zero results: The sign of
   // exact 0.0 results is positive unless both a and op1 * op2 are negative.
   if (((op1 == 0.0) || (op2 == 0.0)) && (a == 0.0)) {
     return ((sign_a < 0) && (sign_prod < 0)) ? -0.0 : 0.0;
   }
 
   result = FusedMultiplyAdd(op1, op2, a);
-  ASSERT(!std::isnan(result));
+  DCHECK(!std::isnan(result));
 
   // Work around broken fma implementations for rounded zero results: If a is
   // 0.0, the sign of the result is the sign of op1 * op2 before rounding.
   if ((a == 0.0) && (result == 0.0)) {
     return copysign(0.0, sign_prod);
   }
 
   return result;
 }
 
 
 template <typename T>
 T Simulator::FPSqrt(T op) {
   if (std::isnan(op)) {
     return FPProcessNaN(op);
   } else if (op < 0.0) {
     return FPDefaultNaN<T>();
   } else {
     return std::sqrt(op);
   }
 }
 
 
 template <typename T>
 T Simulator::FPSub(T op1, T op2) {
   // NaNs should be handled elsewhere.
-  ASSERT(!std::isnan(op1) && !std::isnan(op2));
+  DCHECK(!std::isnan(op1) && !std::isnan(op2));
 
   if (std::isinf(op1) && std::isinf(op2) && (op1 == op2)) {
     // inf - inf returns the default NaN.
     return FPDefaultNaN<T>();
   } else {
     // Other cases should be handled by standard arithmetic.
     return op1 - op2;
   }
 }
 
 
 template <typename T>
 T Simulator::FPProcessNaN(T op) {
-  ASSERT(std::isnan(op));
+  DCHECK(std::isnan(op));
   return fpcr().DN() ? FPDefaultNaN<T>() : ToQuietNaN(op);
 }
 
 
 template <typename T>
 T Simulator::FPProcessNaNs(T op1, T op2) {
   if (IsSignallingNaN(op1)) {
     return FPProcessNaN(op1);
   } else if (IsSignallingNaN(op2)) {
     return FPProcessNaN(op2);
   } else if (std::isnan(op1)) {
-    ASSERT(IsQuietNaN(op1));
+    DCHECK(IsQuietNaN(op1));
     return FPProcessNaN(op1);
   } else if (std::isnan(op2)) {
-    ASSERT(IsQuietNaN(op2));
+    DCHECK(IsQuietNaN(op2));
     return FPProcessNaN(op2);
   } else {
     return 0.0;
   }
 }
 
 
 template <typename T>
 T Simulator::FPProcessNaNs3(T op1, T op2, T op3) {
   if (IsSignallingNaN(op1)) {
     return FPProcessNaN(op1);
   } else if (IsSignallingNaN(op2)) {
     return FPProcessNaN(op2);
   } else if (IsSignallingNaN(op3)) {
     return FPProcessNaN(op3);
   } else if (std::isnan(op1)) {
-    ASSERT(IsQuietNaN(op1));
+    DCHECK(IsQuietNaN(op1));
     return FPProcessNaN(op1);
   } else if (std::isnan(op2)) {
-    ASSERT(IsQuietNaN(op2));
+    DCHECK(IsQuietNaN(op2));
     return FPProcessNaN(op2);
   } else if (std::isnan(op3)) {
-    ASSERT(IsQuietNaN(op3));
+    DCHECK(IsQuietNaN(op3));
     return FPProcessNaN(op3);
   } else {
     return 0.0;
   }
 }
 
 
 bool Simulator::FPProcessNaNs(Instruction* instr) {
   unsigned fd = instr->Rd();
   unsigned fn = instr->Rn();
@@ skipping 35 matching lines @@
       case MSR: {
         switch (instr->ImmSystemRegister()) {
           case NZCV: nzcv().SetRawValue(xreg(instr->Rt())); break;
           case FPCR: fpcr().SetRawValue(xreg(instr->Rt())); break;
           default: UNIMPLEMENTED();
         }
         break;
       }
     }
   } else if (instr->Mask(SystemHintFMask) == SystemHintFixed) {
-    ASSERT(instr->Mask(SystemHintMask) == HINT);
+    DCHECK(instr->Mask(SystemHintMask) == HINT);
     switch (instr->ImmHint()) {
       case NOP: break;
       default: UNIMPLEMENTED();
     }
   } else if (instr->Mask(MemBarrierFMask) == MemBarrierFixed) {
     __sync_synchronize();
   } else {
     UNIMPLEMENTED();
   }
 }
@@ skipping 22 matching lines @@
                   reinterpret_cast<uint64_t*>(value)) == 1;
   } else {
     return SScanF(desc, "%" SCNu64,
                   reinterpret_cast<uint64_t*>(value)) == 1;
   }
 }
 
 
 bool Simulator::PrintValue(const char* desc) {
   if (strcmp(desc, "csp") == 0) {
-    ASSERT(CodeFromName(desc) == static_cast<int>(kSPRegInternalCode));
+    DCHECK(CodeFromName(desc) == static_cast<int>(kSPRegInternalCode));
     PrintF(stream_, "%s csp:%s 0x%016" PRIx64 "%s\n",
         clr_reg_name, clr_reg_value, xreg(31, Reg31IsStackPointer), clr_normal);
     return true;
   } else if (strcmp(desc, "wcsp") == 0) {
-    ASSERT(CodeFromName(desc) == static_cast<int>(kSPRegInternalCode));
+    DCHECK(CodeFromName(desc) == static_cast<int>(kSPRegInternalCode));
     PrintF(stream_, "%s wcsp:%s 0x%08" PRIx32 "%s\n",
         clr_reg_name, clr_reg_value, wreg(31, Reg31IsStackPointer), clr_normal);
     return true;
   }
 
   int i = CodeFromName(desc);
   STATIC_ASSERT(kNumberOfRegisters == kNumberOfFPRegisters);
   if (i < 0 || static_cast<unsigned>(i) >= kNumberOfFPRegisters) return false;
 
   if (desc[0] == 'v') {
@@ skipping 371 matching lines @@
             if (parameters & LOG_FP_REGS) { PrintFPRegisters(); }
             break;
           case TRACE_DISABLE:
             set_log_parameters(log_parameters() & ~parameters);
             break;
           case TRACE_OVERRIDE:
             set_log_parameters(parameters);
             break;
           default:
             // We don't support a one-shot LOG_DISASM.
-            ASSERT((parameters & LOG_DISASM) == 0);
+            DCHECK((parameters & LOG_DISASM) == 0);
             // Don't print information that is already being traced.
             parameters &= ~log_parameters();
             // Print the requested information.
             if (parameters & LOG_SYS_REGS) PrintSystemRegisters(true);
             if (parameters & LOG_REGS) PrintRegisters(true);
             if (parameters & LOG_FP_REGS) PrintFPRegisters(true);
         }
 
         // The stop parameters are inlined in the code. Skip them:
         //  - Skip to the end of the message string.
         size_t size = kDebugMessageOffset + strlen(message) + 1;
         pc_ = pc_->InstructionAtOffset(RoundUp(size, kInstructionSize));
         //  - Verify that the unreachable marker is present.
-        ASSERT(pc_->Mask(ExceptionMask) == HLT);
-        ASSERT(pc_->ImmException() ==  kImmExceptionIsUnreachable);
+        DCHECK(pc_->Mask(ExceptionMask) == HLT);
+        DCHECK(pc_->ImmException() ==  kImmExceptionIsUnreachable);
         //  - Skip past the unreachable marker.
         set_pc(pc_->following());
 
         // Check if the debugger should break.
         if (parameters & BREAK) Debug();
 
       } else if (instr->ImmException() == kImmExceptionIsRedirectedCall) {
         DoRuntimeCall(instr);
       } else if (instr->ImmException() == kImmExceptionIsPrintf) {
         DoPrintf(instr);
 
       } else if (instr->ImmException() == kImmExceptionIsUnreachable) {
         fprintf(stream_, "Hit UNREACHABLE marker at PC=%p.\n",
                 reinterpret_cast<void*>(pc_));
         abort();
 
       } else {
         base::OS::DebugBreak();
       }
       break;
     }
 
     default:
       UNIMPLEMENTED();
   }
 }
 
 
 void Simulator::DoPrintf(Instruction* instr) {
-  ASSERT((instr->Mask(ExceptionMask) == HLT) &&
+  DCHECK((instr->Mask(ExceptionMask) == HLT) &&
               (instr->ImmException() == kImmExceptionIsPrintf));
 
   // Read the arguments encoded inline in the instruction stream.
   uint32_t arg_count;
   uint32_t arg_pattern_list;
   STATIC_ASSERT(sizeof(*instr) == 1);
   memcpy(&arg_count,
          instr + kPrintfArgCountOffset,
          sizeof(arg_count));
   memcpy(&arg_pattern_list,
          instr + kPrintfArgPatternListOffset,
          sizeof(arg_pattern_list));
 
-  ASSERT(arg_count <= kPrintfMaxArgCount);
-  ASSERT((arg_pattern_list >> (kPrintfArgPatternBits * arg_count)) == 0);
+  DCHECK(arg_count <= kPrintfMaxArgCount);
+  DCHECK((arg_pattern_list >> (kPrintfArgPatternBits * arg_count)) == 0);
 
   // We need to call the host printf function with a set of arguments defined by
   // arg_pattern_list. Because we don't know the types and sizes of the
   // arguments, this is very difficult to do in a robust and portable way. To
   // work around the problem, we pick apart the format string, and print one
   // format placeholder at a time.
 
   // Allocate space for the format string. We take a copy, so we can modify it.
   // Leave enough space for one extra character per expected argument (plus the
   // '\0' termination).
   const char * format_base = reg<const char *>(0);
-  ASSERT(format_base != NULL);
+  DCHECK(format_base != NULL);
   size_t length = strlen(format_base) + 1;
   char * const format = new char[length + arg_count];
 
   // A list of chunks, each with exactly one format placeholder.
   const char * chunks[kPrintfMaxArgCount];
 
   // Copy the format string and search for format placeholders.
   uint32_t placeholder_count = 0;
   char * format_scratch = format;
   for (size_t i = 0; i < length; i++) {
@@ skipping 14 matching lines @@
         }
       } else {
         CHECK(placeholder_count < arg_count);
         // Insert '\0' before placeholders, and store their locations.
         *format_scratch++ = '\0';
         chunks[placeholder_count++] = format_scratch;
         *format_scratch++ = format_base[i];
       }
     }
   }
-  ASSERT(format_scratch <= (format + length + arg_count));
+  DCHECK(format_scratch <= (format + length + arg_count));
   CHECK(placeholder_count == arg_count);
 
   // Finally, call printf with each chunk, passing the appropriate register
   // argument. Normally, printf returns the number of bytes transmitted, so we
   // can emulate a single printf call by adding the result from each chunk. If
   // any call returns a negative (error) value, though, just return that value.
 
   fprintf(stream_, "%s", clr_printf);
 
   // Because '\0' is inserted before each placeholder, the first string in
@@ skipping 47 matching lines @@
 
   delete[] format;
 }
 
 
 #endif  // USE_SIMULATOR
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_ARM64