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1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <limits.h> // For LONG_MIN, LONG_MAX. | 5 #include <limits.h> // For LONG_MIN, LONG_MAX. |
6 | 6 |
7 #include "src/v8.h" | 7 #include "src/v8.h" |
8 | 8 |
9 #if V8_TARGET_ARCH_ARM | 9 #if V8_TARGET_ARCH_ARM |
10 | 10 |
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247 } | 247 } |
248 } | 248 } |
249 | 249 |
250 | 250 |
251 void MacroAssembler::Mls(Register dst, Register src1, Register src2, | 251 void MacroAssembler::Mls(Register dst, Register src1, Register src2, |
252 Register srcA, Condition cond) { | 252 Register srcA, Condition cond) { |
253 if (CpuFeatures::IsSupported(MLS)) { | 253 if (CpuFeatures::IsSupported(MLS)) { |
254 CpuFeatureScope scope(this, MLS); | 254 CpuFeatureScope scope(this, MLS); |
255 mls(dst, src1, src2, srcA, cond); | 255 mls(dst, src1, src2, srcA, cond); |
256 } else { | 256 } else { |
257 ASSERT(!dst.is(srcA)); | 257 ASSERT(!srcA.is(ip)); |
258 mul(ip, src1, src2, LeaveCC, cond); | 258 mul(ip, src1, src2, LeaveCC, cond); |
259 sub(dst, srcA, ip, LeaveCC, cond); | 259 sub(dst, srcA, ip, LeaveCC, cond); |
260 } | 260 } |
261 } | 261 } |
262 | 262 |
263 | 263 |
264 void MacroAssembler::And(Register dst, Register src1, const Operand& src2, | 264 void MacroAssembler::And(Register dst, Register src1, const Operand& src2, |
265 Condition cond) { | 265 Condition cond) { |
266 if (!src2.is_reg() && | 266 if (!src2.is_reg() && |
267 !src2.must_output_reloc_info(this) && | 267 !src2.must_output_reloc_info(this) && |
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4103 sub(result, result, Operand(dividend)); | 4103 sub(result, result, Operand(dividend)); |
4104 } | 4104 } |
4105 if (ms.shift() > 0) mov(result, Operand(result, ASR, ms.shift())); | 4105 if (ms.shift() > 0) mov(result, Operand(result, ASR, ms.shift())); |
4106 add(result, result, Operand(dividend, LSR, 31)); | 4106 add(result, result, Operand(dividend, LSR, 31)); |
4107 } | 4107 } |
4108 | 4108 |
4109 | 4109 |
4110 } } // namespace v8::internal | 4110 } } // namespace v8::internal |
4111 | 4111 |
4112 #endif // V8_TARGET_ARCH_ARM | 4112 #endif // V8_TARGET_ARCH_ARM |
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