Add mips64 port.

src/mips64/assembler-mips64-inl.h

Index: src/mips64/assembler-mips64-inl.h
diff --git a/src/mips/assembler-mips-inl.h b/src/mips64/assembler-mips64-inl.h
similarity index 92%
copy from src/mips/assembler-mips-inl.h
copy to src/mips64/assembler-mips64-inl.h
index 086e55a6f48dee5fae170a69be02d28a74ea2ffe..776fe567910d52119fa74eff1bd51e9ad231ff8b 100644
--- a/src/mips/assembler-mips-inl.h
+++ b/src/mips64/assembler-mips64-inl.h
@@ -37,7 +37,7 @@
 #ifndef V8_MIPS_ASSEMBLER_MIPS_INL_H_
 #define V8_MIPS_ASSEMBLER_MIPS_INL_H_
 
-#include "src/mips/assembler-mips.h"
+#include "src/mips64/assembler-mips64.h"
 
 #include "src/assembler.h"
 #include "src/debug.h"
@@ -53,23 +53,23 @@ bool CpuFeatures::SupportsCrankshaft() { return IsSupported(FPU); }
 // -----------------------------------------------------------------------------
 // Operand and MemOperand.
 
-Operand::Operand(int32_t immediate, RelocInfo::Mode rmode)  {
+Operand::Operand(int64_t immediate, RelocInfo::Mode rmode)  {
   rm_ = no_reg;
-  imm32_ = immediate;
+  imm64_ = immediate;
   rmode_ = rmode;
 }
 
 
 Operand::Operand(const ExternalReference& f)  {
   rm_ = no_reg;
-  imm32_ = reinterpret_cast<int32_t>(f.address());
+  imm64_ = reinterpret_cast<int64_t>(f.address());
   rmode_ = RelocInfo::EXTERNAL_REFERENCE;
 }
 
 
 Operand::Operand(Smi* value) {
   rm_ = no_reg;
-  imm32_ =  reinterpret_cast<intptr_t>(value);
+  imm64_ =  reinterpret_cast<intptr_t>(value);
   rmode_ = RelocInfo::NONE32;
 }
 
@@ -113,14 +113,6 @@ int FPURegister::ToAllocationIndex(FPURegister reg) {
 // RelocInfo.
 
 void RelocInfo::apply(intptr_t delta, ICacheFlushMode icache_flush_mode) {
-  if (IsCodeTarget(rmode_)) {
-    uint32_t scope1 = (uint32_t) target_address() & ~kImm28Mask;
-    uint32_t scope2 = reinterpret_cast<uint32_t>(pc_) & ~kImm28Mask;
-
-    if (scope1 != scope2) {
-      Assembler::JumpLabelToJumpRegister(pc_);
-    }
-  }
   if (IsInternalReference(rmode_)) {
     // Absolute code pointer inside code object moves with the code object.
     byte* p = reinterpret_cast<byte*>(pc_);
@@ -155,8 +147,10 @@ Address RelocInfo::target_address_address() {
   // place, ready to be patched with the target. After jump optimization,
   // that is the address of the instruction that follows J/JAL/JR/JALR
   // instruction.
+  // return reinterpret_cast<Address>(
+  //  pc_ + Assembler::kInstructionsFor32BitConstant * Assembler::kInstrSize);
   return reinterpret_cast<Address>(
-    pc_ + Assembler::kInstructionsFor32BitConstant * Assembler::kInstrSize);
+    pc_ + Assembler::kInstructionsFor64BitConstant * Assembler::kInstrSize);
 }
 
 
@@ -269,7 +263,7 @@ void RelocInfo::set_target_cell(Cell* cell,
 }
 
 
-static const int kNoCodeAgeSequenceLength = 7 * Assembler::kInstrSize;
+static const int kNoCodeAgeSequenceLength = 9 * Assembler::kInstrSize;
 
 
 Handle<Object> RelocInfo::code_age_stub_handle(Assembler* origin) {
@@ -327,7 +321,7 @@ Object* RelocInfo::call_object() {
 Object** RelocInfo::call_object_address() {
   ASSERT((IsJSReturn(rmode()) && IsPatchedReturnSequence()) ||
          (IsDebugBreakSlot(rmode()) && IsPatchedDebugBreakSlotSequence()));
-  return reinterpret_cast<Object**>(pc_ + 2 * Assembler::kInstrSize);
+  return reinterpret_cast<Object**>(pc_ + 6 * Assembler::kInstrSize);
 }
 
 
@@ -346,14 +340,17 @@ void RelocInfo::WipeOut() {
 
 
 bool RelocInfo::IsPatchedReturnSequence() {
-  Instr instr0 = Assembler::instr_at(pc_);
-  Instr instr1 = Assembler::instr_at(pc_ + 1 * Assembler::kInstrSize);
-  Instr instr2 = Assembler::instr_at(pc_ + 2 * Assembler::kInstrSize);
+  Instr instr0 = Assembler::instr_at(pc_);  // lui.
+  Instr instr1 = Assembler::instr_at(pc_ + 1 * Assembler::kInstrSize);  // ori.
+  Instr instr2 = Assembler::instr_at(pc_ + 2 * Assembler::kInstrSize);  // dsll.
+  Instr instr3 = Assembler::instr_at(pc_ + 3 * Assembler::kInstrSize);  // ori.
+  Instr instr4 = Assembler::instr_at(pc_ + 4 * Assembler::kInstrSize);  // jalr.
+
   bool patched_return = ((instr0 & kOpcodeMask) == LUI &&
                          (instr1 & kOpcodeMask) == ORI &&
-                         ((instr2 & kOpcodeMask) == JAL ||
-                          ((instr2 & kOpcodeMask) == SPECIAL &&
-                           (instr2 & kFunctionFieldMask) == JALR)));
+                         (instr2 & kFunctionFieldMask) == DSLL &&
+                         (instr3 & kOpcodeMask) == ORI &&
+                         (instr4 & kFunctionFieldMask) == JALR);
   return patched_return;
 }
 
@@ -441,6 +438,16 @@ void Assembler::emit(Instr x) {
 }
 
 
+void Assembler::emit(uint64_t x) {
+  if (!is_buffer_growth_blocked()) {
+    CheckBuffer();
+  }
+  *reinterpret_cast<uint64_t*>(pc_) = x;
+  pc_ += kInstrSize * 2;
+  CheckTrampolinePoolQuick();
+}
+
+
 } }  // namespace v8::internal
 
 #endif  // V8_MIPS_ASSEMBLER_MIPS_INL_H_