Add mips64 port.

src/mips64/constants-mips64.cc

Index: src/mips64/constants-mips64.cc
diff --git a/src/mips/constants-mips.cc b/src/mips64/constants-mips64.cc
similarity index 91%
copy from src/mips/constants-mips.cc
copy to src/mips64/constants-mips64.cc
index f14992719dbf8a89c84e5dfac0070f7746cc8b3c..04f4bbc52f88960467c207917235b88463b1865a 100644
--- a/src/mips/constants-mips.cc
+++ b/src/mips64/constants-mips64.cc
@@ -4,9 +4,9 @@
 
 #include "src/v8.h"
 
-#if V8_TARGET_ARCH_MIPS
+#if V8_TARGET_ARCH_MIPS64
 
-#include "src/mips/constants-mips.h"
+#include "src/mips64/constants-mips64.h"
 
 namespace v8 {
 namespace internal {
@@ -22,8 +22,8 @@ const char* Registers::names_[kNumSimuRegisters] = {
   "zero_reg",
   "at",
   "v0", "v1",
-  "a0", "a1", "a2", "a3",
-  "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
+  "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
+  "t0", "t1", "t2", "t3",
   "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
   "t8", "t9",
   "k0", "k1",
@@ -222,21 +222,38 @@ Instruction::Type Instruction::InstructionType() const {
         case JALR:
         case BREAK:
         case SLL:
+        case DSLL:
+        case DSLL32:
         case SRL:
+        case DSRL:
+        case DSRL32:
         case SRA:
+        case DSRA:
+        case DSRA32:
         case SLLV:
+        case DSLLV:
         case SRLV:
+        case DSRLV:
         case SRAV:
+        case DSRAV:
         case MFHI:
         case MFLO:
         case MULT:
+        case DMULT:
         case MULTU:
+        case DMULTU:
         case DIV:
+        case DDIV:
         case DIVU:
+        case DDIVU:
         case ADD:
+        case DADD:
         case ADDU:
+        case DADDU:
         case SUB:
+        case DSUB:
         case SUBU:
+        case DSUBU:
         case AND:
         case OR:
         case XOR:
@@ -292,7 +309,9 @@ Instruction::Type Instruction::InstructionType() const {
     case BLEZ:
     case BGTZ:
     case ADDI:
+    case DADDI:
     case ADDIU:
+    case DADDIU:
     case SLTI:
     case SLTIU:
     case ANDI:
@@ -307,6 +326,8 @@ Instruction::Type Instruction::InstructionType() const {
     case LH:
     case LWL:
     case LW:
+    case LWU:
+    case LD:
     case LBU:
     case LHU:
     case LWR:
@@ -314,6 +335,7 @@ Instruction::Type Instruction::InstructionType() const {
     case SH:
     case SWL:
     case SW:
+    case SD:
     case SWR:
     case LWC1:
     case LDC1:
@@ -333,4 +355,4 @@ Instruction::Type Instruction::InstructionType() const {
 
 } }   // namespace v8::internal
 
-#endif  // V8_TARGET_ARCH_MIPS
+#endif  // V8_TARGET_ARCH_MIPS64