Add mips64 port.

src/mips64/constants-mips64.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/v8.h"
 
-#if V8_TARGET_ARCH_MIPS
+#if V8_TARGET_ARCH_MIPS64
 
-#include "src/mips/constants-mips.h"
+#include "src/mips64/constants-mips64.h"
 
 namespace v8 {
 namespace internal {
 
 
 // -----------------------------------------------------------------------------
 // Registers.
 
 
 // These register names are defined in a way to match the native disassembler
 // formatting. See for example the command "objdump -d <binary file>".
 const char* Registers::names_[kNumSimuRegisters] = {
   "zero_reg",
   "at",
   "v0", "v1",
-  "a0", "a1", "a2", "a3",
-  "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
+  "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
+  "t0", "t1", "t2", "t3",
   "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
   "t8", "t9",
   "k0", "k1",
   "gp",
   "sp",
   "fp",
   "ra",
   "LO", "HI",
   "pc"
 };
@@ skipping 178 matching lines @@
 
 
 Instruction::Type Instruction::InstructionType() const {
   switch (OpcodeFieldRaw()) {
     case SPECIAL:
       switch (FunctionFieldRaw()) {
         case JR:
         case JALR:
         case BREAK:
         case SLL:
+        case DSLL:
+        case DSLL32:
         case SRL:
+        case DSRL:
+        case DSRL32:
         case SRA:
+        case DSRA:
+        case DSRA32:
         case SLLV:
+        case DSLLV:
         case SRLV:
+        case DSRLV:
         case SRAV:
+        case DSRAV:
         case MFHI:
         case MFLO:
         case MULT:
+        case DMULT:
         case MULTU:
+        case DMULTU:
         case DIV:
+        case DDIV:
         case DIVU:
+        case DDIVU:
         case ADD:
+        case DADD:
         case ADDU:
+        case DADDU:
         case SUB:
+        case DSUB:
         case SUBU:
+        case DSUBU:
         case AND:
         case OR:
         case XOR:
         case NOR:
         case SLT:
         case SLTU:
         case TGE:
         case TGEU:
         case TLT:
         case TLTU:
@@ skipping 35 matching lines @@
       break;
     case COP1X:
       return kRegisterType;
     // 16 bits Immediate type instructions. e.g.: addi dest, src, imm16.
     case REGIMM:
     case BEQ:
     case BNE:
     case BLEZ:
     case BGTZ:
     case ADDI:
+    case DADDI:
     case ADDIU:
+    case DADDIU:
     case SLTI:
     case SLTIU:
     case ANDI:
     case ORI:
     case XORI:
     case LUI:
     case BEQL:
     case BNEL:
     case BLEZL:
     case BGTZL:
     case LB:
     case LH:
     case LWL:
     case LW:
+    case LWU:
+    case LD:
     case LBU:
     case LHU:
     case LWR:
     case SB:
     case SH:
     case SWL:
     case SW:
+    case SD:
     case SWR:
     case LWC1:
     case LDC1:
     case SWC1:
     case SDC1:
       return kImmediateType;
     // 26 bits immediate type instructions. e.g.: j imm26.
     case J:
     case JAL:
       return kJumpType;
     default:
       return kUnsupported;
   }
   return kUnsupported;
 }
 
 
 } }   // namespace v8::internal
 
-#endif  // V8_TARGET_ARCH_MIPS
+#endif  // V8_TARGET_ARCH_MIPS64