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Unified Diff: tests_lit/llvm2ice_tests/vector-const.ll

Issue 353553004: Add support for vector types and vector constants. (Closed) Base URL: https://gerrit.chromium.org/gerrit/p/native_client/pnacl-subzero.git@master
Patch Set: Created 6 years, 6 months ago
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« src/IceTypes.def ('K') | « src/llvm2ice.cpp ('k') | tests_lit/llvm2ice_tests/vector-pool.ll » ('j') | no next file with comments »
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Index: tests_lit/llvm2ice_tests/vector-const.ll
diff --git a/tests_lit/llvm2ice_tests/vector-const.ll b/tests_lit/llvm2ice_tests/vector-const.ll
new file mode 100644
index 0000000000000000000000000000000000000000..42c32f7fe23efb83621bd6a069ff8bd32c31896e
--- /dev/null
+++ b/tests_lit/llvm2ice_tests/vector-const.ll
@@ -0,0 +1,182 @@
+; This file tests that vector constants are represented correctly. It
+; is not meant to be valid PNaCl IR or to be lowered to assembly.
+
+; RUN: %llvm2ice --verbose inst %s | FileCheck %s
+; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
+; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
+
+define <4 x i1> @test_v4i1(i32 %arg) {
+entry:
+ switch i32 %arg, label %zeros [
+ i32 0, label %intmax
+ i32 1, label %incr
+ i32 2, label %decr
+ i32 3, label %random
+ i32 4, label %alternating
+ ]
+intmax:
+ ret <4 x i1> <i1 1, i1 1, i1 1, i1 1>
+incr:
+ ret <4 x i1> <i1 0, i1 1, i1 0, i1 1>
+decr:
+ ret <4 x i1> <i1 1, i1 0, i1 1, i1 0>
+random:
+ ret <4 x i1> <i1 0, i1 0, i1 1, i1 0>
+alternating:
+ ret <4 x i1> <i1 0, i1 1, i1 0, i1 1>
+zeros:
+ ret <4 x i1> <i1 0, i1 0, i1 0, i1 0>
+}
+
+define <8 x i1> @test_v8i1(i32 %arg) {
+entry:
+ switch i32 %arg, label %zeros [
+ i32 0, label %intmax
+ i32 1, label %incr
+ i32 2, label %decr
+ i32 3, label %random
+ i32 4, label %alternating
+ ]
+intmax:
+ ret <8 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>
+incr:
+ ret <8 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>
+decr:
+ ret <8 x i1> <i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0>
+random:
+ ret <8 x i1> <i1 0, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0>
+alternating:
+ ret <8 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>
+zeros:
+ ret <8 x i1> <i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0>
+}
+
+define <16 x i1> @test_v16i1(i32 %arg) {
+entry:
+ switch i32 %arg, label %zeros [
+ i32 0, label %intmax
+ i32 1, label %incr
+ i32 2, label %decr
+ i32 3, label %random
+ i32 4, label %alternating
+ ]
+intmax:
+ ret <16 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>
+incr:
+ ret <16 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>
+decr:
+ ret <16 x i1> <i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0>
+random:
+ ret <16 x i1> <i1 0, i1 1, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 1, i1 1>
+alternating:
+ ret <16 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1 1>
+zeros:
+ ret <16 x i1> <i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0>
+}
+
+define <16 x i8> @test_v16i8(i32 %arg) {
+entry:
+ switch i32 %arg, label %zeros [
+ i32 0, label %intmax
+ i32 1, label %incr
+ i32 2, label %decr
+ i32 3, label %random
+ i32 4, label %alternating
+ ]
+intmax:
+ ret <16 x i8> <i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255>
+incr:
+ ret <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>
+decr:
+ ret <16 x i8> <i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+random:
+ ret <16 x i8> <i8 63, i8 75, i8 126, i8 187, i8 79, i8 241, i8 98, i8 155, i8 251, i8 46, i8 116, i8 100, i8 155, i8 187, i8 165, i8 212>
+alternating:
+ ret <16 x i8> <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
+zeros:
+ ret <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
+}
+
+define <8 x i16> @test_v8i16(i32 %arg) {
+entry:
+ switch i32 %arg, label %zeros [
+ i32 0, label %intmax
+ i32 1, label %incr
+ i32 2, label %decr
+ i32 3, label %random
+ i32 4, label %alternating
+ ]
+intmax:
+ ret <8 x i16> <i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535>
+incr:
+ ret <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+decr:
+ ret <8 x i16> <i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>
+random:
+ ret <8 x i16> <i16 32306, i16 22920, i16 36561, i16 44370, i16 1518, i16 22922, i16 26454, i16 29426>
+alternating:
+ ret <8 x i16> <i16 0, i16 65535, i16 0, i16 65535, i16 0, i16 65535, i16 0, i16 65535>
+zeros:
+ ret <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
+}
+
+define <4 x i32> @test_v4i32(i32 %arg) {
+entry:
+ switch i32 %arg, label %zeros [
+ i32 0, label %intmax
+ i32 1, label %incr
+ i32 2, label %decr
+ i32 3, label %random
+ i32 4, label %alternating
+ ]
+intmax:
+ ret <4 x i32> <i32 4294967295, i32 4294967295, i32 4294967295, i32 4294967295>
+incr:
+ ret <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+decr:
+ ret <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+random:
+ ret <4 x i32> <i32 3639884198, i32 2963421555, i32 3743370439, i32 2521435933>
+alternating:
+ ret <4 x i32> <i32 0, i32 4294967295, i32 0, i32 4294967295>
+zeros:
+ ret <4 x i32> <i32 0, i32 0, i32 0, i32 0>
+}
+
+; The CHECK lines are in this function because szdiff ignores lines
+; containing float constants.
+define <4 x float> @test_v4f32(i32 %arg) {
+entry:
+ switch i32 %arg, label %zeros [
+ i32 0, label %extremes
+ i32 1, label %incr
+ i32 2, label %decr
+ i32 3, label %random
+ i32 5, label %nan
+ i32 6, label %negzero
+ ]
+extremes:
+ ret <4 x float> <float 0x7FF0000000000000, float 0x47EFFFFFE0000000, float 0x3810000000000000, float 0xFFF0000000000000>
+; CHECK: ret <4 x float> <float inf, float 3.402823e+38, float 1.175494e-38, float -inf>
+incr:
+ ret <4 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
+; CHECK: ret <4 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
+decr:
+ ret <4 x float> <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
+; CHECK: ret <4 x float> <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
+random:
+ ret <4 x float> <float 1.500000e+00, float 4.250000e+00, float -1.562500e-02, float -3.209375e+01>
+; CHECK: ret <4 x float> <float 1.500000e+00, float 4.250000e+00, float -1.562500e-02, float -3.209375e+01>
+nan:
+ ret <4 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x7FF8000000000000>
+; CHECK: ret <4 x float> <float nan, float nan, float nan, float nan>
+negzero:
+ ret <4 x float> <float 0.000000e+00, float -0.000000e+00, float 0.000000e+00, float 0.000000e+00>
+; CHECK: ret <4 x float> <float 0.000000e+00, float -0.000000e+00, float 0.000000e+00, float 0.000000e+00>
+zeros:
+ ret <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>
+; CHECK: ret <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>
+}
+
+; ERRORS-NOT: ICE translation error
+; DUMP-NOT: SZ
« src/IceTypes.def ('K') | « src/llvm2ice.cpp ('k') | tests_lit/llvm2ice_tests/vector-pool.ll » ('j') | no next file with comments »

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