| Index: src/base/atomicops_internals_x86_gcc.h
|
| ===================================================================
|
| --- src/base/atomicops_internals_x86_gcc.h (revision 21880)
|
| +++ src/base/atomicops_internals_x86_gcc.h (working copy)
|
| @@ -17,7 +17,9 @@
|
| struct AtomicOps_x86CPUFeatureStruct {
|
| bool has_amd_lock_mb_bug; // Processor has AMD memory-barrier bug; do lfence
|
| // after acquire compare-and-swap.
|
| +#if !defined(__SSE2__)
|
| bool has_sse2; // Processor has SSE2.
|
| +#endif
|
| };
|
| extern struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures;
|
|
|
| @@ -92,7 +94,7 @@
|
| *ptr = value;
|
| }
|
|
|
| -#if defined(__x86_64__)
|
| +#if defined(__x86_64__) || defined(__SSE2__)
|
|
|
| // 64-bit implementations of memory barrier can be simpler, because it
|
| // "mfence" is guaranteed to exist.
|
|
|