| Index: src/base/atomicops_internals_x86_gcc.cc
|
| ===================================================================
|
| --- src/base/atomicops_internals_x86_gcc.cc (revision 21880)
|
| +++ src/base/atomicops_internals_x86_gcc.cc (working copy)
|
| @@ -88,9 +88,10 @@
|
| } else {
|
| AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = false;
|
| }
|
| -
|
| +#if !defined(__SSE2__)
|
| // edx bit 26 is SSE2 which we use to tell use whether we can use mfence
|
| AtomicOps_Internalx86CPUFeatures.has_sse2 = ((edx >> 26) & 1);
|
| +#endif
|
| }
|
|
|
| class AtomicOpsx86Initializer {
|
|
|