ARM: add AArch32 support and new vcvt instructions

test/cctest/test-disasm-arm.cc

Index: test/cctest/test-disasm-arm.cc
diff --git a/test/cctest/test-disasm-arm.cc b/test/cctest/test-disasm-arm.cc
index c1f6ce26907ffa10afcc5acb92e2af3a6e92fc05..55135ad2094bcbf240d22192fdeb902acb566625 100644
--- a/test/cctest/test-disasm-arm.cc
+++ b/test/cctest/test-disasm-arm.cc
@@ -904,3 +904,29 @@ TEST(LoadStore) {
 
   VERIFY_RUN();
 }
+
+
+TEST(AArch32) {
+  SET_UP();
+
+  if (CpuFeatures::IsSupported(ARMv8)) {
+      COMPARE(vcvta_s32_f64(s2, d0),
+              "febc1bc0       vcvta.s32.f64 s2, d0");
+      COMPARE(vcvtn_s32_f64(s3, d4),
+              "fefd1bc4       vcvtn.s32.f64 s3, d4");
+      COMPARE(vcvtp_s32_f64(s6, d5),
+              "febe3bc5       vcvtp.s32.f64 s6, d5");
+      COMPARE(vcvtm_s32_f64(s7, d8),
+              "feff3bc8       vcvtm.s32.f64 s7, d8");
+      COMPARE(vcvta_u32_f64(s18, d20),
+              "febc9b64       vcvta.u32.f64 s18, d20");
+      COMPARE(vcvtn_u32_f64(s21, d30),
+              "fefdab6e       vcvtn.u32.f64 s21, d30");
+      COMPARE(vcvtp_u32_f64(s22, d31),
+              "febebb6f       vcvtp.u32.f64 s22, d31");
+      COMPARE(vcvtm_u32_f64(s31, d31),
+              "fefffb6f       vcvtm.u32.f64 s31, d31");
+  }
+
+  VERIFY_RUN();
+}