ARM: add AArch32 support and new vcvt instructions

test/cctest/test-disasm-arm.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 886 matching lines @@
             "e16dc7ff       strd ip, [sp, #-127]!");
 
     COMPARE(pld(MemOperand(r1, 0)),
             "f5d1f000       pld [r1]");
     COMPARE(pld(MemOperand(r2, 128)),
             "f5d2f080       pld [r2, #+128]");
   }
 
   VERIFY_RUN();
 }
+
+
+TEST(AArch32) {
+  SET_UP();
+
+  if (CpuFeatures::IsSupported(ARMv8)) {
+      COMPARE(vcvta_s32_f64(s2, d0),
+              "febc1bc0       vcvta.s32.f64 s2, d0");
+      COMPARE(vcvtn_s32_f64(s3, d4),
+              "fefd1bc4       vcvtn.s32.f64 s3, d4");
+      COMPARE(vcvtp_s32_f64(s6, d5),
+              "febe3bc5       vcvtp.s32.f64 s6, d5");
+      COMPARE(vcvtm_s32_f64(s7, d8),
+              "feff3bc8       vcvtm.s32.f64 s7, d8");
+      COMPARE(vcvta_u32_f64(s18, d20),
+              "febc9b64       vcvta.u32.f64 s18, d20");
+      COMPARE(vcvtn_u32_f64(s21, d30),
+              "fefdab6e       vcvtn.u32.f64 s21, d30");
+      COMPARE(vcvtp_u32_f64(s22, d31),
+              "febebb6f       vcvtp.u32.f64 s22, d31");
+      COMPARE(vcvtm_u32_f64(s31, d31),
+              "fefffb6f       vcvtm.u32.f64 s31, d31");
+  }
+
+  VERIFY_RUN();
+}