ARM: add AArch32 support and new vcvt instructions

src/arm/assembler-arm.cc

Index: src/arm/assembler-arm.cc
diff --git a/src/arm/assembler-arm.cc b/src/arm/assembler-arm.cc
index c3f9ab0b9b2501997a7f83d154b1607c6fad6ca3..13d814ba3316aa1991128cf86de225100e3591bf 100644
--- a/src/arm/assembler-arm.cc
+++ b/src/arm/assembler-arm.cc
@@ -46,11 +46,14 @@ namespace v8 {
 namespace internal {
 
 // Get the CPU features enabled by the build. For cross compilation the
-// preprocessor symbols CAN_USE_ARMV7_INSTRUCTIONS and CAN_USE_VFP3_INSTRUCTIONS
-// can be defined to enable ARMv7 and VFPv3 instructions when building the
-// snapshot.
+// preprocessor symbols CAN_USE_ARMV8_INSTRUCTIONS, CAN_USE_ARMV7_INSTRUCTIONS
+// and CAN_USE_VFP3_INSTRUCTIONS can be defined to enable ARMv8, ARMv7 and VFPv3
+// instructions when building the snapshot.
 static unsigned CpuFeaturesImpliedByCompiler() {
   unsigned answer = 0;
+#ifdef CAN_USE_ARMV8_INSTRUCTIONS
+  if (FLAG_enable_armv8) answer |= 1u << ARMv8;
+#endif  // CAN_USE_ARMV8_INSTRUCTIONS
 #ifdef CAN_USE_ARMV7_INSTRUCTIONS
   if (FLAG_enable_armv7) answer |= 1u << ARMv7;
 #endif  // CAN_USE_ARMV7_INSTRUCTIONS
@@ -81,7 +84,8 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
 
 #ifndef __arm__
   // For the simulator build, use whatever the flags specify.
-  if (FLAG_enable_armv7) {
+  if (FLAG_enable_armv7 || FLAG_enable_armv8) {
+    if (FLAG_enable_armv8) supported_ |= 1u << ARMv8;
     supported_ |= 1u << ARMv7;
     if (FLAG_enable_vfp3) supported_ |= 1u << VFP3;
     if (FLAG_enable_neon) supported_ |= 1u << NEON | 1u << VFP32DREGS;
@@ -105,6 +109,9 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
   if (FLAG_enable_sudiv && cpu.has_idiva()) supported_ |= 1u << SUDIV;
 
   if (cpu.architecture() >= 7) {
+    if ((cpu.architecture() >= 8) && FLAG_enable_armv8) {
+      supported_ |= 1u << ARMv8;
+    }
     if (FLAG_enable_armv7) supported_ |= 1u << ARMv7;
     if (FLAG_enable_unaligned_accesses) supported_ |= 1u << UNALIGNED_ACCESSES;
     // Use movw/movt for QUALCOMM ARMv7 cores.
@@ -133,7 +140,9 @@ void CpuFeatures::PrintTarget() {
   const char* arm_thumb = "";
   const char* arm_float_abi = NULL;
 
-#if defined CAN_USE_ARMV7_INSTRUCTIONS
+#if defined CAN_USE_ARMV8_INSTRUCTIONS
+  arm_arch = "arm v8";
+#elif defined CAN_USE_ARMV7_INSTRUCTIONS
   arm_arch = "arm v7";
 #else
   arm_arch = "arm v6";
@@ -183,8 +192,9 @@ void CpuFeatures::PrintTarget() {
 
 void CpuFeatures::PrintFeatures() {
   printf(
-    "ARMv7=%d VFP3=%d VFP32DREGS=%d NEON=%d SUDIV=%d UNALIGNED_ACCESSES=%d "
-    "MOVW_MOVT_IMMEDIATE_LOADS=%d",
+    "ARMv8=%d ARMv7=%d VFP3=%d VFP32DREGS=%d NEON=%d SUDIV=%d "
+    "UNALIGNED_ACCESSES=%d MOVW_MOVT_IMMEDIATE_LOADS=%d",
+    CpuFeatures::IsSupported(ARMv8),
     CpuFeatures::IsSupported(ARMv7),
     CpuFeatures::IsSupported(VFP3),
     CpuFeatures::IsSupported(VFP32DREGS),
@@ -2760,6 +2770,76 @@ void Assembler::vcvt_f64_s32(const DwVfpRegister dst,
 }
 
 
+static Instr AArch32EncodeVCVT(const SwVfpRegister dst,
+                               const DwVfpRegister src,
+                               VCVTDataType data_type,
+                               VCVTRoundingMode rounding_mode) {
+  int vd, d;
+  dst.split_code(&vd, &d);
+  int vm, m;
+  src.split_code(&vm, &m);
+  return
+      0xFU*B28 | 0x1D*B23 | d*B22 | 0x3*B20 | 0x3*B18 | rounding_mode*B16 |
+      vd*B12 | 0x5*B9 | B8 | data_type*B7 | B6 | m*B5 | vm;
+}
+
+
+void Assembler::vcvta_s32_f64(const SwVfpRegister dst,
+                              const DwVfpRegister src) {
+  ASSERT(CpuFeatures::IsSupported(ARMv8));
+  emit(AArch32EncodeVCVT(dst, src, kVcvtSigned, kVcvtTiesToAway));
+}
+
+
+void Assembler::vcvta_u32_f64(const SwVfpRegister dst,
+                              const DwVfpRegister src) {
+  ASSERT(CpuFeatures::IsSupported(ARMv8));
+  emit(AArch32EncodeVCVT(dst, src, kVcvtUnsigned, kVcvtTiesToAway));
+}
+
+
+void Assembler::vcvtm_s32_f64(const SwVfpRegister dst,
+                              const DwVfpRegister src) {
+  ASSERT(CpuFeatures::IsSupported(ARMv8));
+  emit(AArch32EncodeVCVT(dst, src, kVcvtSigned, kVcvtTowardMinusInfinity));
+}
+
+
+void Assembler::vcvtm_u32_f64(const SwVfpRegister dst,
+                              const DwVfpRegister src) {
+  ASSERT(CpuFeatures::IsSupported(ARMv8));
+  emit(AArch32EncodeVCVT(dst, src, kVcvtUnsigned, kVcvtTowardMinusInfinity));
+}
+
+
+void Assembler::vcvtn_s32_f64(const SwVfpRegister dst,
+                              const DwVfpRegister src) {
+  ASSERT(CpuFeatures::IsSupported(ARMv8));
+  emit(AArch32EncodeVCVT(dst, src, kVcvtSigned, kVcvtTiesToEven));
+}
+
+
+void Assembler::vcvtn_u32_f64(const SwVfpRegister dst,
+                              const DwVfpRegister src) {
+  ASSERT(CpuFeatures::IsSupported(ARMv8));
+  emit(AArch32EncodeVCVT(dst, src, kVcvtUnsigned, kVcvtTiesToEven));
+}
+
+
+void Assembler::vcvtp_s32_f64(const SwVfpRegister dst,
+                              const DwVfpRegister src) {
+  ASSERT(CpuFeatures::IsSupported(ARMv8));
+  emit(AArch32EncodeVCVT(dst, src, kVcvtSigned, kVcvtTowardPlusInfinity));
+}
+
+
+void Assembler::vcvtp_u32_f64(const SwVfpRegister dst,
+                              const DwVfpRegister src) {
+  ASSERT(CpuFeatures::IsSupported(ARMv8));
+  emit(AArch32EncodeVCVT(dst, src, kVcvtUnsigned, kVcvtTowardPlusInfinity));
+}
+
+
 void Assembler::vneg(const DwVfpRegister dst,
                      const DwVfpRegister src,
                      const Condition cond) {