ARM: add AArch32 support and new vcvt instructions

src/arm/assembler-arm.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 28 matching lines @@
 #if V8_TARGET_ARCH_ARM
 
 #include "src/arm/assembler-arm-inl.h"
 #include "src/macro-assembler.h"
 #include "src/serialize.h"
 
 namespace v8 {
 namespace internal {
 
 // Get the CPU features enabled by the build. For cross compilation the
-// preprocessor symbols CAN_USE_ARMV7_INSTRUCTIONS and CAN_USE_VFP3_INSTRUCTIONS
-// can be defined to enable ARMv7 and VFPv3 instructions when building the
-// snapshot.
+// preprocessor symbols CAN_USE_ARMV8_INSTRUCTIONS, CAN_USE_ARMV7_INSTRUCTIONS
+// and CAN_USE_VFP3_INSTRUCTIONS can be defined to enable ARMv8, ARMv7 and VFPv3
+// instructions when building the snapshot.
 static unsigned CpuFeaturesImpliedByCompiler() {
   unsigned answer = 0;
+#ifdef CAN_USE_ARMV8_INSTRUCTIONS
+  if (FLAG_enable_armv8) answer |= 1u << ARMv8;
+#endif  // CAN_USE_ARMV8_INSTRUCTIONS
 #ifdef CAN_USE_ARMV7_INSTRUCTIONS
   if (FLAG_enable_armv7) answer |= 1u << ARMv7;
 #endif  // CAN_USE_ARMV7_INSTRUCTIONS
 #ifdef CAN_USE_VFP3_INSTRUCTIONS
   if (FLAG_enable_vfp3) answer |= 1u << VFP3 | 1u << ARMv7;
 #endif  // CAN_USE_VFP3_INSTRUCTIONS
 #ifdef CAN_USE_VFP32DREGS
   if (FLAG_enable_32dregs) answer |= 1u << VFP32DREGS;
 #endif  // CAN_USE_VFP32DREGS
 #ifdef CAN_USE_NEON
@@ skipping 10 matching lines @@
 void CpuFeatures::ProbeImpl(bool cross_compile) {
   supported_ |= OS::CpuFeaturesImpliedByPlatform();
   supported_ |= CpuFeaturesImpliedByCompiler();
   cache_line_size_ = 64;
 
   // Only use statically determined features for cross compile (snapshot).
   if (cross_compile) return;
 
 #ifndef __arm__
   // For the simulator build, use whatever the flags specify.
-  if (FLAG_enable_armv7) {
+  if (FLAG_enable_armv7 || FLAG_enable_armv8) {
+    if (FLAG_enable_armv8) supported_ |= 1u << ARMv8;
     supported_ |= 1u << ARMv7;
     if (FLAG_enable_vfp3) supported_ |= 1u << VFP3;
     if (FLAG_enable_neon) supported_ |= 1u << NEON | 1u << VFP32DREGS;
     if (FLAG_enable_sudiv)  supported_ |= 1u << SUDIV;
     if (FLAG_enable_movw_movt) supported_ |= 1u << MOVW_MOVT_IMMEDIATE_LOADS;
     if (FLAG_enable_32dregs) supported_ |= 1u << VFP32DREGS;
   }
   if (FLAG_enable_unaligned_accesses) supported_ |= 1u << UNALIGNED_ACCESSES;
 
 #else  // __arm__
   // Probe for additional features at runtime.
   CPU cpu;
   if (FLAG_enable_vfp3 && cpu.has_vfp3()) {
     // This implementation also sets the VFP flags if runtime
     // detection of VFP returns true. VFPv3 implies ARMv7, see ARM DDI
     // 0406B, page A1-6.
     supported_ |= 1u << VFP3 | 1u << ARMv7;
   }
 
   if (FLAG_enable_neon && cpu.has_neon()) supported_ |= 1u << NEON;
   if (FLAG_enable_sudiv && cpu.has_idiva()) supported_ |= 1u << SUDIV;
 
   if (cpu.architecture() >= 7) {
+    if ((cpu.architecture() >= 8) && FLAG_enable_armv8) {
+      supported_ |= 1u << ARMv8;
+    }
     if (FLAG_enable_armv7) supported_ |= 1u << ARMv7;
     if (FLAG_enable_unaligned_accesses) supported_ |= 1u << UNALIGNED_ACCESSES;
     // Use movw/movt for QUALCOMM ARMv7 cores.
     if (FLAG_enable_movw_movt && cpu.implementer() == CPU::QUALCOMM) {
       supported_ |= 1u << MOVW_MOVT_IMMEDIATE_LOADS;
     }
   }
 
   // ARM Cortex-A9 and Cortex-A5 have 32 byte cachelines.
   if (cpu.implementer() == CPU::ARM && (cpu.part() == CPU::ARM_CORTEX_A5 ||
                                         cpu.part() == CPU::ARM_CORTEX_A9)) {
     cache_line_size_ = 32;
   }
 
   if (FLAG_enable_32dregs && cpu.has_vfp3_d32()) supported_ |= 1u << VFP32DREGS;
 #endif
 
   ASSERT(!IsSupported(VFP3) || IsSupported(ARMv7));
 }
 
 
 void CpuFeatures::PrintTarget() {
   const char* arm_arch = NULL;
   const char* arm_test = "";
   const char* arm_fpu = "";
   const char* arm_thumb = "";
   const char* arm_float_abi = NULL;
 
-#if defined CAN_USE_ARMV7_INSTRUCTIONS
+#if defined CAN_USE_ARMV8_INSTRUCTIONS
+  arm_arch = "arm v8";
+#elif defined CAN_USE_ARMV7_INSTRUCTIONS
   arm_arch = "arm v7";
 #else
   arm_arch = "arm v6";
 #endif
 
 #ifdef __arm__
 
 # ifdef ARM_TEST
   arm_test = " test";
 # endif
@@ skipping 29 matching lines @@
 
 #endif  // __arm__
 
   printf("target%s %s%s%s %s\n",
          arm_test, arm_arch, arm_fpu, arm_thumb, arm_float_abi);
 }
 
 
 void CpuFeatures::PrintFeatures() {
   printf(
-    "ARMv7=%d VFP3=%d VFP32DREGS=%d NEON=%d SUDIV=%d UNALIGNED_ACCESSES=%d "
-    "MOVW_MOVT_IMMEDIATE_LOADS=%d",
+    "ARMv8=%d ARMv7=%d VFP3=%d VFP32DREGS=%d NEON=%d SUDIV=%d "
+    "UNALIGNED_ACCESSES=%d MOVW_MOVT_IMMEDIATE_LOADS=%d",
+    CpuFeatures::IsSupported(ARMv8),
     CpuFeatures::IsSupported(ARMv7),
     CpuFeatures::IsSupported(VFP3),
     CpuFeatures::IsSupported(VFP32DREGS),
     CpuFeatures::IsSupported(NEON),
     CpuFeatures::IsSupported(SUDIV),
     CpuFeatures::IsSupported(UNALIGNED_ACCESSES),
     CpuFeatures::IsSupported(MOVW_MOVT_IMMEDIATE_LOADS));
 #ifdef __arm__
   bool eabi_hardfloat = OS::ArmUsingHardFloat();
 #elif USE_EABI_HARDFLOAT
@@ skipping 2555 matching lines @@
   int vd, d;
   dst.split_code(&vd, &d);
   int imm5 = 32 - fraction_bits;
   int i = imm5 & 1;
   int imm4 = (imm5 >> 1) & 0xf;
   emit(cond | 0xE*B24 | B23 | d*B22 | 0x3*B20 | B19 | 0x2*B16 |
        vd*B12 | 0x5*B9 | B8 | B7 | B6 | i*B5 | imm4);
 }
 
 
+static Instr AArch32EncodeVCVT(const SwVfpRegister dst,
+                               const DwVfpRegister src,
+                               VCVTDataType data_type,
+                               VCVTRoundingMode rounding_mode) {
+  int vd, d;
+  dst.split_code(&vd, &d);
+  int vm, m;
+  src.split_code(&vm, &m);
+  return
+      0xFU*B28 | 0x1D*B23 | d*B22 | 0x3*B20 | 0x3*B18 | rounding_mode*B16 |
+      vd*B12 | 0x5*B9 | B8 | data_type*B7 | B6 | m*B5 | vm;
+}
+
+
+void Assembler::vcvta_s32_f64(const SwVfpRegister dst,
+                              const DwVfpRegister src) {
+  ASSERT(CpuFeatures::IsSupported(ARMv8));
+  emit(AArch32EncodeVCVT(dst, src, kVcvtSigned, kVcvtTiesToAway));
+}
+
+
+void Assembler::vcvta_u32_f64(const SwVfpRegister dst,
+                              const DwVfpRegister src) {
+  ASSERT(CpuFeatures::IsSupported(ARMv8));
+  emit(AArch32EncodeVCVT(dst, src, kVcvtUnsigned, kVcvtTiesToAway));
+}
+
+
+void Assembler::vcvtm_s32_f64(const SwVfpRegister dst,
+                              const DwVfpRegister src) {
+  ASSERT(CpuFeatures::IsSupported(ARMv8));
+  emit(AArch32EncodeVCVT(dst, src, kVcvtSigned, kVcvtTowardMinusInfinity));
+}
+
+
+void Assembler::vcvtm_u32_f64(const SwVfpRegister dst,
+                              const DwVfpRegister src) {
+  ASSERT(CpuFeatures::IsSupported(ARMv8));
+  emit(AArch32EncodeVCVT(dst, src, kVcvtUnsigned, kVcvtTowardMinusInfinity));
+}
+
+
+void Assembler::vcvtn_s32_f64(const SwVfpRegister dst,
+                              const DwVfpRegister src) {
+  ASSERT(CpuFeatures::IsSupported(ARMv8));
+  emit(AArch32EncodeVCVT(dst, src, kVcvtSigned, kVcvtTiesToEven));
+}
+
+
+void Assembler::vcvtn_u32_f64(const SwVfpRegister dst,
+                              const DwVfpRegister src) {
+  ASSERT(CpuFeatures::IsSupported(ARMv8));
+  emit(AArch32EncodeVCVT(dst, src, kVcvtUnsigned, kVcvtTiesToEven));
+}
+
+
+void Assembler::vcvtp_s32_f64(const SwVfpRegister dst,
+                              const DwVfpRegister src) {
+  ASSERT(CpuFeatures::IsSupported(ARMv8));
+  emit(AArch32EncodeVCVT(dst, src, kVcvtSigned, kVcvtTowardPlusInfinity));
+}
+
+
+void Assembler::vcvtp_u32_f64(const SwVfpRegister dst,
+                              const DwVfpRegister src) {
+  ASSERT(CpuFeatures::IsSupported(ARMv8));
+  emit(AArch32EncodeVCVT(dst, src, kVcvtUnsigned, kVcvtTowardPlusInfinity));
+}
+
+
 void Assembler::vneg(const DwVfpRegister dst,
                      const DwVfpRegister src,
                      const Condition cond) {
   // Instruction details available in ARM DDI 0406C.b, A8-968.
   // cond(31-28) | 11101(27-23) | D(22) | 11(21-20) | 0001(19-16) | Vd(15-12) |
   // 101(11-9) | sz=1(8) | 0(7) | 1(6) | M(5) | 0(4) | Vm(3-0)
   int vd, d;
   dst.split_code(&vd, &d);
   int vm, m;
   src.split_code(&vm, &m);
@@ skipping 889 matching lines @@
   ASSERT((index_64bit == count_of_64bit_) &&
          (index_code_ptr == (index_64bit + count_of_code_ptr_)) &&
          (index_heap_ptr == (index_code_ptr + count_of_heap_ptr_)) &&
          (index_32bit == (index_heap_ptr + count_of_32bit_)));
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_ARM